CN107689359A - 包括具有嵌入芯片的再布线层的半导体封装件 - Google Patents

包括具有嵌入芯片的再布线层的半导体封装件 Download PDF

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Publication number
CN107689359A
CN107689359A CN201710397399.5A CN201710397399A CN107689359A CN 107689359 A CN107689359 A CN 107689359A CN 201710397399 A CN201710397399 A CN 201710397399A CN 107689359 A CN107689359 A CN 107689359A
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Prior art keywords
semiconductor chip
wiring layer
layer
semiconductor package
wiring
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CN201710397399.5A
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CN107689359B (zh
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金知晃
沈钟辅
赵汊济
李元
李元一
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明提供了一种半导体封装件，其包括衬底、再布线层、多个半导体芯片堆叠结构以及第二半导体芯片。再布线层设置在衬底的上表面上。再布线层包括凹陷部。半导体芯片堆叠结构包括多个第一半导体芯片。第一半导体芯片设置在再布线层上。第一半导体芯片在水平方向上彼此隔开。第二半导体芯片设置在凹陷部中。第二半导体芯片构造为使多个半导体芯片堆叠结构中的每一个彼此电连接。

Description

包括具有嵌入芯片的再布线层的半导体封装件
相关申请的交叉引用
本申请要求于2016年8月5日提交至韩国知识产权局的韩国专利申请No.10-2016-0100126的优先权，该申请全部内容以引用方式并入本文中。
技术领域
本发明构思涉及一种半导体封装件，更具体地，涉及一种包括具有嵌入其中的半导体芯片的再布线层的半导体封装件。
背景技术
半导体封装件可具有相对较大的容量和相对较小的尺寸。为了增大半导体芯片的容量，需要用于制造在相对有限的空间内包括更多单元的半导体芯片的工艺。然而，该工艺会需要诸如精确细线宽的先进技术。因此，使用半导体芯片或半导体封装件(例如，多芯片堆叠封装件或其中以三维方式堆叠半导体芯片的堆叠型半导体封装件)来实现相对较高的集成度的方法会是期望的。
发明内容
本发明构思的示例性实施例提供了一种半导体封装件，并且更具体地，提供了一种可提高印刷电路板(PCB)产量、减少制造费用并使再布线层的翘曲最小化的半导体封装件。
根据本发明构思的示例性实施例提供了一种半导体封装件。该半导体封装件包括衬底、再布线层、多个半导体芯片堆叠结构以及第二半导体芯片。再布线层设置在衬底的上表面上。再布线层包括凹陷部。半导体芯片堆叠结构包括多个第一半导体芯片。第一半导体芯片设置在再布线层上。第一半导体芯片在水平方向上彼此隔开。第二半导体芯片设置在凹陷部中。第二半导体芯片构造为使多个半导体芯片堆叠结构彼此电连接。
根据本发明构思的示例性实施例提供了一种半导体封装件。该半导体封装件包括衬底、多个半导体芯片堆叠结构、第一再布线层以及桥接层。衬底形成在第一水平高度处。半导体芯片堆叠结构形成在第三水平高度处。半导体芯片堆叠结构在水平方向上彼此隔开。第一再布线层形成在第二水平高度处。第二水平高度设置在第一水平高度和第三水平高度之间。第一再布线层将衬底和半导体芯片堆叠结构中的至少一个电连接。桥接层形成在第二水平高度处。桥接层电连接半导体芯片堆叠结构中的至少一个。
根据本发明构思的示例性实施例提供了一种半导体封装件。该半导体封装件包括衬底、再布线层、多个半导体芯片堆叠结构以及第二半导体芯片。再布线层设置在衬底上。再布线层包括凹陷部。半导体芯片堆叠结构设置在再布线层上。第二半导体芯片设置在凹陷部中。第二半导体芯片构造为使半导体芯片堆叠结构彼此电连接。
附图说明
通过以下结合附图的详细描述，将更清晰的理解本发明构思的示例性实施例，其中：
图1A是示出了根据本发明构思的示例性实施例的半导体封装件的示意平面图；
图1B是示出了根据本发明构思的示例性实施例的半导体封装件的沿着图1A的I-I'线截取的截面图；
图2和图3是示出了根据本发明构思的示例性实施例的半导体封装件的平面图；
图4是示出了根据本发明构思的示例性实施例的形成半导体封装件的过程的示意流程图；
图5A至图5H是示出了根据本发明构思的示例性实施例的制造半导体封装件的方法的图1B的截面图；并且
图6A至图6D是示出了根据本发明构思的示例性实施例的制造半导体封装件的方法的截面图。
具体实施方式
图1A是示出了根据本发明构思的示例性实施例的半导体封装件的示意平面图。图1B是示出了根据本发明构思的示例性实施例的半导体封装件的沿着图1A的I-I'线截取的截面图。
参考图1A和图1B，半导体封装件100可包括衬底10。衬底10可以是支撑体衬底。半导体封装件100还可包括再布线层20、第二半导体芯片40以及多个半导体芯片堆叠结构30。再布线层20、第二半导体芯片40以及半导体芯片堆叠结构30可分别设置在衬底10上。衬底10可包括第一体层BD、下保护层LP以及上保护层UP。衬底10可以是印刷电路板(PCB)、陶瓷衬底、玻璃衬底或插入衬底。衬底10还可以是有源晶片。有源晶片可指其中形成半导体芯片的晶片，例如硅晶片。
可将实质上垂直于衬底10的上表面的方向定义为第一方向(例如，Z方向)。可将实质上平行于衬底10的上表面的两个方向分别定义为第二方向(例如，X方向)和第三方向(例如，Y方向)。第二方向(例如，X方向)和第三方向(例如，Y方向)可彼此交叉。例如，第二方向(例如，X方向)和第三方向(例如，Y方向)可在实质上彼此垂直的方向上交叉。第二方向(例如，X方向)和第三方向(例如，Y方向)可分别实质上垂直于第一方向(例如，Z方向)。图1A和图1B中箭头所表示的方向和与该方向相反的方向将在本文中描述为相同的方向。
在半导体封装件100中，衬底10可以是PCB，例如模塑底部填充(MUF)PCB。然而，衬底10并不限于此。MUF工艺可指通过一次模塑使用大体上相同的密封树脂来密封半导体芯片的边界部分和半导体芯片与PCB之间的空隙部分的工艺。可替换地，MUF工艺可指通过一次模塑使用大体上相同的密封树脂来密封一个或多个半导体芯片的边界部分的工艺。在MUF工艺中使用的PCB可称作MUF PCB。布线可形成在衬底10中。衬底10可构造为电连接至外部连接端子2。衬底10可通过外部连接焊盘4电连接至外部连接端子2。外部连接端子2可设置在衬底10的下表面。例如，外部连接端子2可设置在与安装半导体芯片堆叠结构30的表面相对的表面上。衬底10可通过外部连接端子2设置在模块衬底或系统板上。外部连接端子2可包括导电凸块、焊料球、导电间隔件、引脚栅格阵列(PGA)或者焊料凸块。此描述可应用于下面将要描述的多个第一连接端子12、多个第二连接端子22以及多个第三连接端子32。
第一体层BD可包括布线图案。布线图案可具有多层结构。可替换地，布线图案可具有单层结构。半导体封装件100可包括内部连接焊盘14。内部连接焊盘14可构造为电连接至外部连接端子2。内部连接焊盘14和外部连接端子2可通过布线图案彼此电连接。衬底10可包括下保护层LP和上保护层UP。下保护层LP和上保护层UP可分别保护第一体层。例如，下保护层LP和上保护层UP可分别包括阻焊剂(SR)。
当衬底10是PCB时，可通过下列方式来形成第一体层BD：压缩苯酚、环氧玻璃(或FR-4)树脂至预定厚度；形成薄膜；将铜箔涂覆在薄膜两侧；以及通过图案化形成布线图案。布线图案可以是电信号的传送路径。可通过通孔接触件电连接形成在上表面和下表面上的布线图案来形成下保护层LP和上保护层UP。通孔接触件可穿透进入第一体层BD。还可通过利用阻焊剂层涂覆第一体层BD的上表面和下表面来形成下保护层LP和上保护层UP。例如，第一体层BD的实质上全部上表面和下表面可涂覆有阻焊剂层。端子连接部分不可涂覆阻焊剂层。端子连接部分可指在其中形成内部连接焊盘14和外部连接焊盘4的部分。
外部连接焊盘4和内部连接焊盘14可包括铜(Cu)、铝(Al)、镍(Ni)、银(Ag)、金(Au)、铂(Pt)、锡(Sn)、铅(Pb)、钛(Ti)、铬(Cr)、钯(Pd)、铟(In)、锌(Zn)、碳(C)或者它们的组合/合金。半导体封装件100可包括第一连接焊盘24、第二连接焊盘34以及第三连接焊盘44。第一连接焊盘至第三连接焊盘23、33和43的组成可与外部连接焊盘4和内部连接焊盘14的组成实质上相同。
PCB可以是单层PCB。单层PCB可具有形成在其一个表面上的布线。可替换地，PCB可以是双层PCB。双层PCB可具有形成在其两个表面上的布线。绝缘体可形成至少三个铜箔层和至少三个布线层。绝缘体可以是预浸料。根据形成铜箔层的数量，绝缘体可形成至少三个铜箔层和至少三个布线层。因此，可形成具有多个布线层的PCB。然而，半导体封装件100的衬底10不仅限于上述PCB的结构或材料。
可在衬底10上形成再布线层20。再布线层20可包括多个绝缘层25a、25b、25c以及25d。在衬底10上可顺序设置绝缘层25a、25b、25c以及25d。再布线层20还可以包括第一布线26。可在绝缘层25a、25b、25c以及25d上形成第一布线26。虽然再布线层20如图1B所示可包括四个绝缘层，但本发明构思的示例性实施例不限于此。例如，再布线层20可包括三个或更少的绝缘层或至少五个绝缘层。绝缘层25a、25b、25c以及25d可包括例如苯酚或环氧玻璃(或FR-4)树脂、预浸料、Ajinomoto积聚膜(ABF)或聚酰亚胺的绝缘材料。
第一布线26可包括第一通孔26a、再布线图案26b以及第二通孔26c。第一通孔26a和第二通孔26c可在第一方向(例如，Z方向)上延伸。第一通孔26a和第二通孔26c可具有填充柱形状或圆柱形。第一通孔26a和第二通孔26c的顶部临界尺寸(CD)可分别大于第一通孔26a和第二通孔26c的底部临界尺寸(CD)。然而，本发明构思的示例性实施例不限于此。再布线图案26b可在水平方向上延伸，例如第三方向(例如，Y方向)。因此，如图1B所示，通孔和再布线图案可用于形成线结构；然而，本发明构思的示例性实施例不限于此。关于电路的设计，线结构可包括更多或更少的通孔和再布线图案。
第一通孔26a、再布线图案26b以及第二通孔26c可包括铜(Cu)、铝(Al)、镍(Ni)、银(Ag)、金(Au)、铂(Pt)、锡(Sn)、铅(Pb)、钛(Ti)、铬(Cr)、钯(Pd)、铟(In)、锌(Zn)、碳(C)或者它们的组合/合金。半导体封装件100可包括第二布线46。第二布线46的组成可与第一通孔26a、再布线图案26b以及第二通孔26c的组成实质上相同。
可通过光刻工艺形成第一布线26。第一布线26的线规范和间距规范中的每一个可大于约2μm。可替换地，第一布线26的半节距可约大于2μm或者第一布线26的一个节距可大于约4μm。然而，本发明构思的示例性实施例不限于此。
可在与绝缘层25a实质上相同的水平高度处形成第一连接焊盘24。因此，第一连接焊盘24可形成在绝缘层25a、25b、25c以及25d的最底层上。第一连接焊盘24可电连接第一布线26和第一连接端子12。因此，第一连接焊盘24可构造为电连接至衬底10。第一连接焊盘24可通过第一连接端子12电连接至衬底10。
第二连接焊盘34可形成在绝缘层25d上。因此，第二连接焊盘34可形成在绝缘层25a、25b、25c以及25d的最高层上。然而，本发明构思的示例性实施例不限于此。例如，第二连接焊盘34可形成在与绝缘层25d实质上相同的平面上。因此，第二连接焊盘34可形成在绝缘层25a、25b、25c以及25d的最高层上。
第二连接焊盘34可电连接第一布线26和第二连接端子22。因此，衬底10可构造为经由第一连接端子12、第一连接焊盘24、第一布线26、第二连接焊盘34以及第二连接端子22电连接至半导体芯片堆叠结构30。因此，第一连接焊盘24的尺寸可大于第二连接焊盘34的尺寸。
再布线层20具有凹陷部H。凹陷部H可穿透进入再布线层20。凹陷部H可形成在与再布线层20实质上相同的平面上。可替换地，凹陷部H在竖直方向上的高度可与再布线层20在竖直方向上的高度实质上相同。凹陷部H在竖直方向上的高度可与绝缘层25a、25b、25c以及25d的堆叠高度实质上相同。然而，本发明构思的示例性实施例不限于此。例如，凹陷部H在竖直方向上的高度可低于再布线层20在竖直方向上的高度。凹陷部H可以没有延伸入绝缘层25a、25b、25c以及25d中的一些绝缘层。例如，凹陷部H可以没有延伸入绝缘层25a。绝缘层25a可以是绝缘层25a、25b、25c以及25d中最低的一层。可通过刻蚀再布线层20的多个绝缘层提供图案25p(图5E所示)来形成凹陷部H。通过刻蚀绝缘层提供图案25p而生成的空洞可成为凹陷部H。因此，根据绝缘层提供图案25p的刻蚀程度，凹陷部H在竖直方向上的高度可以不同。再布线层20可包括两个堆叠结构。这两个堆叠结构可被凹陷部H分开。第二半导体芯片40可安装在凹陷部H中。因此，凹陷部H的水平截面积可大于第二半导体芯片40的水平截面积。
半导体芯片堆叠结构30可设置在再布线层20上。半导体芯片堆叠结构30在水平方向上彼此隔开。半导体芯片堆叠结构30可包括多个第一半导体芯片。第一半导体芯片可在实质上垂直于衬底10上表面的方向上堆叠。
第一半导体芯片可以是非易失性存储器装置。因此，第一半导体芯片可电擦除和编程数据。即使供电受阻，第一半导体芯片也可保持数据。根据本发明构思的示例性实施例，可提供NAND型闪速存储器装置作为非易失性存储器装置。NAND型闪速存储器装置可具有相对大容量和相对高速存储能力。第一半导体芯片可包括PRAM、MRAM、ReRAM、FRAM或者NOR闪速存储器。第一半导体芯片可以是易失性存储器装置。因此，当供电受阻时，第一半导体芯片可丢失数据，例如DRAM或SRAM。然而，本发明构思的示例性实施例不限于此。例如，第一半导体芯片可以是逻辑芯片、测量装置、通信装置、数字信号处理器(DSP)或片上系统(SoC)。半导体芯片堆叠结构30可包括不同类型的第一半导体芯片。
第二半导体芯片40可插入到凹陷部H中。因此，第二半导体芯片40的水平截面积可实质上小于凹陷部H的水平截面积。第二半导体芯片40在竖直方向上的高度可实质上低于凹陷部H在竖直方向上的高度。然而，本发明构思的示例性实施例不限于此。例如，第二半导体芯片40在竖直方向上的高度可实质上等于或大于凹陷部H在竖直方向上的高度。尽管可如图1A和图1B所示将一个第二半导体芯片40插入到凹陷部H，但本发明构思的示例性实施例不限于此。例如，可将至少两个第二半导体芯片40插入到凹陷部H。
第二半导体芯片40可包括第二体层BD'、钝化层PL以及第二布线46。第二布线46可以是内部布线。第二体层BD'可与衬底10的第一体层BD实质上相同。第二体层BD'可基于有源晶片。有源晶片可以是除插入衬底之外的晶片。可替换地，第二体层BD'可包括半导体芯片。半导体芯片可以基于硅(Si)。可替换地，第二体层BD'可包括有源元件。第二体层BD'可包括逻辑芯片、测量装置、通信装置、数字信号处理器(DSP)或片上系统(SoC)。
钝化层PL可保护第二体层BD'不受外部的物理和化学损伤。与上保护层UP或下保护层LP类似，钝化层PL可保护第二体层BD'。钝化层PL可包括氧化物层或氮化物层。可替换地，钝化层PL可包括双层。双层可包括氧化物层和氮化物层。钝化层PL可包括通过HDP-CVD(高密度等离子体化学气相淀积)工艺形成的氧化物层或氮化物层，例如氧化硅(SiO2)层和/或氮化硅(SiNx)层。绝缘层25a、25b、25c以及25d中的最高层绝缘层25d与钝化层PL可形成在实质上相同的平面上。然而，本发明构思的示例性实施例不限于此。例如，绝缘层25a、25b、25c以及25d中的最高层绝缘层25d与钝化层PL可形成在不同的平面上。钝化层PL可涂覆第二体层BD'的上表面。钝化层PL可涂覆除了第二体层BD'上形成第二布线46的部分以外的第二体层BD'的上表面上。第二布线46可穿透进入钝化层PL的一部分。可通过涂覆氧化硅层、氮化硅(SiNx)层或者包括氧化硅层和氮化硅(SiNx)层的双层形成钝化层PL。
第三连接焊盘44可形成在钝化层PL上。然而，本发明构思的示例性实施例不限于此。例如，第三连接焊盘44可形成在与钝化层PL实质上相同的平面上。第二连接焊盘34和第三连接焊盘44可形成在实质上相同的平面上。
第二半导体芯片40可构造为电连接至第三连接端子32。第三连接端子32可设置在第二半导体芯片40和半导体芯片堆叠结构30之间。第二半导体芯片40通过第三连接焊盘44电连接至第三连接端子32。第二半导体芯片40可构造为桥接层。桥接层可将在水平方向上彼此隔开的半导体芯片堆叠结构30电连接。
第二半导体芯片40可包括第二布线46。第二布线46可以是细线结构。第二布线46可构造为电连接至第三连接焊盘44。第二布线46的线规范和间距规格中的每一个可小于约2μm。第二布线46的半节距可小于约2μm。第二布线46的一个节距可小于约4μm。可替换地，第二布线46的临界尺寸(CD)可小于约2μm。然而，本发明构思的示例性实施例不限于此。
第一连接焊盘24的尺寸可大于第二连接焊盘34和第三连接焊盘44的尺寸。为了提高连接效率和布线的自由度，用于电连接衬底(尤其是PCB衬底)的连接焊盘可大于用于半导体芯片之间的电连接的连接焊盘。此外，第二连接焊盘34的尺寸可实质上等于或大于第三连接焊盘44的尺寸。第三连接焊盘44可连接至具有细线结构的第二布线46。通过利用常规刻蚀工艺(诸如光刻)会较难实现第二布线46的细线结构。因此，第二连接焊盘34的尺寸可实质上等于或大于第三连接焊盘44的尺寸。
第一连接端子12的尺寸可大于第二连接端子22和第三连接端子32的尺寸。第二连接端子22的尺寸可实质上等于或大于第三连接端子32的尺寸。
用于连接不同半导体芯片的传统中介层技术可包括：硅中介层、有机中介层、扇出型晶圆级封装件(FO-WLP)或嵌入式多芯片互连桥接(EMIB)。由于硅通孔(TSV)和势垒/种子(B/S)工艺，硅中介层会增加费用和产量。由于芯片尺寸的增加，硅中介层也会增加费用和产量。有机中介层和FO-WLP会较难实现细线结构。由于翘曲所引起的有限工艺，有机中介层和FO-WLP会较难实现细线结构。EMIB可在具有细小且多节焊盘的PCB中嵌入SI桥接芯片。因此，EMIB会在安装芯片的工艺中引起翘曲，所述芯片在PCB上具有精细结构的焊料凸块。
根据本发明构思的示例性实施例，使得衬底的内部布线最小化。为了使得衬底10的内部布线最小化，半导体芯片堆叠结构30和衬底10可构造为彼此电连接。半导体芯片堆叠结构30和衬底10可构造为通过在衬底10上分离地形成再布线层20来彼此电连接。此外，通过常规刻蚀在再布线层20中较难实现的细线结构可通过安装桥接层来实现。桥接层可具有基于硅的细线结构，例如第二半导体芯片40。
第二半导体芯片40可附接至再布线层20。第二半导体芯片40可通过粘合件48附接至再布线层20。如图1B所示，粘合件48围绕在第二半导体芯片40的侧表面和下表面；然而，本发明构思的示例性实施例不限于此。例如，粘合件48可直接与第二半导体芯片40的侧表面和下表面接触。粘合件48可包括非导电膜(NCF)、各向异性导电膜(ACF)、UV膜、速凝粘合剂、热固性粘合剂、激光固化粘合剂、超声固化粘合剂、非导电浆(NCP)或芯片附着膜(DAF)。第二半导体芯片40的上表面、粘合件48的上表面以及绝缘层25a、25b、25c和25d中的最高层绝缘层25d的上表面可形成实质上相同的平面。然而，本发明构思的示例性实施例不限于此。例如，在竖直截面上，粘合件48的上表面和第二半导体芯片40的上表面可低于绝缘层25a、25b、25c和25d中的最高层绝缘层25d的上表面。
芯片密封件38可构造为密封多个半导体芯片堆叠结构30。芯片密封件38可保护半导体芯片堆叠结构30免于外部杂质。芯片密封件38可包括，例如，环氧树脂模塑料(EMC)、硅基材料、热固性材料、热塑性材料或者UV固化材料。热固性材料可包括酚类固化剂、酸酐类固化剂、胺类固化剂、丙烯酸聚合物添加剂或它们的任意组合。
可通过晶圆级模塑工艺形成芯片密封件38。芯片密封件38可在晶圆级上形成。如图5H所示，晶圆级可设置在布线封装件500之前。芯片密封件38可分解为单元布线封装件。如图5H所示，单元布线封装件可设置在载体60上。芯片密封件38可包括芯片底部填充38a和芯片模具38b。可通过使用例如毛细效应底部填充的方法形成芯片底部填充38a。芯片模具38b可覆盖并保护半导体芯片堆叠结构30。可通过MUF工艺形成芯片密封件38。因此，覆盖第一半导体芯片的暴露部分(诸如边缘)的材料与填充在半导体芯片堆叠结构30和再布线层20之间的材料可实质上相同。
封装密封件28可密封再布线层20的侧表面和下表面。封装密封件28可密封芯片密封件38的侧表面和下表面。封装密封件28的组成可与芯片密封件38的组成实质上相同。因此，可保护再布线层20、半导体芯片堆叠结构30以及第二半导体芯片40免于外部杂质。
半导体封装件100可包括衬底10。衬底10可形成在第一水平高度LV1处。半导体封装件100还可包括半导体芯片堆叠结构30。半导体芯片堆叠结构30在水平方向上彼此隔开。半导体芯片堆叠结构30可设置在第三水平高度LV3处。半导体芯片堆叠结构30可在与第一水平高度LV1垂直的方向上隔开。半导体封装件100还可包括再布线层20和桥接层(例如，第二半导体芯片40)。再布线层20和桥接层可分别形成在第二水平高度LV2处。第二水平高度LV2可设置在第一水平高度LV1和第三水平高度LV3之间。再布线层20可电连接衬底10和至少一个半导体芯片堆叠结构30。桥接层(例如，第二半导体芯片40)可使至少两个半导体芯片堆叠结构30彼此电连接。半导体封装件100可包括形成在与衬底10不同的水平高度处的再布线层20。例如，衬底10可形成在第一水平高度LV1处，再布线层20可形成在第二水平高度LV2处。
图2是示出了根据本发明构思的示例性实施例的半导体封装件的平面图。
半导体封装件200可包括衬底210。衬底210可形成在第一水平高度处。半导体封装件200还可包括多个半导体芯片堆叠结构230a和230b。半导体芯片堆叠结构230a和230b可在水平方向上彼此隔开。半导体芯片堆叠结构230a和230b可形成在第三水平高度处。半导体封装件200可包括再布线层220和桥接层(例如，第二半导体芯片240)。再布线层220和桥接层可形成在第二水平高度处。第二水平高度可设置在第一水平高度和第三水平高度之间。再布线层220可构造为电连接衬底210和至少一个半导体芯片堆叠结构230a和230b。
桥接层(例如，第二半导体芯片240)可插入到再布线层220中。再布线层220可包括多个凹陷部H'。凹陷部H'中的每一个可包括多个桥接层(例如，第二半导体芯片240)。桥接层(例如，第二半导体芯片240)可电连接到至少两个半导体堆叠件230a和230b。凹陷部H'可形成在第二水平高度处。第二半导体芯片240可分别插入凹陷部H'。第二半导体芯片240可设置在第二水平高度处。虽然凹陷部H'的尺寸和形状在图2中示出为可实质上彼此相同，但本发明构思的示例性实施例不限于此。凹陷部H'的尺寸和形状可根据分别插入凹陷部H'的第二半导体芯片240的尺寸来修改。凹陷部H'的尺寸和形状也可根据半导体芯片堆叠结构230a和230b之间的位置关系来修改。
半导体芯片堆叠结构230a和230b可包括第一半导体芯片堆叠结构230a和第二半导体芯片堆叠结构230b。第一半导体芯片堆叠结构230a中的每一个可构造为通过桥接层与第二半导体芯片堆叠结构230b彼此电连接。根据本发明构思的示例性实施例，例如，第一半导体芯片堆叠结构230a可以是上述存储器芯片的堆叠。第二半导体芯片堆叠结构230b可包括有源元件、逻辑芯片或专用集成电路(ASIC)。
图3是示出了根据本发明构思的示例性实施例的半导体封装件的平面图。
半导体封装件300可包括衬底310。衬底310可形成在第一水平高度处。半导体封装件300还可包括多个半导体芯片堆叠结构330。半导体芯片堆叠结构330可在水平方向上彼此隔开。半导体芯片堆叠结构330可形成在第三水平高度处。半导体封装件300还可包括再布线层320和桥接层(例如，第二半导体芯片340)。再布线层320和桥接层(例如，第二半导体芯片340)可形成在第二水平高度处。第二水平高度可设置在第一水平高度和第三水平高度之间。
凹陷部H"可形成在与再布线层320实质上相同的水平高度处。凹陷部H"的长度与再布线层320的长度在第二方向(例如，X方向)上可实质上相同。第二方向(例如，X方向)可以是与衬底310的上表面实质上平行的方向。当凹陷部H"的高度与再布线层320的高度在竖直方向上实质上相同时，再布线层320可分为两个区域。再布线层320可被凹陷部H"分为两个区域。半导体封装件300可包括多个再布线层320。再布线层320在水平方向上隔开。设置在多个再布线层320之间的空的空间(例如，空洞)可指凹陷部H"。第二半导体芯片340可设置在相邻的再布线层320之间。
参考图2和图3，再布线层220和320、凹陷部H'和H"的位置与形状以及第二半导体芯片240和340的布置可以例如根据产品性能和设计考虑而改变。
图4是示出了根据本发明构思的示例性实施例的形成半导体封装件的过程的示意流程图。图5A至图5H是示出了根据本发明构思的示例性实施例的制造半导体封装件的方法的图1B的截面图。
参考图4和图5A，在制备再布线层的过程P1010中可提供载体固定层65和载体60。载体60可以是刚性体，例如，石英衬底、玻璃衬底、半导体衬底、陶瓷衬底或金属衬底。载体60可包括相对刚性的材料。载体60可具有机械刚度。载体60可支承正在形成的再布线层。因此，载体60可有助于形成再布线层的过程。载体60可执行晶圆级处理。晶圆级处理可是翘曲的出现最小化。载体60的厚度可在从约100μm到约1000μm的范围内。然而，载体60的厚度不限于此。例如，载体60的厚度可小于约100μm或者大于约1000μm。在晶圆级上执行制造工艺可指将半导体芯片直接安装在晶圆状态下的晶圆上。在晶圆级上执行制造工艺还可指执行裁剪工艺或磨削工艺。在晶圆级上执行制造工艺还可指在将晶圆切割成独立的基片或独立的芯片并在晶圆尺寸的支撑衬底上重新布置独立的基片或独立的芯片之后执行制造工艺。
载体固定层65可形成在载体60上。载体固定层65可将绝缘层提供层251固定在载体60上。因此，载体固定层65可包括粘合剂材料。载体固定层65可以是粘合层。粘合层可将绝缘层提供层251固定在载体60上。粘合层可包括胶。载体固定层65可包括聚合物。例如，载体固定层65可包括硅氧烷。载体固定层65可包括含有苯基的硅氧烷。可替换地，载体固定层65可通过环氧树脂交联。例如，载体固定层65可包括聚合物，其中环氧树脂在含有苯基的硅氧烷中用做交联剂。
可通过利用自旋沉积(SOD)法来形成载体固定层65。因此，载体固定层65可实质上均匀地涂覆在载体60上；然而，本发明构思的示例性实施例不限于此。
可在载体固定层65上提供释放层。如图5D所示，释放层可将载体60从再布线层20分离。在包括载体60的制造工艺后，释放层可将载体60从再布线层20分离。然而，在包括载体60的制造工艺的过程中，释放层也可固定至载体60和再布线层20中的每一个，如图5D所示。释放层可包括聚合物。释放层可包括硅氧烷。
可在载体固定层65上提供绝缘层提供层251。例如，化学气相沉积(CVD)可用于在载体固定层65上实质上均匀地提供绝缘层提供层251。然而，本发明构思的示例性实施例不限于此。例如，可通过利用SOD、物理气相沉积(PVD)或原子层沉积(ALD)来提供绝缘层提供层251。绝缘层提供层251可具有与参考图1A和图1B描述的绝缘层25a、25b、25c和25d的组成实质上相同的组成。
参考图4和图5B，在过程P1010中，制备了绝缘层提供图案25p。光致抗蚀剂可涂覆在绝缘层提供层251上。可对绝缘层提供层251进行图案化。可通过曝光和显影对绝缘层提供层251进行图案化。因此，可形成光致抗蚀剂图案。通过光致抗蚀剂图案可限定将要形成第一连接焊盘24的区域。随后可刻蚀绝缘层提供层251。可刻蚀绝缘层提供层251直至裸露出载体固定层65的上表面。可利用光致抗蚀剂图案作为刻蚀掩模来刻蚀绝缘层提供层251。因此，可形成绝缘层提供图案25p。
随后，可在绝缘层提供图案25p上提供导电材料层。导电材料层可实质上一致地填充在形成在绝缘层提供图案25p中的空洞中。可通过利用绝缘层提供图案25p作为刻蚀终止层来执行化学机械抛光(CMP)。因此，可形成第一连接焊盘24。因此，第一连接焊盘24和绝缘层提供图案25p可具有实质上相同的高度。在CMP过程中可部分地刻蚀绝缘层提供图案25p的上表面。
参考图4和图5C，在过程P1010中，可与参考图5B描述的实质上相同地制备绝缘层提供图案25p和第一通孔26a。在绝缘层提供图案25p上提供与第一连接焊盘24在实质上相同的水平高度处的绝缘层提供层后，可在绝缘层提供图案25p上形成光致抗蚀剂图案。光致抗蚀剂图案可在绝缘层提供层中限定第一通孔26a。随后，可通过将光致抗蚀剂图案用作刻蚀掩模来刻蚀绝缘层提供层。可刻蚀绝缘层提供层直至裸露出第一连接焊盘24的上表面。第一通孔26a可形成在第一方向(例如，Z方向)上。可通过执行参考图5B描述的CMP过程提供第一通孔26a和绝缘层提供图案25p。
参考图4和图5D，在过程P1010中，如参考图5B或图5C描述的那样，可提供绝缘层提供图案25p和再布线图案26b。再布线图案26b可形成在第三方向(例如，Y方向)上；然而，本发明构思的示例性实施例不限于此。例如，再布线图案26b可形成在第二方向(例如，X方向)上。
参考图4和图5E，在过程P1010中，参考图5B描述的那样，可提供绝缘层提供图案25p、第一布线26以及第二连接焊盘34。可提供使绝缘层提供图案25p彼此结合的邻接层。可在绝缘层提供图案25p之间提供邻接层。邻接层可包括NCF、ACF、UV膜、速凝粘合剂、热固性粘合剂、激光固化粘合剂、超声固化粘合剂、NCP或DAF。
可在绝缘层提供图案25p上形成牺牲层。牺牲层可具有相对于绝缘层提供图案25p的刻蚀选择性。在形成牺牲层后，可参考图5B描述的那样提供第二连接焊盘34。随后可去除牺牲层。可利用湿法刻蚀去除牺牲层。
在提供绝缘层提供层而非牺牲层以形成第二连接焊盘34时，第二连接焊盘34可形成在与在竖直截面中的最高层绝缘层提供图案25p实质上相同的水平高度处。最高层绝缘层提供图案25p的厚度可小于其他绝缘层提供图案25p的厚度。最高层绝缘层提供图案25p可包括第二连接焊盘34。如图5H所示，第二连接焊盘34可连接至半导体芯片堆叠结构30。第二连接焊盘34的尺寸可小于第一连接焊盘24的尺寸。第二连接焊盘34的高度可与最高层绝缘层提供图案25p的高度实质上相同。
参考图5B至图5E描述的第一布线26的形成是本发明构思的一个示例性实施例；然而，本发明构思的示例性实施例不限于此。例如，第一布线26的形成可根据半导体封装件的设计而改变。
参考图4和图5F，在过程P1020中，可形成凹陷部H。可类似于参考图5A描述的光刻法来形成凹陷部H。然而，在形成光致抗蚀剂之前可形成硬掩模层。硬掩模层可包括无定型碳层或多晶硅层。可在硬掩模层上形成抗反射涂层。可通过对光致抗蚀剂进行图案化形成光致抗蚀剂图案。可通过曝光和显影对光致抗蚀剂进行图案化。随后，可通过刻蚀硬掩模层形成硬掩模图案。可通过将光致抗蚀剂图案用作刻蚀掩模来刻蚀硬掩模层。在去除光致抗蚀剂图案之后，可在最高层绝缘层提供图案25p上形成硬掩模图案。可在排除形成凹陷部H的部分之外的绝缘层提供图案25p上形成硬掩模图案。可通过将硬掩模图案用作刻蚀掩模来形成凹陷部H。随后可通过将硬掩模图案用作刻蚀掩模来刻蚀绝缘层提供图案25p。然而，本发明构思的示例性实施例不限于此。可在不使用硬掩模层的情况下通过将硬掩模图案用作刻蚀掩模来刻蚀绝缘层提供图案25p。相应地，绝缘层提供图案25p可成为绝缘层25a、25b、25c以及25d。
参考图4和图5G，在过程P1030中，可在凹陷部H中提供第二半导体芯片40。在提供第二半导体芯片40时，可执行向凹陷部H提供多个粘合件48并将第二半导体芯片40压至粘合件48的方法。可在晶圆级上例如通过晶圆上芯片(COW)工艺执行提供第二半导体芯片40的过程。对于形成在载体60上的多个再布线层20的阵列，可在使每个再布线层20独立之前将第二半导体芯片40插入凹陷部H中。第二半导体芯片40可插入安装在载体60上的晶圆层。因此，可提高处理效率并且可使施加在再布线层20或第二半导体芯片40的翘曲最小化。然而，本发明构思的示例性实施例不限于此。可在个体化工艺之后提供第二半导体芯片40。
参考图4和图5H，可提供半导体芯片堆叠结构30。第二连接端子22可构造为电连接半导体芯片堆叠结构30和再布线层20。第三连接端子32构造为电连接半导体芯片堆叠结构30和第二半导体芯片40。也可在晶圆级上提供半导体芯片堆叠结构30。因此可提高处理效率并且可使翘曲最小化。然而，本发明构思的示例性实施例不限于此。可在个体化工艺之后提供半导体芯片堆叠结构30。
随后可提供芯片密封件38。芯片密封件38可保护半导体芯片堆叠结构30。芯片密封件38可包括芯片底部填充38a和芯片模具38b。可通过使用毛细效应底部填充方法提供芯片底部填充38a。可提供芯片模具38b以覆盖并保护半导体芯片堆叠结构30的上表面和侧表面。然而，本发明构思的示例性实施例不限于此。例如，通过MUF工艺可形成芯片密封件38。包括再布线层20、半导体芯片堆叠结构30、芯片密封件38、粘合件48以及第二半导体芯片40的结构可称作布线封装件500。
参考图1B，可通过将如图5H所示的布线封装件500布置在衬底10上来提供半导体封装件100。
可通过执行将图5H所示的布线封装件500切割成单元结构的个体化工艺来生产单元布线封装件500。随后，可将单元布线封装件500安装在衬底10上。单元布线封装件500可构造为电连接至衬底10。单元布线封装件500可经由如图1B所示的第一连接端子12和内部连接焊盘14电连接至衬底10。封装密封件28可保护布线封装件500免于外部损坏因素。可通过底部填充工艺(例如，MUF工艺)提供封装密封件28。
图6A至图6D是示出了根据本发明构思的示例性实施例的制造半导体封装件的方法的截面图。
参考图6A，可在刻蚀工艺期间刻蚀将要形成凹陷部的部分。刻蚀工艺可包括光致抗蚀剂图案。可在绝缘层提供层上提供导电材料层。可在绝缘层提供层上形成如图1B所示的凹陷部H。导电材料层可实质上一致地填充在形成在绝缘层提供图案25p中的孔洞中。随后，可通过将绝缘层25a的上表面用作刻蚀终止层来执行CMP。因此，可形成第一连接焊盘24和牺牲图案29a。
参考图6B，与参考图6A的描述相似，当刻蚀绝缘层提供层以形成第一布线26和第二连接焊盘34时，可刻蚀将要形成凹陷部H的部分。因此，可限定将要分别形成在绝缘层提供层中的牺牲图案29b、29c以及29d的凹陷。因此，在形成第一布线26和第二连接焊盘34时可形成牺牲图案29b、29c以及29d。
参考图6C，可在最高层绝缘层25d上形成掩模层图案70p。掩模层图案70p可防止在去除牺牲图案的过程中暴露的第二连接焊盘34受到由例如湿法刻蚀液体引起的损坏。因此，掩模层图案70p可包括相对于牺牲图案29b、29c以及29d具有刻蚀选择性的材料。掩模层图案70p可实质上一致地形成在最高层绝缘层25d和第二连接焊盘34上。因此，形成在第二连接焊盘34上的掩模层图案70p可包括不均匀。
参考图6D，可通过例如湿法刻蚀去除牺牲图案29b、29c以及29d。然而，本发明构思的示例性实施例不限于此。例如，可通过干法刻蚀去除牺牲图案29b、29c以及29d。在去除牺牲图案29b、29c以及29d后可去除掩模层图案70p。
可通过与参考图5G和图5H描述的过程实质上相同的过程提供半导体封装件100、半导体封装件200以及半导体封装件300。
虽然已参考本发明构思的实施例详细具体示出并说明了本发明构思的示例性实施例，但需要理解的是，在不脱离本发明构思的精神和范围的情况下，可进行多种形式和细节上的改变。

Claims (20)

1.一种半导体封装件，包括：
衬底；
再布线层，其设置在所述衬底的上表面上，所述再布线层包括凹陷部；
多个半导体芯片堆叠结构，其包括设置在所述再布线层上并在水平方向上彼此隔开的多个第一半导体芯片；以及
第二半导体芯片，其设置在所述凹陷部中，
其中，所述第二半导体芯片构造为使所述多个半导体芯片堆叠结构中的每一个彼此电连接。
2.根据权利要求1所述的半导体封装件，其中，所述凹陷部设置在所述再布线层面向所述第一半导体芯片的表面上。
3.根据权利要求1所述的半导体封装件，其中，所述凹陷部穿透进入所述再布线层。
4.根据权利要求1所述的半导体封装件，还包括设置在所述凹陷部中的粘合件，其中，所述粘合件将所述再布线层附接至所述第二半导体芯片。
5.根据权利要求4所述的半导体封装件，其中，所述第二半导体芯片是有源元件。
6.根据权利要求5所述的半导体封装件，还包括：
多个第一连接端子，其设置在所述再布线层和所述衬底之间；
多个第二连接端子，其设置在所述再布线层和所述半导体芯片堆叠结构之间；以及
多个第三连接端子，其设置在所述第二半导体芯片和所述半导体芯片堆叠结构之间，
其中，所述第一连接端子比所述第二连接端子更大。
7.根据权利要求6所述的半导体封装件，其中，所述第二连接端子比所述第三连接端子更大。
8.根据权利要求6所述的半导体封装件，还包括：
多个第一连接焊盘，其设置在所述再布线层面向所述衬底的表面上并电连接至所述第一连接端子；
多个第二连接焊盘，其设置在所述再布线层面向所述半导体芯片堆叠结构的表面上并电连接至所述第二连接端子；以及
多个第三连接焊盘，其设置在所述第二半导体芯片面向所述半导体芯片堆叠结构的表面上并电连接至所述第三连接端子，
其中，所述第一连接焊盘比所述第二连接焊盘更大。
9.根据权利要求8所述的半导体封装件，其中，所述第二连接焊盘比所述第三连接焊盘更大。
10.根据权利要求1所述的半导体封装件，还包括：
包括在所述再布线层中的第一布线；以及
包括在所述第二半导体芯片中的第二布线，
其中，所述第一布线的线宽大于所述第二布线的线宽。
11.根据权利要求10所述的半导体封装件，其中，所述第二布线的线宽小于2μm。
12.一种半导体封装件，包括：
衬底，其形成在第一水平高度处；
多个半导体芯片堆叠结构，其形成在第三水平高度处并在水平方向上彼此隔开；
第一再布线层，其形成在第二水平高度处，所述第二水平高度设置在所述第一水平高度和所述第三水平高度之间，并且所述第一再布线层将所述衬底与所述半导体芯片堆叠结构中的至少一个电连接；以及
桥接层，其形成在所述第二水平高度处并且电连接所述半导体芯片堆叠结构中的至少一个。
13.根据权利要求12所述的半导体封装件，其中，所述桥接层设置在所述第一再布线层中。
14.根据权利要求12所述的半导体封装件，还包括形成在所述第二水平高度处的第二再布线层，其中，所述第二再布线层与所述第一再布线层隔开，并且将所述衬底与所述半导体芯片堆叠结构中的至少一个电连接。
15.根据权利要求14所述的半导体封装件，其中，所述桥接层设置在所述第一再布线层和所述第二再布线层之间。
16.一种半导体封装件，包括：
衬底；
再布线层，其设置在所述衬底上，所述再布线层包括凹陷部；
多个半导体芯片堆叠结构，其设置在所述再布线层上；以及
第二半导体芯片，其设置在所述凹陷部中，
其中，所述第二半导体芯片构造为将所述半导体芯片堆叠结构彼此电连接。
17.根据权利要求16所述的半导体封装件，其中，所述凹陷部设置在所述再布线层面向所述第一半导体芯片的表面上。
18.根据权利要求16所述的半导体封装件，其中，所述凹陷部穿透进入所述再布线层。
19.根据权利要求16所述的半导体封装件，其中，所述再布线层包括多个绝缘层。
20.根据权利要求16所述的半导体封装件，其中，所述第二半导体芯片的水平横截面积小于所述凹陷部的水平横截面积。
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