WO2024082130A1 - 具备芯片间精细内互连线路的扇出封装结构及其制造方法 - Google Patents

具备芯片间精细内互连线路的扇出封装结构及其制造方法 Download PDF

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WO2024082130A1
WO2024082130A1 PCT/CN2022/125896 CN2022125896W WO2024082130A1 WO 2024082130 A1 WO2024082130 A1 WO 2024082130A1 CN 2022125896 W CN2022125896 W CN 2022125896W WO 2024082130 A1 WO2024082130 A1 WO 2024082130A1
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fine
layer
chip
chips
interconnection
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PCT/CN2022/125896
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English (en)
French (fr)
Inventor
燕英强
胡川
凌云志
郑伟
陈志涛
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广东省科学院半导体研究所
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Application filed by 广东省科学院半导体研究所 filed Critical 广东省科学院半导体研究所
Priority to PCT/CN2022/125896 priority Critical patent/WO2024082130A1/zh
Priority to CN202280013630.5A priority patent/CN116998008A/zh
Publication of WO2024082130A1 publication Critical patent/WO2024082130A1/zh

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  • the present application relates to the field of chip heterogeneous integration and advanced packaging technology, and more specifically, to a fan-out packaging structure with fine internal interconnection lines between chips and a manufacturing method thereof.
  • the first preparation method is as follows: fine interconnection lines (also collectively referred to as silicon bridges, the line width and line spacing of the fine interconnection lines can be less than 5 ⁇ m, or even less than 2 ⁇ m) are prepared in advance on flat, non-deformable, and low CTE materials such as silicon, glass, and ceramics, and then cut into individual silicon bridges, and finally buried in the IC carrier (printed circuit board).
  • the IC carrier printed circuit board.
  • the fine interconnection pin pads of the chip are mounted on the interconnection pin pads of the silicon bridge, and the non-fine interconnection pin pads of the chip are electrically connected to other interconnection lines (line width and line spacing greater than 5 ⁇ m, or even greater than 7 ⁇ m) in the IC carrier.
  • the second preparation method is as follows: pre-prepare fine interconnection lines (also collectively referred to as silicon bridges, the line width and line spacing of the fine interconnection lines can be less than 5 ⁇ m, or even less than 2 ⁇ m) on flat, non-deformable, and low-CTE materials such as silicon, glass, and ceramics, and then cut them into individual fine interconnection lines, which are buried in the fan-out package plastic packaging material, or attached to a temporary bonding material like the chip, and then flip-chip mounted, the fine interconnection pins of the chip are electrically connected to the interconnection pins of the silicon bridge, and the non-fine interconnection pins of the chip are electrically connected to other interconnection lines in the fan-out package.
  • the present application provides a fan-out packaging structure with internal interconnection lines between chips and a manufacturing method thereof, the purpose of which at least includes reducing costs, reducing process difficulty, and ensuring high alignment accuracy of chip placement across silicon bridges.
  • the present application provides a method for manufacturing a fan-out packaging structure having fine internal interconnection lines between chips, comprising:
  • Temporary carrier plates can be provided
  • a peelable material may be formed on a temporary carrier
  • a rewiring layer may be formed on the strippable material, the rewiring layer comprising an insulating material layer, interconnection lines embedded in the insulating material layer, and external pin pads, the external pin pads being arranged on a first side of the rewiring layer opposite to the temporary carrier and used for interconnection lines;
  • the chips may be arranged on external pin pads in a flip-chip manner with their functional surfaces facing downward, wherein each chip has a fine interconnect pin pad and a non-fine interconnect pin pad, the fine interconnect pin pad being arranged at an end of the functional surface of each chip close to an adjacent chip and arranged to face the rewiring layer, and the non-fine interconnect pin pad being arranged on the functional surface of each chip and electrically interconnected with the external pin pad of the interconnection line;
  • a plastic encapsulation material may be used to perform plastic encapsulation on the side of the rewiring layer opposite to the temporary carrier to form a plastic encapsulation layer, so that the chip is embedded in the plastic encapsulation layer;
  • the temporary carrier and the strippable material may be removed to obtain the mold package-rewiring layer assembly, so that a second side of the rewiring layer opposite to the first side is fully exposed;
  • the obtained plastic encapsulation-rewiring layer assembly can be turned over, and a groove can be formed on the plastic encapsulation-rewiring layer assembly from the second side of the rewiring layer, so that the fine interconnection pin pads of the chip embedded in the plastic encapsulation layer are exposed;
  • Inter-chip fine interconnection lines can be made between chips, so that the fine interconnection pin pads of the chips form electrical interconnections;
  • the grooves can be filled with insulating materials to cover the fine interconnection lines between chips and form insulating inserts;
  • An insulating protective layer may be formed over the insulating inlay and the rewiring layer;
  • Vias may be formed on the insulating protection layer and package external pin solder balls and/or bumps may be prepared.
  • forming a rewiring layer on the strippable material includes: arranging or preparing a sacrificial block in an area where a groove is to be formed on a first side of the rewiring layer; forming a groove on the plastic encapsulation-rewiring layer assembly from a second side of the rewiring layer includes: forming a through hole penetrating the rewiring layer, and removing the sacrificial block to form the groove, so that the fine interconnect pin pads of the chip embedded in the plastic encapsulation layer are exposed.
  • the chip may be flip-chip mounted on the external pin pad using a self-alignment patch technology, a reflow soldering process, a thermocompression bonding process, or a thermocompression ultrasonic bonding process.
  • the lower portion of the functional surface of each chip and the gaps between the non-fine interconnect pin pads may be bottom-filled so that there is no gap between the plastic encapsulation layer and the rewiring layer.
  • the grooves may be formed by processes such as laser drilling, thermal dissociation, solvent cleaning, or dry etching.
  • the preparation of fine interconnection lines between chips can adopt semiconductor processes such as adaptive exposure technology, PVD technology, electroplating technology, 3D printing, etc.
  • the strippable material may be a layer of a temporary bonding material including thermal, chemical, optical, and mechanical stripping.
  • the inter-chip fine interconnection lines may be a single-layer line structure or a multi-layer line structure, and the inter-chip fine interconnection lines may include metal interconnection lines and insulating layers between the metal interconnection lines.
  • the inter-chip fine interconnection lines fabricated between chips include: prefabricating a fine interconnection circuit board as the inter-chip fine interconnection lines, and flipping the prefabricated fine interconnection circuit board onto the fine interconnection pin pads of the chip in a manner similar to the chip, so that the fine interconnection pin pads of adjacent chips are electrically interconnected.
  • the prefabricated fine interconnect circuit board can be prepared on a flat, non-deformable, and low CTE material such as silicon, glass, or ceramic.
  • the insulating insert may fill the groove so that the upper surface of the insulating insert is flush with the upper surface of the redistribution layer.
  • filling the groove with insulating material to cover the fine internal interconnection lines between chips and forming an insulating insert includes: filling the groove with insulating material to cover the fine internal interconnection lines between chips, and covering the surface of the redistribution layer on the side opposite to the plastic encapsulation layer with the insulating material, thereby forming a flange portion at the end of the insulating insert opposite to the plastic encapsulation layer.
  • the non-fine interconnect pin pads may be electrically interconnected with external pin pads of the interconnect circuits of the redistribution layer through the chip flip-chip bumps.
  • the present application provides a fan-out packaging structure with fine internal interconnection lines between chips, including: chips, fine internal interconnection lines between chips, a rewiring layer, a plastic encapsulation layer, an insulating insert, an insulating protective layer, and package external pin solder balls and/or bumps.
  • each chip may have a fine interconnection pin pad and a non-fine interconnection pin pad arranged on a functional surface
  • the functional surface of each chip may be arranged to face the first side of the plastic encapsulation layer
  • the fine interconnection pin pad of each chip may be arranged at the end of the functional surface close to the adjacent chip
  • the non-fine interconnection pin pad of each chip may be guided to the first side of the plastic encapsulation layer and directly electrically interconnected with the external pin pad of the rewiring layer;
  • the rewiring layer may be arranged adjacent to the first side of the plastic encapsulation layer, and the rewiring layer may include an insulating material layer, an interconnection line embedded in the insulating material layer, and an external pin pad, the external pin pad being arranged on a surface of the rewiring layer connected to the first side of the plastic encapsulation layer and used to form an electrical interconnection with the non-fine interconnection pin pad of the chip;
  • the insulating insert may be embedded in the rewiring layer and extend through the rewiring layer, and the insulating insert may be partially embedded in the plastic packaging layer, completely covering the fine internal interconnection lines between chips and partially covering the functional surfaces of the chips electrically interconnected by the fine internal interconnection lines between chips;
  • the insulating protection layer may be disposed on a side of the rewiring layer opposite to the plastic encapsulation layer and covers the insulating insert and the rewiring layer;
  • the package external pin solder balls and/or bumps may be arranged on the side of the insulating protection layer opposite to the rewiring layer and form electrical interconnections with the rewiring layer.
  • the inter-chip fine interconnection lines are arranged between adjacent chips and embedded in the package body, and the inter-chip fine interconnection lines enable the fine interconnection pin pads of adjacent chips to form electrical interconnection.
  • two or more chips may be arranged on the external pin pads in a flip-chip manner by using a self-alignment chip bonding technology, or a reflow soldering process, or a thermocompression bonding process or a thermocompression ultrasonic bonding process.
  • the inter-chip fine interconnection lines may be electrically connected only to the fine interconnection pin pads of adjacent chips.
  • the inter-chip fine interconnection lines may be a single-layer line structure or a multi-layer line structure, and the inter-chip fine interconnection lines include metal interconnection lines and insulating layers between the metal interconnection lines.
  • the fine interconnection lines between chips may be prefabricated fine interconnection circuit boards.
  • the prefabricated fine interconnect circuit board can be prepared on a flat, non-deformable, and low CTE material such as silicon, glass, or ceramic.
  • the line width and line spacing of the fine interconnection lines between chips may be smaller than the line width and line spacing of the interconnection lines in the redistribution layer.
  • the fine interconnection lines between chips can be directly covered on the functional surface of each chip and the molding material between the chips.
  • the end of the insulating insert opposite to the molding layer is configured to have a flange portion, and the flange portion covers the surface of the re-wiring layer opposite to the molding layer.
  • the non-fine interconnect pin pads may be electrically interconnected with external pin pads of the interconnect circuits through chip flip-chip bumps.
  • the fan-out packaging structure provided in the embodiment of the present application, and the fan-out packaging structure obtained by the manufacturing method provided in the embodiment of the present application use adaptive exposure technology to ensure the feasibility of preparing fine internal interconnection lines between chips; omit the process flow of preparing silicon bridges and the process flow of silicon bridge cutting and patching; use self-alignment patching technology to first perform high-precision patching, ensure the position accuracy and consistency of adjacent chips, and avoid the defect of difficult patch alignment. Therefore, the fan-out packaging structure provided in the present application and the packaging structure obtained by the manufacturing method provided in the present application can meet the user's usage needs in more scenarios.
  • FIG. 1 is a schematic flow chart showing a method for preparing a fan-out packaging structure according to an exemplary embodiment of the present disclosure
  • FIGS. 2 a to 9 are schematic diagrams showing a fan-out packaging structure during a manufacturing process according to an exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram showing a fan-out package structure with fine internal interconnection lines between chips according to an exemplary embodiment of the present disclosure.
  • Icon 100-fan-out packaging structure; 1-temporary carrier; 2-strippable material; 3-rewiring layer; 31-insulating material layer; 32-interconnection line; 33-external pin pad; 34-sacrificial block; 4-plastic layer; 41-chip; 42-non-fine interconnection pin pad; 43-fine interconnection pin pad; 44-fine internal interconnection line between chips; 441-metal interconnection line; 442-insulating layer; 45-plastic material; 46-chip flip-chip bump; 5-insulating insert; 51-groove; 6-insulating protective layer; 61-package external pin solder balls and/or bumps.
  • FIG1 is a schematic flow chart showing a method for preparing a fan-out packaging structure 100 according to an exemplary embodiment of the present disclosure. As shown in FIG1 , in this embodiment, the manufacturing method includes:
  • Step S100 providing a temporary carrier board.
  • Step S200 forming a peelable material on a temporary carrier.
  • Step S300 forming a rewiring layer on the strippable material, the rewiring layer comprising an insulating material layer, interconnection lines embedded in the insulating material layer, and external pin pads, which are arranged on a first side of the rewiring layer opposite to the temporary carrier and are used for interconnection lines.
  • Step 400 arrange the chip with its functional surface facing downward on the external pin pad in a flip-chip manner, wherein each chip has a fine interconnect pin pad and a non-fine interconnect pin pad, the fine interconnect pin pad is arranged at the end of the functional surface of each chip close to the adjacent chip and arranged to face the rewiring layer, and the non-fine interconnect pin pad is arranged on the functional surface of each chip and is electrically interconnected with the external pin pad of the interconnection line.
  • Step S500 Using a plastic encapsulation material to perform plastic encapsulation on the side of the rewiring layer opposite to the temporary carrier to form a plastic encapsulation layer, so that the chip is embedded in the plastic encapsulation layer.
  • Step S600 removing the temporary carrier and the strippable material to obtain a plastic package-rewiring layer assembly, so that a second side of the rewiring layer opposite to the first side is completely exposed.
  • Step S700 turning over the obtained plastic encapsulation-rewiring layer assembly, and forming a groove on the plastic encapsulation-rewiring layer assembly from the second side of the rewiring layer, so that the fine interconnection pin pads of the chip embedded in the plastic encapsulation layer are exposed.
  • Step S800 fabricating inter-chip fine interconnection circuits between chips, so that the fine interconnection pin pads of the chips form electrical interconnections.
  • Step S900 filling the grooves with insulating material to cover the fine interconnection lines between chips and form insulating inserts.
  • Step S1000 forming an insulating protection layer on the insulating insert and the rewiring layer.
  • Step S1100 forming via holes on the insulating protection layer and preparing package external pin solder balls and/or bumps.
  • the manufacturing method provided in the embodiment of the present application can manufacture a fan-out packaging structure 100 with fine internal interconnection lines between chips.
  • the fan-out packaging structure prepared by this method can realize internal interconnection between chips with different functions, realize accurate alignment of patches, and has simple process steps, saving costs, and adapting to the development needs of high-density advanced packaging.
  • FIG. 2a to 9 are schematic diagrams showing a fan-out package structure in a manufacturing process according to an exemplary embodiment of the present disclosure. Referring to FIG. 2a to 9 , the above steps S100 to S1100 are described in detail.
  • a strippable material 2 may be first formed on a temporary carrier 1 provided.
  • a strippable material 2 may be coated on the temporary carrier 1.
  • a rewiring layer 3 is then formed on the strippable material 2.
  • the rewiring layer 3 is deposited on the strippable material 2.
  • the rewiring layer 3 may include an insulating material layer 31, an interconnection line 32 embedded in the insulating material layer 31, and an external pin pad 33 for the interconnection line 32 disposed on a first side of the rewiring layer 3 opposite to the temporary carrier 1.
  • the external pin pad 33 may be used to connect the non-fine interconnection pin pads 42 of the chips 41 with different functions, thereby facilitating the flip-chip of the chips 41 with different functions.
  • the external pin pad 33 may be connected to the non-fine interconnection pin pads 42 of the chips 41 with different functions via the chip flip-chip bump 46.
  • the interconnection line 32 may be a multi-layer interconnection line.
  • the multi-layer interconnection lines 32 are interconnected by conductive materials in the through-holes.
  • the peelable material 2 is a material layer selected from temporary bonding materials capable of thermal, chemical, optical, and mechanical peeling.
  • the interconnection line 32 may be prepared by a redistribution layer (RDL) process.
  • the redistribution layer (RDL) process includes the following steps: providing a wafer; forming a Ti/Cu seed layer on the wafer by physical vapor deposition (PVD); depositing a photoresist on the Ti/Cu seed layer; patterning the photoresist; then electroplating Cu to form a Cu metal layer; removing the photoresist; and etching the Ti/Cu seed layer to form an RDL metal line.
  • PVD physical vapor deposition
  • this embodiment is different from the embodiment of FIG. 2 a in that a sacrificial block 34 can be arranged or prepared in the area where the groove 51 is to be formed on the first side of the rewiring layer.
  • the sacrificial block 34 can be removed through the through hole to form the groove 51, so that the chip fine interconnect pin pads of the chip 41 are exposed.
  • the sacrificial block 34 is located between the fine interconnect pin pads 43 of the chip 41 and the first side of the rewiring layer.
  • the height of the sacrificial block 34 can be just equal to the spacing between the fine interconnect pin pads 43 of the chip 41 and the first side of the rewiring layer or slightly less than the spacing.
  • the width of the sacrificial block 34 can be the same as the width of the groove 51, so that after the sacrificial block 34 is removed, the fine interconnect pin pads 43 of the adjacent chips 41 are exposed.
  • step S400 is involved.
  • the functional surface of the chips 41 with different functions is flipped down on the external pin pads 33 of the interconnection line 32 in the rewiring layer 3.
  • Each chip 41 may have a fine interconnection pin pad 43 and a non-fine interconnection pin pad 42.
  • the fine interconnection pin pad 43 may be arranged at the end of the functional surface of each chip 41 close to the adjacent chip 41 and arranged to face the rewiring layer 3, while the non-fine interconnection pin pad 42 may be arranged on the functional surface of each chip 41 and electrically interconnected with the external pin pad 33 of the interconnection line 32 through the chip flip bump 46.
  • the chips 41 with different functions may be flipped on the external pin pad 33 of the interconnection line 32 in the rewiring layer 3 by using a self-alignment chip placement technology, or a reflow process, or a thermocompression bonding process or a thermocompression ultrasonic bonding process.
  • This flip-chip is achieved by electrically interconnecting the non-fine interconnection pin pad 42 arranged on the functional surface of each chip 41 with the external pin pad 33 of the interconnection line 32 by means of the chip flip bump 46.
  • step S500 is involved.
  • a molding material 45 is used to perform molding on the opposite side of the temporary carrier 1 on the rewiring layer 3 to form a molding layer 4, so that the chip 41 is embedded in the molding layer 4.
  • the molding material 45 in the molding layer 4 can completely wrap the chip 41 and cover the upper surface of the rewiring layer 3.
  • the lower part of the functional surface of each chip 41 and the gap between the non-fine interconnect pin pads 42 are bottom-filled, so that the molding material fills the gap between each chip 41 and the rewiring layer 3, so that there is no gap between the molding layer 4 and the rewiring layer 3.
  • the molding material 45 in the molding layer 4 may cover the sacrificial block 34 located on the upper surface of the redistribution layer 3 .
  • step S600 is involved.
  • the temporary carrier 1 and the strippable material 2 can be removed to obtain a plastic encapsulation-rewiring layer assembly, so that the second side of the rewiring layer 3 opposite to the first side is completely exposed.
  • the plastic encapsulation-rewiring layer assembly includes a plastic encapsulation layer 4 and a rewiring layer 3.
  • the temporary carrier 1 is separated from the rewiring layer 3 by separating the strippable material 2 from the rewiring layer 3.
  • the strippable material 2 can be a material layer of a temporary bonding material including thermal, chemical, optical, and mechanical stripping.
  • step S700 is involved.
  • the obtained plastic encapsulation-rewiring layer assembly can be turned over to form a groove 51 on the plastic encapsulation-rewiring layer assembly from the second side of the rewiring layer 3.
  • the groove 51 can extend from the second side of the rewiring layer 3 through the rewiring layer 3 and at least a portion of the plastic encapsulation layer 4 to expose the fine interconnect pin pads 43 of the chip 41 embedded in the plastic encapsulation layer 4.
  • the groove 51 can expose a portion of the functional surface of each chip 41 and the fine interconnect pin pads 43 of each chip 41.
  • the groove 51 can be formed by laser drilling, thermal dissociation, solvent cleaning or dry etching.
  • the obtained plastic encapsulation-rewiring layer assembly can be flipped over, and then a through hole extending from the second side of the rewiring layer 3 through the rewiring layer 3 is formed on the rewiring layer 3, and then the sacrificial block 34 is removed through the through hole to expose the fine interconnect pin pads 43 of the chip 41 embedded in the plastic encapsulation layer 4.
  • the plastic encapsulation material 45 between the sacrificial block 34 and the chip 41 may be removed by using a process such as laser drilling or solvent cleaning.
  • step S800 is involved.
  • Fine inter-chip interconnection lines 44 are made between the chips 41 so that the fine interconnection pin pads 43 of the chips 41 are electrically interconnected.
  • fine inter-chip interconnection lines 44 are prepared between the functional surfaces of the chips 41 with different functions so that the fine interconnection pin pads 43 of the chips 41 with different functions are electrically interconnected.
  • the fine inter-chip interconnection lines 44 can be a single-layer line structure or a multi-layer line structure.
  • the fine inter-chip interconnection lines 44 can include metal interconnection lines 441 and an insulating layer 442 between the metal interconnection lines 441.
  • the fine inter-chip interconnection lines 44 can be directly covered on the functional surface of each chip 41 and the plastic encapsulation material 45 between the chips 41.
  • the preparation of the fine inter-chip interconnection lines 44 can adopt semiconductor processes such as adaptive exposure technology, PVD technology, electroplating technology, 3D printing, etc.
  • the adaptive exposure device automatically adjusts the exposure pattern according to the expansion, contraction, deformation, warping of the material and the offset, rotation, etc. of the chip.
  • the inter-chip fine interconnection lines 44 formed between the chips 41 include: a fine interconnection circuit board prefabricated as the inter-chip fine interconnection lines 44.
  • the prefabricated fine interconnection circuit board is flipped on the fine interconnection pin pads 43 of the chip 41 in a manner similar to the chip, so that the fine interconnection pin pads 43 of adjacent chips 41 are electrically interconnected.
  • the prefabricated fine interconnection circuit board can be prepared on a flat, non-deformable, and low CTE material such as silicon, glass, and ceramic.
  • step S900 is involved.
  • the groove 51 is filled with an insulating material to cover the fine internal interconnection line 44 between chips and form an insulating insert 5.
  • the remaining space of the groove 51 i.e., the space other than the fine internal interconnection line 44 between chips
  • the insulating material can fill and level the groove 51 so that the upper surface of the insulating insert 5 is flush with the upper surface of the rewiring layer 3.
  • the groove 51 can be filled with an insulating material to cover the fine internal interconnection line 44 between chips, and the surface of the rewiring layer 3 on the side opposite to the plastic encapsulation layer 4 can be covered with an insulating material, thereby forming a flange portion at the end of the insulating insert 5 opposite to the plastic encapsulation layer 4.
  • the flange portion can cover the rewiring layer 3.
  • one or more other rewiring layers can be continuously prepared on the flange portion of the insulating insert 5. The preparation method of other rewiring layers adopts the aforementioned RDL process.
  • steps S1000 and S1100 are involved.
  • An insulating protective layer 6 is formed on the insulating insert 5 and the rewiring layer 3. Vias are formed on the insulating protective layer 6 and package external pin solder balls and/or bumps 61 are prepared.
  • the package external pin solder balls 61 may be BGA package external pin solder balls, such as Sn-Ag-Cu alloy. In an optional embodiment, the package external pin solder balls 61 may also be replaced by package types such as DFN, QFN, etc.
  • the fan-out packaging structure with fine internal interconnection lines between chips is described in detail below with reference to FIG. 10 .
  • the fan-out package structure 100 includes a chip 41 , fine internal interconnection lines 44 between chips, a plastic encapsulation layer 4 , a redistribution layer 3 , an insulating insert 5 , an insulating protection layer 6 , and package external pin solder balls/or bumps 61 .
  • Each chip 41 may have a fine interconnect pin pad 43 and a non-fine interconnect pin pad 42 arranged on its functional surface.
  • the functional surface of each chip 41 may be arranged to face the first side of the plastic encapsulation layer 4, the fine interconnect pin pad 43 of each chip 41 may be arranged at the end of the functional surface close to the adjacent chip 41 and form an electrical interconnection with the fine interconnect pin pad 43 of the adjacent chip 41 through the fine internal interconnection line 44 between chips, and the non-fine interconnect pin pad 42 of each chip 41 is guided to the first side of the plastic encapsulation layer 4 and is directly electrically interconnected with the external pin pad 33 of the rewiring layer 3.
  • Two or more chips 41 may be flip-chip mounted on the external pin pad 33 of the interconnection line 32 in the rewiring layer 3 by self-alignment chip placement technology, or reflow soldering process, or thermocompression bonding process or thermocompression ultrasonic bonding process.
  • This flip-chip is achieved by electrically interconnecting the non-fine interconnect pin pad 43 arranged on the functional surface of each chip 41 with the external pin pad 33 of the interconnection line 32.
  • the non-fine interconnect pin pad 42 can be electrically interconnected with the external pin pad 33 of the interconnect line 32 in the rewiring layer 3 through the chip flip bump 46.
  • the fine inter-chip interconnect line 44 is arranged between adjacent chips 41 and buried in the package body, and the fine inter-chip interconnect line 44 makes the fine interconnect pin pad 43 of the adjacent chips 41 form an electrical interconnection.
  • the rewiring layer 3 may be arranged on the plastic encapsulation layer 4 and adjacent to the first side of the plastic encapsulation layer 4.
  • the rewiring layer 3 may include an insulating material layer 31, an interconnection line 32 embedded in the insulating material layer 31, and an external pin pad 33 provided on the surface of the rewiring layer 3 connected to the first side of the plastic encapsulation layer 4 for forming electrical interconnection with the non-fine interconnection pin pad 42 of the chip 41.
  • the interconnection line 32 and the external pin pad 33 of the interconnection line 32 are provided in the insulating material layer 31 of the rewiring layer 3.
  • the external pin pad 33 is electrically interconnected with the non-fine interconnection pin pad 42 of each chip 41.
  • the external pin pad 33 may be electrically interconnected with the non-fine interconnection pin pad 42 through the chip flip-chip bump 46. There is no gap between the plastic encapsulation layer 4 and the rewiring layer 3.
  • the insulating insert 5 may be embedded in the rewiring layer 3 and extend through the rewiring layer 3.
  • the insulating insert 5 may be partially embedded in the plastic layer 4, completely covering the fine inter-chip interconnection line 44 and partially covering the functional surface of the chip 41 electrically interconnected by the fine inter-chip interconnection line 44.
  • the fine inter-chip interconnection line 44 is arranged between the functional surfaces of the chips 41 with different functions, so that the fine interconnection pin pads 43 of the chips 41 with different functions are electrically interconnected.
  • the fine inter-chip interconnection line 44 includes a metal interconnection line 441 and an insulating layer 442 between the metal interconnection lines 441.
  • the fine inter-chip interconnection line 44 is electrically connected only to the fine interconnection pin pads 43 of the adjacent chip 41.
  • the fine inter-chip interconnection line 44 is a single-layer line structure or a multi-layer line structure.
  • the line width and line spacing of the fine inter-chip interconnection line 44 is smaller than the line width and line spacing of the interconnection line 32 in the rewiring layer 3.
  • the inter-chip fine interconnection lines 44 directly cover the exposed functional surface of each chip 41 and the molding material 45 between the chips 41 .
  • the inter-chip fine interconnection circuit 44 may be a prefabricated fine interconnection circuit board.
  • the prefabricated fine interconnection circuit board is flipped on the fine interconnection pin pads 43 of the chip 41 in a similar manner to the chip, so that the fine interconnection pin pads 43 of adjacent chips 41 are electrically interconnected.
  • the prefabricated fine interconnection circuit board may be made on a flat, non-deformable, and low CTE material such as silicon, glass, or ceramic.
  • the insulating insert 5 fills the remaining space of the groove 51 (i.e., the space except the fine inter-chip interconnection line 44) to cover the fine inter-chip interconnection line 44. That is, the insulating insert 5 completely covers the fine inter-chip interconnection line 44.
  • the insulating insert 5 fills and levels the groove 51 so that the upper surface of the insulating insert 5 is flush with the upper surface of the rewiring layer 3.
  • the end of the insulating insert 5 opposite to the plastic encapsulation layer 4 is configured to have a flange portion, which covers the surface of the rewiring layer 3 on the side opposite to the plastic encapsulation layer 4.
  • one or more other rewiring layers are arranged on the flange portion of the insulating insert 5.
  • the insulating protective layer 6 can be arranged on the side of the rewiring layer 3 opposite to the plastic layer 4, and covers the insulating insert 5 and the rewiring layer 3.
  • the package external pin solder balls and/or bumps 61 can be arranged on the side of the insulating protective layer 6 opposite to the rewiring layer 3 and form electrical interconnections with the rewiring layer 3.
  • the package external pin solder balls 61 can be BGA package external pin solder balls, such as Sn-Ag-Cu alloy. In an optional embodiment, the package external pin solder balls 61 can also be replaced by package types such as DFN, QFN, etc.
  • the selection of metal materials is non-limiting in the present disclosure.
  • the metal material may include at least one of copper, aluminum, silver or gold.
  • the fan-out packaging structure provided in the present application and the fan-out packaging structure manufactured by the manufacturing method provided in the present application enable manufacturers to simplify the process flow and save costs, and can be applied to the field of semiconductor packaging technology.

Abstract

本申请的实施例提供了一种扇出封装结构及其制备方法，涉及芯片技术领域。本申请实施例提供的扇出封装结构，以及本申请实施例提供的制备方法制备得到的扇出封装结构，在芯片的功能面之间具有芯片间精细内互连线路，使相邻芯片的精细互连引脚焊盘形成电互连。因此，本申请提供的扇出封装结构以及本申请提供的制备方法所制得的封装结构简化工艺流程、节约成本。

Description

具备芯片间精细内互连线路的扇出封装结构及其制造方法 技术领域
本申请涉及芯片异构集成和先进封装技术领域，具体而言，涉及一种具备芯片间精细内互连线路的扇出封装结构及其制造方法。
背景技术
目前，扇出封装芯片间精细互连线路的制备方法有两种。
第一种制备方法如下：在硅、玻璃、陶瓷等平坦、不易变形、CTE系数小的材料上预先制备好精细互连线路(也被统称为硅桥，该精细互连线路的线宽线距可以小于5μm，甚至小于2μm)，然后切割成单个硅桥，最后埋置在IC载板(印刷线路板)内。在将芯片进行倒装贴片时，芯片的精细互连引脚焊盘贴装在硅桥的互连引脚焊盘上，芯片的非精细互连引脚焊盘与IC载板内的其他互连线路(线宽线距大于5μm，甚至大于7μm)电连接。
第二种制备方法如下：在硅、玻璃、陶瓷等平坦、不易变形、CTE系数小的材料上预先制备好精细互连线路(也被统称为硅桥，该精细互连线路的线宽线距可以小于5μm，甚至小于2μm)，然后切割成精细互连线个体，被埋置在扇出封装塑封材料中，或同芯片一样贴在临时键合材料上，然后将芯片倒装贴片，芯片的精细互连引脚与硅桥的互连引脚电连接，芯片的非精细互连引脚与扇出封装中的其他互连线电连接。
上述两种制备方法导致成本高，硅片(硅桥)埋置和贴片位置精度难以控制，尤其是2个硅桥间的间距位置精度控制困难，造成跨硅桥芯片贴片对位困难。
发明内容
本申请提供一种具备芯片间内互连线路的扇出封装结构及其制造方法，目的至少包括，降低成本，降低工艺难度，确保跨硅桥芯片贴片对位精度高。
本申请的实施例可以这样实现：
第一方面，本申请提供一种具备芯片间精细内互连线路的扇出封装结构的制造方法，包括：
可以提供临时载板；
可以在临时载板上形成可剥离材料；
可以在可剥离材料上形成再布线层，该再布线层包括绝缘材料层、嵌设在绝缘材料层中的互连线路、以及外接引脚焊盘，所述外接引脚焊盘设置在再布线层的与临时 载板相背的第一侧上且用于互连线路；
可以将芯片的功能面向下以倒装的方式布设在外接引脚焊盘上，其中，每个芯片具有精细互连引脚焊盘和非精细互连引脚焊盘，精细互连引脚焊盘设置在各个芯片的功能面的靠近相邻芯片的端部处并且设置成面向再布线层，而非精细互连引脚焊盘设置在各个芯片的功能面上并且与互连线路的外接引脚焊盘电互连；
可以利用塑封材料在再布线层上的与临时载板相背的一侧上进行塑封以形成塑封层，使得芯片嵌埋在塑封层中；
可以去除临时载板和可剥离材料以获得塑封-再布线层组件，使得再布线层的与第一侧相反的第二侧完全暴露；
可以将所获得的塑封-再布线层组件进行翻转，从再布线层的第二侧在塑封-再布线层组件上形成凹槽，使得嵌埋在塑封层中的芯片的精细互连引脚焊盘露出；
可以制作在芯片之间的芯片间精细内互连线路，使芯片的精细互连引脚焊盘形成电互连；
可以利用绝缘材料填充凹槽以覆盖芯片间精细内互连线路并形成绝缘嵌件；
可以在绝缘嵌件和再布线层之上形成绝缘保护层；以及
可以在绝缘保护层上形成过孔并制备封装外接引脚焊球和/或凸点。
在一些可选的实施方式中，在可剥离材料上形成再布线层包括：可以在再布线层的第一侧将要形成凹槽的区域布设或者制备牺牲块；从再布线层的第二侧在塑封-再布线层组件上形成凹槽包括：形成穿透再布线层的通孔，并且去除牺牲块，以形成凹槽，使得嵌埋在塑封层中的芯片的精细互连引脚焊盘露出。
在一些可选的实施方式中，可以采用自对位贴片技术、或者回流焊工艺、或者热压键合工艺或热压超声键合工艺将芯片以倒装的方式布设在外接引脚焊盘上。
在一些可选的实施方式中，在进行塑封之前，可以对每个芯片的功能面的下部以及非精细互连引脚焊盘之间的空隙进行底部填充，使得塑封层与再布线层之间没有间隙。
在一些可选的实施方式中，可以采用激光打孔、热解离、溶剂清洗或干法蚀刻等工艺形成凹槽。
在一些可选的实施方式中，芯片间精细内互连线路的制备可以采用自适应曝光技术、PVD技术、电镀技术、3D打印等半导体工艺。
在一些可选的实施方式中，可剥离材料可以是包括热、化学、光学、机械剥离的临时键合材料中的一层材料层。
在一些可选的实施方式中，芯片间精细内互连线路可以是单层线路结构或多层线路结构，并且芯片间精细内互连线路可以包括金属互连线以及金属互连线之间的绝缘层。
在一些可选的实施方式中，制作在芯片之间的芯片间精细内互连线路包括：预制作为芯片间精细内互连线路的精细互连线路板，以及将预制的精细互连线路板以与芯片类似的方式倒装在芯片的精细互连引脚焊盘上，使相邻芯片的精细互连引脚焊盘形成电互连。
在一些可选的实施方式中，预制的精细互连线路板可以是在硅、玻璃、陶瓷等平坦、不易变形、CTE系数小的材料上制备的。
在一些可选的实施方式中，绝缘嵌件可以将凹槽填平，以使绝缘嵌件的上表面与再布线层的上表面平齐。
在一些可选的实施方式中，利用绝缘材料填充所述凹槽以覆盖所述芯片间精细内互连线路并形成绝缘嵌件包括：利用绝缘材料填充所述凹槽以覆盖所述芯片间精细内互连线路，并且利用所述绝缘材料覆盖所述再布线层的与所述塑封层相背的一侧的表面，从而在所述绝缘嵌件的与所述塑封层相背的一端形成凸缘部。
在一些可选的实施方式中，非精细互连引脚焊盘可以通过芯片倒装凸块与再布线层的互连线路的外接引脚焊盘电互连。
第二方面，本申请提供一种具备芯片间精细内互连线路的扇出封装结构，包括：芯片、芯片间精细内互连线路、再布线层、塑封层、绝缘嵌件、绝缘保护层、封装外接引脚焊球/或凸点。在塑封层中可以嵌埋有两个或更多个芯片，每个芯片可以具有设置在功能面上的精细互连引脚焊盘和非精细互连引脚焊盘，每个芯片的功能面可以被设置成面向塑封层的第一侧，每个芯片的精细互连引脚焊盘可以被设置在功能面的靠近相邻芯片的端部处，并且每个芯片的非精细互连引脚焊盘可以被引导至塑封层的第一侧并且与再布线层的外接引脚焊盘直接电互连；
再布线层可以被布设成与塑封层的第一侧相邻接，再布线层可以包括绝缘材料层、嵌设在绝缘材料层中的互连线路、以及外接引脚焊盘，该外接引脚焊盘被设置在再布线层的与塑封层的第一侧相连的表面上并且用于与芯片的非精细互连引脚焊盘形成电互连；
绝缘嵌件可以嵌设在再布线层中且延伸贯穿再布线层，并且绝缘嵌件可以部分地嵌设在塑封层中，完全覆盖芯片间精细内互连线路并且部分地覆盖由芯片间精细内互连线路实现电互连的芯片的功能面；
绝缘保护层可以设置在再布线层的与塑封层相背的一侧，并且覆盖绝缘嵌件和再布线层；以及
封装外接引脚焊球和/或凸点可以被设置在绝缘保护层的与再布线层相背的一侧上且与再布线层形成电互连，
其中，芯片间精细内互连线路被布设在相邻芯片之间，并且被埋置在封装体内，该芯片间精细内互连线路使相邻芯片的精细互连引脚焊盘形成电互连。
在一些可选的实施方式中，两个或更多个芯片可以通过自对位贴片技术、或者回流焊工艺、或者热压键合工艺或热压超声键合工艺以倒装的方式布设在外接引脚焊盘上。
在一些可选的实施方式中，芯片间精细内互连线路可以仅与相邻芯片的精细互连引脚焊盘电连接。
在一些可选的实施方式中，芯片间精细内互连线路可以是单层线路结构或多层线路结构，并且芯片间精细内互连线路包括金属互连线以及金属互连线之间的绝缘层。
在一些可选的实施方式中，芯片间精细内互连线路可以是预制的精细互连线路板。
在一些可选的实施方式中，预制的精细互连线路板可以是在硅、玻璃、陶瓷等平坦、不易变形、CTE系数小的材料上制备的。
在一些可选的实施方式中，芯片间精细内互连线路的线宽线距可以小于再布线层中的互连线路的线宽线距。
在一些可选的实施方式中，，芯片间精细内互连线路可以直接覆盖在每个芯片的功能面以及芯片之间的塑封材料上。
在一些可选的实施方式中，绝缘嵌件的与塑封层相背的一端构造成具有凸缘部，该凸缘部覆盖再布线层的与塑封层相背的一侧的表面。
在一些可选的实施方式中，非精细互连引脚焊盘可以通过芯片倒装凸块与互连线路的外接引脚焊盘电互连。
本申请实施例的有益效果例如包括：
本申请实施例提供的扇出封装结构，以及本申请实施例提供的制造方法制造得到的扇出封装结构，采用自适应曝光技术更可确保制备芯片间精细内互连线路的可行性；省略了制备硅桥工艺流程和硅桥切割贴片工艺流程；采用自对位贴片技术先进行高精度贴片，确保了相邻芯片位置精度和一致性，避免贴片对位困难的缺陷。因此，本申请提供的扇出封装结构以及本申请提供的制造方法所制得的封装结构能够满足用户在更多场景下的使用需求。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为示出了根据本公开的示例性实施方式的用于制备扇出封装结构的方法的示意性流程图；
图2a至图9为示出了根据本公开的示例性实施方式的扇出封装结构在制造过程中的示意图。
图10为示出了根据本公开的示例性实施方式的具备芯片间精细内互连线路的扇出封装结构的示意图。
图标：100-扇出封装结构；1-临时载板；2-可剥离材料；3-再布线层；31-绝缘材料层；32-互连线路；33-外接引脚焊盘；34-牺牲块；4-塑封层；41-芯片；42-非精细互连引脚焊盘；43-精细互连引脚焊盘；44-芯片间精细内互连线路；441-金属互连线；442-绝缘层；45-塑封材料；46-芯片倒装凸块；5-绝缘嵌件；51-凹槽；6-绝缘保护层；61-封装外接引脚焊球和/或凸点。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本申请实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围，而是仅仅表示本申请的选定实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，若出现术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，若出现术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
需要说明的是，在不冲突的情况下，本申请的实施例中的特征可以相互结合。
接下来，将参照附图对根据本公开的示例性实施方式所提供的制备扇出封装结构的制备方法以及所制备的扇出封装结构进行详细的描述。
图1为示出了根据本公开的示例性实施方式的用于制备扇出封装结构100的制备方法的示意性流程图。如图1所示，在本实施例中，制造方法包括：
步骤S100，提供临时载板。
步骤S200，在临时载板上形成可剥离材料。
步骤S300，在可剥离材料上形成再布线层，该再布线层包括绝缘材料层、嵌设在绝缘 材料层中的互连线路、以及外接引脚焊盘，该外接引脚焊盘被设置在再布线层的与临时载板相背的第一侧上并且用于互连线路。
步骤400，将芯片的功能面向下以倒装的方式布设在外接引脚焊盘上，其中，每个芯片具有精细互连引脚焊盘和非精细互连引脚焊盘，精细互连引脚焊盘设置在各个芯片的功能面的靠近相邻芯片的端部处并且设置成面向再布线层，而非精细互连引脚焊盘设置在各个芯片的功能面上并且与互连线路的外接引脚焊盘电互连。
步骤S500，利用塑封材料在再布线层上的与临时载板相背的一侧上进行塑封以形成塑封层，使得芯片嵌埋在塑封层中。
步骤S600，去除临时载板和可剥离材料以获得塑封-再布线层组件，使得再布线层的与第一侧相反的第二侧完全暴露。
步骤S700，将所获得的塑封-再布线层组件进行翻转，从再布线层的第二侧在塑封-再布线层组件上形成凹槽，使得嵌埋在塑封层中的芯片的精细互连引脚焊盘露出。
步骤S800，制作在芯片之间的芯片间精细内互连线路，使芯片的精细互连引脚焊盘形成电互连。
步骤S900，利用绝缘材料填充凹槽以覆盖芯片间精细内互连线路并形成绝缘嵌件。
步骤S1000，在绝缘嵌件和再布线层之上形成绝缘保护层。
步骤S1100，在绝缘保护层上形成过孔并制备封装外接引脚焊球和/或凸点。
通过本申请实施例提供的制造方法可以制造出具备芯片间精细内互连线路的扇出封装结构100。通过该方法制备的扇出封装结构能够实现不同功能的芯片之间的内部互连，实现贴片的精确对位，工艺步骤简单，节省成本，适应了高密度先进封装的发展需求。
图2a至图9为示出了根据本公开的示例性实施方式的扇出封装结构在制造过程中的示意图。下面参考图2a至图9，对上述步骤S100～S1100进行详细介绍。
参考图2a和图2b，涉及步骤S100至S300。可以先在提供的临时载板1上形成可剥离材料2。例如，可以在临时载板1上涂覆可剥离材料2。然后在可剥离材料2上形成再布线层3。例如在可剥离材料2上沉积再布线层3。再布线层3可以包括绝缘材料层31、嵌设在绝缘材料层31中的互连线路32、以及设置在再布线层3的与临时载板1相背的第一侧上的用于互连线路32的外接引脚焊盘33。外接引脚焊盘33可以用于连接不同功能的芯片41的非精细互连引脚焊盘42，从而有利于不同功能的芯片41的倒装。在可选的实施例中，外接引脚焊盘33可以经由芯片倒装凸块46连接不同功能的芯片41的非精细互连引脚焊盘42。在可选的实施例中，互连线路32可以是多层互连线路。多层互连线路32之间通过穿通孔内的导电材料互连。在可选的实施例中，可剥离材料2是包括热、化学、光学、机械剥离的临时键合材料中的一层材料层。
在可选的实施例中，互连线路32的制备可以采用重布线层(RDL)工艺。重布线层(RDL)工艺包括如下步骤：提供晶圆；采用物理气相沉积(PVD)，在晶圆上形成Ti/Cu种子层；在Ti/Cu种子层上沉积光阻；使光阻图形化；然后电镀Cu，形成Cu金属层；去除光阻；以及对Ti/Cu种子层进行刻蚀，形成RDL金属线。
参考图2b，该实施例与图2a的实施例不同，原因在于：可以在再布线层的第一侧将要形成凹槽51的区域布设或者制备牺牲块34。在通过从再布线层3的第二侧上形成穿透再布线层3的通孔以后，可以经由通孔去除牺牲块34来形成凹槽51，使芯片41的芯片精细互连引脚焊盘露出。牺牲块34位于芯片41的精细互连引脚焊盘43与再布线层的第一侧之间。牺牲块34的高度可以恰好等于芯片41的精细互连引脚焊盘43与再布线层的第一侧之间的间距或者略小于该间距。牺牲块34的宽度可以与凹槽51的宽度相同，以在牺牲块34被去除之后，使相邻芯片41的精细互连引脚焊盘43都露出。
参考图3a和图3b，涉及步骤S400。将不同功能的芯片41的功能面向下倒装在再布线层3中的互连线路32的外接引脚焊盘33上。每个芯片41可以具有精细互连引脚焊盘43和非精细互连引脚焊盘42。精细互连引脚焊盘43可以设置在各个芯片41的功能面的靠近相邻芯片41的端部处并且设置成面向再布线层3，而非精细互连引脚焊盘42可以设置在各个芯片41的功能面上并且通过芯片倒装凸块46与互连线路32的外接引脚焊盘33电互连。可以采用自对位贴片技术、或者回流焊工艺、或者热压键合工艺或热压超声键合工艺将不同功能的芯片41倒装在再布线层3中的互连线路32的外接引脚焊盘33上。这种倒装贴片是通过使设置在每个芯片41的功能面上的非精细互连引脚焊盘42与互连线路32的外接引脚焊盘33借助于芯片倒装凸块46电互连实现的。通过这些工艺，实现了贴片的精确对位，提高了贴片速度。
参考图4a和图4b，涉及步骤S500。利用塑封材料45在再布线层3上的临时载板1相背的一侧上进行塑封以形成塑封层4，使得芯片41嵌埋在塑封层4中。塑封层4中的塑封材料45可以完全包裹芯片41，并且覆盖再布线层3的上表面。在可选的实施例中，在进行塑封之前，对每个芯片41的功能面的下部以及非精细互连引脚焊盘42之间的空隙进行底部填充，使塑封材料填满每个芯片41与再布线层3之间的间隙，从而塑封层4与再布线层3之间没有间隙。
在图4b中，塑封层4中的塑封材料45可以覆盖位于再布线层3的上表面上的牺牲块34。
参考图5a和图5b，涉及步骤S600。可以去除临时载板1和可剥离材料2，以获得塑封-再布线层组件，使得再布线层3的与第一侧相反的第二侧完全暴露。塑封-再布线层组件包括塑封层4和再布线层3。通过将可剥离材料2与再布线层3分离，以将临时载板1与 再布线层3分离。在可选的实施例中，可剥离材料2可以是包括热、化学、光学、机械剥离的临时键合材料中的一层材料层。
参考图6，涉及步骤S700。可以将所获得的塑封-再布线层组件进行翻转，从再布线层3的第二侧在塑封-再布线层组件上形成凹槽51。凹槽51可以从再布线层3的第二侧延伸穿过再布线层3和塑封层4的至少一部分而使得嵌埋在塑封层4中的芯片41的精细互连引脚焊盘43露出。凹槽51可以使每个芯片41的功能面的一部分以及每个芯片41的精细互连引脚焊盘43暴露。可以采用激光打孔、热解离、溶剂清洗或干法蚀刻等工艺形成凹槽51。
在另一实施例中，可以将所获得的塑封-再布线层组件进行翻转，然后在再布线层3上形成从再布线层3的第二侧延伸穿过再布线层3的通孔，再然后通过该通孔去除牺牲块34，使得嵌埋在塑封层4中的芯片41的精细互连引脚焊盘43露出。
在又一实施例中，在牺牲块34与芯片41之间具有塑封材料45的情况下，可以采用激光打孔或溶剂清洗等工艺去除牺牲块34与芯片41之间的塑封材料45。
参考图7，涉及步骤S800。制作在芯片41之间的芯片间精细内互连线路44，使芯片41的精细互连引脚焊盘43形成电互连。在凹槽51内，在不同功能的芯片41的功能面之间制备芯片间精细内互连线路44，使不同功能的芯片41的精细互连引脚焊盘43形成电互连。芯片间精细内互连线路44可以是单层线路结构或多层线路结构。芯片间精细内互连线路44可以包括金属互连线441以及金属互连线441之间的绝缘层442。芯片间精细内互连线路44可以直接覆盖在每个芯片41的功能面以及芯片41之间的塑封材料45上。芯片间精细内互连线路44的制备可以采用自适应曝光技术、PVD技术、电镀技术、3D打印等半导体工艺。在自适应曝光技术中，根据材料的涨缩、变形、翘曲以及芯片的偏移、旋转等情况，自适应曝光设备自动调整曝光图案。
在另一实施例中，制作在芯片41之间的芯片间精细内互连线路44包括：预制作为芯片间精细内互连线路44的精细互连线路板。将预制的精细互连线路板以与芯片类似的方式倒装在芯片41的精细互连引脚焊盘43上，使相邻芯片41的精细互连引脚焊盘43形成电互连。预制的精细互连线路板可以是在硅、玻璃、陶瓷等平坦、不易变形、CTE系数小的材料上制备的。
参考图8，涉及步骤S900。利用绝缘材料填充凹槽51，以覆盖芯片间精细内互连线路44并形成绝缘嵌件5。可以利用绝缘材料填充凹槽51的剩余空间(即，除了芯片间精细内互连线路44之外的空间)，以覆盖芯片间精细内互连线路44。即，绝缘材料可以将芯片间精细内互连线路44完全覆盖。绝缘材料可以将凹槽51填满填平，以使绝缘嵌件5的上表面与再布线层3的上表面平齐。在可选的实施例中，可以利用绝缘材料填充凹槽51以覆盖 芯片间精细内互连线路44，并且可以利用绝缘材料覆盖再布线层3的与塑封层4相背的一侧的表面，从而在绝缘嵌件5的与塑封层4相背的一端形成凸缘部。凸缘部可以覆盖在再布线层3之上。在可选的实施例中，可以在绝缘嵌件5的凸缘部之上继续制备一个或更多个其他的再布线层。其他的再布线层的制备方法采用前述的RDL工艺。
参考图9，涉及步骤S1000和步骤S1100。在绝缘嵌件5和再布线层3之上形成绝缘保护层6。在绝缘保护层6上形成过孔并制备封装外接引脚焊球和/或凸点61。封装外接引脚焊球61可以是BGA封装外接引脚焊球，诸如Sn-Ag-Cu合金。在可选的实施例中，也可以用DFN、QFN等封装类型来代替封装外接引脚焊球61。
下面参考图10详细描述的具备芯片间精细内互连线路的扇出封装结构。
扇出封装结构100包括芯片41、芯片间精细内互连线路44、塑封层4、再布线层3、绝缘嵌件5、绝缘保护层6、封装外接引脚焊球/或凸点61。
在塑封层4中可以嵌埋有两个或更多个芯片41。每个芯片41可以具有设置在其功能面上的精细互连引脚焊盘43和非精细互连引脚焊盘42。每个芯片41的功能面可以被设置成面向塑封层4的第一侧，每个芯片41的精细互连引脚焊盘43可以设置在功能面的靠近相邻芯片41的端部处并且通过芯片间精细内互连线路44与相邻芯片41的精细互连引脚焊盘43形成电互连，并且每个芯片41的非精细互连引脚焊盘42被引导至塑封层4的第一侧并且与再布线层3的外接引脚焊盘33直接电互连。两个或更多个芯片41可以通过自对位贴片技术、或者回流焊工艺、或者热压键合工艺或热压超声键合工艺倒装在再布线层3中的互连线路32的外接引脚焊盘33上。这种倒装贴片是通过使设置在每个芯片41的功能面上的非精细互连引脚焊盘43与互连线路32的外接引脚焊盘33电互连实现的。非精细互连引脚焊盘42可以通过芯片倒装凸块46与再布线层3中的互连线路32的外接引脚焊盘33电互连。芯片间精细内互连线路44被布设在相邻芯片41之间，并且被埋置在封装体内，芯片间精细内互连线路44使相邻芯片41的精细互连引脚焊盘43形成电互连。经由这样的配置，实现了贴片的精确对位，提高了贴片速度。
再布线层3可以被布设在塑封层4之上并且与塑封层4的第一侧相邻接。再布线层3可以包括绝缘材料层31、嵌设在绝缘材料层31中的互连线路32、以及设置在再布线层3的与塑封层4的第一侧相连的表面上的用于与芯片41的非精细互连引脚焊盘42形成电互连的外接引脚焊盘33。在再布线层3的绝缘材料层31中设置有互连线路32以及互连线路32的外接引脚焊盘33。外接引脚焊盘33与每个芯片41的非精细互连引脚焊盘42电互连。外接引脚焊盘33可以通过芯片倒装凸块46与非精细互连引脚焊盘42电互连。塑封层4与再布线层3之间没有间隙。
绝缘嵌件5可以嵌设在再布线层3中且延伸贯穿再布线层3。绝缘嵌件5可以部分地嵌 设在塑封层4中，完全覆盖芯片间精细内互连线路44并且部分地覆盖由芯片间精细内互连线路44实现电互连的芯片41的功能面。在凹槽51内，在不同功能的芯片41的功能面之间设置有芯片间精细内互连线路44，使不同功能的芯片41的精细互连引脚焊盘43形成电互连。芯片间精细内互连线路44包括金属互连线441以及金属互连线441之间的绝缘层442。芯片间精细内互连线路44仅与相邻芯片41的精细互连引脚焊盘43电连接。芯片间精细内互连线路44是单层线路结构或多层线路结构。芯片间精细内互连线路44的线宽线距小于再布线层3中的互连线路32的线宽线距。芯片间精细内互连线路44直接覆盖在每个芯片41的暴露的功能面以及芯片41之间的塑封材料45上。
在另一实施例中，芯片间精细内互连线路44可以是预制的精细互连线路板。预制的精细互连线路板以与芯片类似的方式倒装在芯片41的精细互连引脚焊盘43上，使相邻芯片41的精细互连引脚焊盘43形成电互连。预制的精细互连线路板可以是在硅、玻璃、陶瓷等平坦、不易变形、CTE系数小的材料上制备的。
绝缘嵌件5填充凹槽51的剩余空间(即，除了芯片间精细内互连线路44之外的空间)，以覆盖芯片间精细内互连线路44。即，绝缘嵌件5将芯片间精细内互连线路44完全覆盖。绝缘嵌件5将凹槽51填满填平，以使绝缘嵌件5的上表面与再布线层3的上表面平齐。在可选的实施例中，绝缘嵌件5的与塑封层4相背的一端构造成具有凸缘部，该凸缘部覆盖再布线层3的与塑封层4相背的一侧的表面。在可选的实施例中，在绝缘嵌件5的凸缘部之上设置有一个或更多个其他的再布线层。
绝缘保护层6可以设置在再布线层3的与塑封层4相背的一侧，并且覆盖绝缘嵌件5和再布线层3。封装外接引脚焊球和/或凸点61可以设置在绝缘保护层6的与再布线层3相背的一侧上且与再布线层3形成电互连。封装外接引脚焊球61可以是BGA封装外接引脚焊球，诸如Sn-Ag-Cu合金。在可选的实施例中，也可以用DFN、QFN等封装类型来代替封装外接引脚焊球61。
尽管未示出，但可以理解的是，金属材料的选取在本公开中是非限制性的。例如，在本公开示出的一些实施方式中，金属材料可以包括铜、铝、银或金中的至少一种。
虽然已经参照示例性实施方式对本公开进行了描述，但是应当理解，本公开并不局限于文中详细描述和示出的具体实施方式。在不偏离本公开的权利要求书所限定的范围的情况下，本领域技术人员可以对示例性实施方式做出各种改变。
在以上对本公开的示例性实施方式的描述中所提及和/或示出的特征可以以相同或类似的方式结合到一个或更多个其他实施方式中，与其他实施方式中的特征相组合或替代其他实施方式中的相应特征。这些经组合或替代所获得的技术方案也应当被视为包括在本公开的保护范围内。
工业实用性
本申请提供的扇出封装结构以及本申请提供的制造方法所制得的扇出封装结构，使得制造者可以简化工艺流程、节约成本，可以应用于半导体封装技术领域。

Claims (23)

  1. 一种具备芯片间精细内互连线路的扇出封装结构的制造方法，其特征在于，包括：
    提供临时载板；
    在所述临时载板上形成可剥离材料；
    在所述可剥离材料上形成再布线层，所述再布线层包括绝缘材料层、嵌设在所述绝缘材料层中的互连线路、以及外接引脚焊盘，所述外接引脚焊盘设置在所述再布线层的与所述临时载板相背的第一侧上且用于所述互连线路；
    将芯片的功能面向下以倒装的方式布设在所述外接引脚焊盘上，其中，每个芯片具有精细互连引脚焊盘和非精细互连引脚焊盘，所述精细互连引脚焊盘设置在各个芯片的功能面的靠近相邻芯片的端部处并且设置成面向所述再布线层，而所述非精细互连引脚焊盘设置在各个芯片的功能面上并且与所述互连线路的所述外接引脚焊盘电互连；
    利用塑封材料在所述再布线层上的与所述临时载板相背的一侧上进行塑封以形成塑封层，使得所述芯片嵌埋在所述塑封层中；
    去除所述临时载板和所述可剥离材料以获得塑封-再布线层组件，使得所述再布线层的与所述第一侧相反的第二侧完全暴露；
    将所获得的塑封-再布线层组件进行翻转，从所述再布线层的所述第二侧在所述塑封-再布线层组件上形成凹槽，使得嵌埋在所述塑封层中的所述芯片的所述精细互连引脚焊盘露出；
    制作在所述芯片之间的芯片间精细内互连线路，使所述芯片的所述精细互连引脚焊盘形成电互连；
    利用绝缘材料填充所述凹槽以覆盖所述芯片间精细内互连线路并形成绝缘嵌件；
    在所述绝缘嵌件和所述再布线层之上形成绝缘保护层；以及
    在所述绝缘保护层上形成过孔并制备封装外接引脚焊球和/或凸点。
  2. 根据权利要求1所述的制造方法，其特征在于，
    在所述可剥离材料上形成再布线层包括：在所述再布线层的第一侧将要形成所述凹槽的区域布设或制备牺牲块；
    从所述再布线层的第二侧在所述塑封-再布线层组件上形成凹槽包括：形成穿透所述再布线层的通孔，并且去除所述牺牲块，以形成所述凹槽，使得嵌埋在所述塑封层中的所述芯片的所述精细互连引脚焊盘露出。
  3. 根据权利要求1所述的制造方法，其特征在于，采用自对位贴片技术、或者回流焊工艺、或者热压键合工艺或热压超声键合工艺将所述芯片以倒装的方式布设在所述外接引脚焊盘上。
  4. 根据权利要求1所述的制造方法，其特征在于，在进行所述塑封之前，对所述每个芯片的功能面的下部以及所述非精细互连引脚焊盘之间的空隙进行底部填充，使得所述塑封层与所述再布线层之间没有间隙。
  5. 根据权利要求1所述的制造方法，其特征在于，采用激光打孔、热解离、溶剂清洗或干法蚀刻等工艺形成所述凹槽。
  6. 根据权利要求1所述的制造方法，其特征在于，所述芯片间精细内互连线路的制备采用自适应曝光技术、PVD技术、电镀技术、3D打印等半导体工艺。
  7. 根据权利要求1所述的制造方法，其特征在于，所述可剥离材料是包括热、化学、光学、机械剥离的临时键合材料中的一层材料层。
  8. 根据权利要求1所述的制造方法，其特征在于，所述芯片间精细内互连线路是单层线路结构或多层线路结构，并且所述芯片间精细内互连线路包括金属互连线以及所述金属互连线之间的绝缘层。
  9. 根据权利要求1所述的制造方法，其特征在于，制作在所述芯片之间的芯片间精细内互连线路包括：预制作为所述芯片间精细内互连线路的精细互连线路板，以及将预制的所述精细互连线路板以与芯片类似的方式倒装在所述芯片的精细互连引脚焊盘上，使所述相邻芯片的精细互连引脚焊盘形成电互连。
  10. 根据权利要求9所述的制造方法，其特征在于，预制的所述精细互连线路板是在硅、玻璃、陶瓷等平坦、不易变形、CTE系数小的材料上制备的。
  11. 根据权利要求1所述的制造方法，其特征在于，所述绝缘嵌件将所述凹槽填平，以使所述绝缘嵌件的上表面与所述再布线层的上表面平齐。
  12. 根据权利要求1所述的制造方法，其特征在于，利用所述绝缘材料填充所述凹槽以覆盖所述芯片间精细内互连线路并形成所述绝缘嵌件包括：利用所述绝缘材料填充所述凹槽以覆盖所述芯片间精细内互连线路，并且利用所述绝缘材料覆盖所述再布线层的与所述塑封层相背的一侧的表面，从而在所述绝缘嵌件的与所述塑封层相背的一端形成凸缘部。
  13. 根据权利要求12所述的制造方法，其特征在于，所述非精细互连引脚焊盘通过芯片倒装凸块与所述再布线层的所述互连线路的所述外接引脚焊盘电互连。
  14. 一种具备芯片间精细内互连线路的扇出封装结构，其特征在于，所述扇出封装结构包括芯片、芯片间精细内互连线路、再布线层、塑封层、绝缘嵌件、绝缘保护层、 封装外接引脚焊球/或凸点；
    在所述塑封层中嵌埋有两个或更多个芯片，每个芯片具有设置在功能面上的精细互连引脚焊盘和非精细互连引脚焊盘，每个芯片的功能面被设置成面向所述塑封层的第一侧，每个芯片的所述精细互连引脚焊盘被设置在所述功能面的靠近相邻芯片的端部处，并且每个芯片的所述非精细互连引脚焊盘被引导至所述塑封层的第一侧并且与所述再布线层的外接引脚焊盘直接电互连；
    所述再布线层被布设成与所述塑封层的第一侧相邻接，所述再布线层包括绝缘材料层、嵌设在所述绝缘材料层中的互连线路、以及外接引脚焊盘，所述外接引脚焊盘设置在所述再布线层的与所述塑封层的第一侧相连的表面上并且用于与所述芯片的所述非精细互连引脚焊盘形成电互连；
    所述绝缘嵌件嵌设在所述再布线层中且延伸贯穿所述再布线层，并且所述绝缘嵌件部分地嵌设在所述塑封层中，完全覆盖所述芯片间精细内互连线路并且部分地覆盖由所述芯片间精细内互连线路实现电互连的芯片的功能面；
    所述绝缘保护层设置在所述再布线层的与所述塑封层相背的一侧，并且覆盖所述绝缘嵌件和所述再布线层；以及
    所述封装外接引脚焊球和/或凸点被设置在所述绝缘保护层的与所述再布线层相背的一侧上且与所述再布线层形成电互连，
    其中，所述芯片间精细内互连线路被布设在所述相邻芯片之间，并且被埋置在封装体内，所述芯片间精细内互连线路使所述相邻芯片的所述精细互连引脚焊盘形成电互连。
  15. 根据权利要求14所述的扇出封装结构，其特征在于，所述两个或更多个芯片通过自对位贴片技术、或者回流焊工艺、或者热压键合工艺或热压超声键合工艺以倒装的方式布设在所述外接引脚焊盘上。
  16. 根据权利要求14所述的扇出封装结构，其特征在于，所述芯片间精细内互连线路仅与相邻芯片的所述精细互连引脚焊盘电连接。
  17. 根据权利要求14所述的扇出封装结构，其特征在于，所述芯片间精细内互连线路是单层线路结构或多层线路结构，并且所述芯片间精细内互连线路包括金属互连线以及所述金属互连线之间的绝缘层。
  18. 根据权利要求14所述的扇出封装结构，其特征在于，所述芯片间精细内互连线路是预制的精细互连线路板。
  19. 根据权利要求18所述的扇出封装结构，其特征在于，所述预制的精细互连线路板是在硅、玻璃、陶瓷等平坦、不易变形、CTE系数小的材料上制备的。
  20. 根据权利要求14所述的扇出封装结构，其特征在于，所述芯片间精细内互连线路的线宽线距小于所述再布线层中的所述互连线路的线宽线距。
  21. 根据权利要求14所述的扇出封装结构，其特征在于，所述芯片间精细内互连线路直接覆盖在每个芯片的功能面以及所述芯片之间的塑封材料上。
  22. 根据权利要求14所述的扇出封装结构，其特征在于，所述绝缘嵌件的与所述塑封层相背的一端构造成具有凸缘部，所述凸缘部覆盖所述再布线层的与所述塑封层相背的一侧的表面。
  23. 根据权利要求14所述的扇出封装结构，其特征在于，所述非精细互连引脚焊盘通过芯片倒装凸块与所述再布线层的所述互连线路的所述外接引脚焊盘电互连。
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CN111244082A (zh) * 2018-11-29 2020-06-05 台湾积体电路制造股份有限公司 封装体
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