WO2020000933A1 - 一种控制形变的扇出封装结构及其制造方法 - Google Patents

一种控制形变的扇出封装结构及其制造方法 Download PDF

Info

Publication number
WO2020000933A1
WO2020000933A1 PCT/CN2018/121703 CN2018121703W WO2020000933A1 WO 2020000933 A1 WO2020000933 A1 WO 2020000933A1 CN 2018121703 W CN2018121703 W CN 2018121703W WO 2020000933 A1 WO2020000933 A1 WO 2020000933A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
fan
plating
package structure
layer
Prior art date
Application number
PCT/CN2018/121703
Other languages
English (en)
French (fr)
Inventor
孙鹏
曹立强
任玉龙
Original Assignee
华进半导体封装先导技术研发中心有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华进半导体封装先导技术研发中心有限公司 filed Critical 华进半导体封装先导技术研发中心有限公司
Publication of WO2020000933A1 publication Critical patent/WO2020000933A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the invention relates to the technical field of semiconductor packaging, in particular to a fan-out packaging structure for controlling deformation and a manufacturing method thereof.
  • FIG. 1 is a schematic cross-sectional view of a conventional Fan-Out package structure 100, where 101 is an IC chip and 102 is a plastic encapsulation layer. Because IC chips contain plastic packaging materials, silicon and metal materials, and the thermal expansion coefficients of the volume sides between silicon and the plastic packaging materials are different in each of the X, Y, and Z directions, the IC chips will be subject to thermal expansion and contraction during processing. The effect of the effect causes the surface warpage of the package.
  • a fan-out packaging structure for controlling deformation including: a chip; a plastic packaging layer, The chip is disposed at a middle portion of the plastic encapsulation layer, and the plastic encapsulation layer covers the first side and the side of the chip; an empty chip, the empty chip is disposed in the plastic encapsulation layer, and the chip A substantially symmetrical layout; re-layout wiring, the re-layout wiring is provided on the second side of the chip and is electrically connected to the pad of the chip, the second side is opposite to the first side; the substrate is soldered A pad, the substrate pad forming an electrical connection with the chip pad through the re-layout wiring, and an external solder ball.
  • the empty chip is located at an edge of the plastic encapsulation layer, and one side of the empty chip is exposed from the plastic encapsulation layer.
  • the empty chip is located at an edge of the plastic encapsulation layer, and a side of the empty chip is wrapped by the plastic encapsulation layer.
  • the re-layout wiring is one or more layers.
  • the deformed fan-out package structure further includes a conductive via electrically connecting the chip to the re-layout wiring and / or a conductive via electrically connecting an adjacent layer of the re-layout wiring. hole.
  • the external solder balls are tin-lead solder balls, tin-silver solder balls, tin-silver-copper solder balls, and copper posts.
  • a manufacturing method of a fan-out package structure for controlling deformation includes: mounting a chip and an empty chip on a carrier board; plastically sealing the chip and the empty chip with a plastic sealing material; Forming a core package substrate; separating the core package substrate from the carrier board; forming a plating seed layer; patterning a plating mask layer on the plating seed layer and plating to form redistribution wiring and pads; removing The plating mask layer and the plating seed layer; forming an external solder ball on the pad; and dicing to form a single package structure.
  • the chip and the empty chip are mounted on the carrier board, the chip and the empty chip are temporarily bonded to the temporary bonding carrier board by a bonding glue, and the key
  • the glue is separated by hot release, mechanical, laser or UV irradiation.
  • the patterning of a plating mask layer on the plating seed layer and electroplating to form a redistribution wiring and pads further include: coating, photolithography, developing to form a plating window, and photolithography. Glue a plating mask; fill the plating window with plating to form the re-layout wiring and the pad.
  • the method for forming an external solder ball on the pad is reflowing after the ball is planted or reflowing after plating the solder ball material.
  • the invention provides a fan-out package structure for controlling deformation and a method for manufacturing the same.
  • the carrier-molded plastic package is used to reconstruct a substrate containing a chip and a dummy chip (Dummy), and combined with processes such as re-layout and wiring to form a fan-out package structure to improve the overall
  • the proportion of silicon material in the fan-out package structure is to balance the influence of the thermal expansion coefficient of the plastic packaging material, reduce the equivalent thermal expansion coefficient of the package, and thereby reduce the package warpage.
  • FIG. 1 is a schematic cross-sectional view of a conventional fan-out type packaging structure 100.
  • FIG. 2A is a schematic cross-sectional view of a deformed fan-out package structure 200 according to an embodiment of the present invention.
  • FIG. 2B is a schematic top plan view of a chip layout of a fan-out package structure 200 for controlling deformation according to an embodiment of the present invention.
  • 3A to 3H are schematic cross-sectional views illustrating a process of forming a fan-out package structure 200 for controlling deformation according to an embodiment of the present invention.
  • FIG. 4 shows a flowchart 400 of forming a fan-out package structure 200 for controlling deformation according to an embodiment of the present invention.
  • the invention provides a fan-out package structure for controlling deformation and a method for manufacturing the same.
  • the carrier-molded plastic package is used to reconstruct a substrate containing a chip and a dummy chip (Dummy), and then combined with processes such as re-layout and wiring to form a fan-out package structure to improve the whole.
  • the proportion of silicon material in the fan-out package structure is to balance the influence of the thermal expansion coefficient of the plastic packaging material, reduce the equivalent thermal expansion coefficient of the package, and thereby reduce the package warpage.
  • the chip 210 is located in the middle of the deformed fan-out package structure 200. As shown in FIG. 2A and FIG. 2B, the chip 210 has chip pads on the front side, and forms an electrical connection with the Re-Distribution Layout (RDL) 240 Or signal connection, the back side and the side opposite to the front side are surrounded by the plastic sealing layer 230.
  • RDL Re-Distribution Layout
  • Dummy chips 220 are located at the edge of the fan-out package structure 200 that controls the deformation. There are multiple dummy chips 220 and the basic layout is symmetrical about the chip 210.
  • the dummy chip (Dummy) mainly plays the role of increasing the proportion of silicon material in the overall packaging structure, thereby balancing the influence of the thermal expansion coefficient of the plastic packaging material and reducing the equivalent thermal expansion coefficient of the overall packaging structure.
  • the molding layer 230 encapsulates the chip 210 and the dummy chip 220 from the back and side directions of the chip 210 and the dummy chip 220.
  • the plastic sealing layer 230 protects the chip, and on the other hand, it also plays the role of reconstructing the chip 210 and the dummy chip 220 into a package.
  • a re-distribution layout layer (RDL) 240 is located on the front side of the chip 210, which is similar to the formation method of the redistribution layout layer of the existing fan-out package structure, and has a similar structure and function.
  • the re-layout wiring layer 240 may be a single layer or a plurality of layers, depending on design requirements.
  • the material of the re-layout wiring layer is generally copper, and the formation method is generally formed by pattern plating.
  • an external pad is also designed and formed at the same time, and the external pad is used to form an electrical and / or signal connection with an external system.
  • the external solder ball 250 is formed on the above-mentioned external pad, and is used to form an electrical and / or signal connection with an external system.
  • the external solder ball can be a tin-lead solder ball, a tin-silver solder ball, a tin-silver-copper solder ball, and a copper pillar, etc.
  • the formation method can be realized by plating, ball-planting, reflow soldering and other processes.
  • FIGS. 3A to 3H are schematic cross-sectional views of a process for forming a deformation-controlling fan-out package structure 200 according to an embodiment of the present invention
  • FIG. 4 is a diagram illustrating forming a deformation-controlling fan according to an embodiment of the present invention
  • a flowchart 400 of the packaging structure 200 is shown.
  • a chip 320 and an empty chip 330 are mounted on a carrier board 310.
  • the front surface of the chip 320 (the surface where the device and the pad 321 are located) is adjacent to the carrier board 310 and is located at the center position of the carrier board; the empty chip 330 is located at the edge position of the carrier board and forms a basic basis for the chip 320 Symmetrical relationship.
  • the chip 320 and the empty chip 330 are mounted on the carrier board 310 by temporary bonding, the carrier board 310 is a temporary bonding substrate, and the chip 320 and the empty chip 330 are bonded by a bonding layer Bonded to the temporary bonding substrate, the bonding adhesive layer can be a laser or UV irradiation peelable material.
  • the chip 320 and the empty chip 330 are plastic-molded by the plastic-molding layer 340, and the core-packaged substrate is re-constructed.
  • the plastic encapsulation layer 340 needs to cover the entire chip 320 and the empty chip 330, and has a certain surplus thickness and a certain structural strength after curing, so as to meet the subsequent process requirements.
  • the carrier board is a light-transmitting material
  • the bonding layer is a laser-peelable material.
  • the method of debonding is to detach the bonds by irradiating laser light on the light-transmitting surface of the carrier board.
  • bond residues and the like are present after the bonds are removed, they can be removed by processes such as washing.
  • a plating seed layer 350 is formed on the surface of the chip pad on the core package substrate.
  • the method of forming the electroplated seed layer can be performed by sputtering, chemical plating, etc.
  • a copper electroplated seed layer is formed by sputtering about 200 angstroms of chromium and about 2000 angstroms of copper.
  • a photoresist plating mask 360 is formed on the plating seed layer 350, and the patterned plating forms a redistribution wiring (RDL) and a pad 370.
  • the re-layout wiring layer may have multiple layers and may be fabricated according to specific design requirements.
  • the pads are located at the outermost layer and may be formed at the same time as the outermost redistribution wiring layer or may be formed independently.
  • the material of the redistribution wiring (RDL) and the pad 370 is usually copper.
  • step 406 the photoresist plating mask layer 360 and the plating seed layer 350 are removed.
  • the photoresist mask layer 360 is removed and cleaned by a stripping process, and then the plating seed layer 350 is removed by an etching process.
  • processes such as etching time and parameters need to be controlled to prevent the risk of weak bonding or even detachment of the re-layout wiring layer caused by over-etching problems.
  • an external solder ball 380 is formed on the formed pad of the core package substrate.
  • the external solder ball 380 is used to form an electrical and / or signal connection with an external system.
  • the external solder ball 380 may be a tin-lead solder ball, a tin-silver solder ball, a tin-silver-copper solder ball, and a copper pillar, and the formation method thereof may be specifically implemented through processes such as electroplating, ball implantation, and reflow soldering.
  • step 408 as shown in FIG. 3H, dicing is performed to form a single package structure.
  • the dicing position is performed in accordance with AA ', BB' shown in FIG. 3G.
  • the empty chip 330 leaks from the edge portion of the package body, and has a good thermal conductivity effect.
  • FIG. 5 is a schematic cross-sectional and layout top view of a fan-out package structure 500 for controlling deformation according to another embodiment of the present invention.
  • the deformation-controlling fan-out packaging structure 500 includes a chip 510, a plastic encapsulation layer 520, and an empty chip 530.
  • the main difference from the foregoing deformation-controlling fan-out packaging structure 200 is that the empty chip 530 is only close to the package. The edges of the body are not exposed.
  • a slide-type plastic package is used to reconstruct a substrate containing a chip and a dummy chip (Dummy), and then combined with processes such as re-layout and wiring to form a fan-out package structure.

Abstract

一种控制形变的扇出封装结构，包括：芯片(210)；塑封层(230)，所述芯片(210)设置在所述塑封层(230)的中间部位，且所述塑封层(230)覆盖于所述芯片(210)第一面及侧面；空芯片(220)，所述空芯片(220)设置在所述塑封层(230)内，且关于所述芯片(210)成基本对称布局；重新布局布线(240)，所述重新布局布线(240)设置在所述芯片(210)与第一面相对的第二面，且电连接至所述芯片(210)的焊盘；基板焊盘，所述基板焊盘通过所述重新布局布线(240)与所述芯片焊盘形成电连接；以及外接焊球(250)。

Description

一种控制形变的扇出封装结构及其制造方法 技术领域
本发明涉及半导体封装技术领域，尤其涉及一种控制形变的扇出封装结构及其制造方法。
背景技术
随着电子产品轻、小型化的要求，IC芯片封装趋于薄型、小型化。图1示出一种传统扇出型(Fan-Out)封装结构100的剖面示意图，其中，101为IC芯片，102为塑封层。由于IC芯片含有塑封材料、硅及金属材料，而硅与塑封材料之间的体积边的热膨胀系数在X、Y、Z各个方向上的不同，因此IC芯片在加工工艺中会受到热涨冷缩效应的影响，造成封装产生表面翘曲。
过度翘曲不仅使塑封之后的后续制程(如切筋、成形等)难度加大，还会使成品塑封IC芯片在SMT组装时制程不良率增高，造成芯片及封装裂纹等严重器件失效问题。
因此，现在亟待一种解决方法来克服上述扇出型封装体的封装翘曲问题。
发明内容
针对现有技术中存在的塑封材料与芯片的热膨胀系数不匹配导致的封装翘曲等问题，根据本发明的一个实施例，提供一种控制形变的扇出封装结构，包括：芯片；塑封层，所述芯片设置在所述塑封层的中间部位，且所述塑封层覆盖于所述芯片的第一面及侧面；空芯片，所述空芯片设置在所述塑封层内，且关于所述芯片成基本对称布局；重新布局布线，所述重新布局布线设置在所述芯片的第二面，且电连接至所述芯片的焊盘，所述第二面与所述第一面相对；基板焊盘，所述基板焊盘通过所述重新布局布线与所述芯片焊盘形成电连接；以及外接焊球。
在本发明的一个实施例中，所述空芯片位于所述塑封层的边缘，且所述空 芯片的一个侧边从所述塑封层裸露出来。
在本发明的一个实施例中，所述空芯片位于所述塑封层的边缘，且所述空芯片的侧边被所述塑封层包裹。
在本发明的一个实施例中，所述重新布局布线为一层或多层。
在本发明的一个实施例中，该控制形变的扇出封装结构还包括电连接所述芯片至所述重新布局布线的导电通孔和/或电连接相邻层所述重新布局布线的导电通孔。
在本发明的一个实施例中，所述外接焊球为锡铅焊球、锡银焊球、锡银铜焊球、铜柱。
根据本发明的另一个实施例，提供一种控制形变的扇出封装结构的制造方法，包括：在载板上贴装芯片和空芯片；通过塑封材料塑封所述芯片和所述空芯片，重构形成有芯封装基板；将所述有芯封装基板与所述载板分离；形成电镀种子层；在所述电镀种子层上图形化电镀掩膜层并电镀形成重新布局布线及焊盘；去除所述电镀掩膜层及所述电镀种子层；在所述焊盘上形成外接焊球；以及划片形成单颗封装结构。
在本发明的另一个实施例中，所述在载板上贴装芯片和空芯片时通过键合胶将所述芯片和所述空芯片临时键合到临时键合载板上，所述键合胶通过热拆、机械、激光或UV照射拆键合分离。
在本发明的另一个实施例中，所述在所述电镀种子层上图形化电镀掩膜层并电镀形成重新布局布线及焊盘进一步包括：涂胶、光刻、显影形成电镀窗口和光刻胶电镀掩膜；电镀填充所述电镀窗口形成所述重新布局布线及所述焊盘。
在本发明的另一个实施例中，所述在所述焊盘上形成外接焊球的方法为植球后进行回流，或电镀焊球材料后进行回流。
本发明提供一种控制形变的扇出封装结构及其制造方法，利用载片塑封重构含有芯片和空芯片(Dummy Die)基板，再结合重新布局布线等工艺形成扇出型封装结构，提高整体扇出型封装结构中的硅材质占比以平衡塑封材料热膨胀系数的影响，减小封装体的等效热膨胀系数，从而降低了封装体翘曲。
附图说明
为了进一步阐明本发明的各实施例的以上和其它优点和特征，将参考附图来呈现本发明的各实施例的更具体的描述。可以理解，这些附图只描绘本发明的典型实施例，因此将不被认为是对其范围的限制。在附图中，为了清楚明了，相同或相应的部件将用相同或类似的标记表示。
图1示出一种传统扇出型封装结构100的剖面示意图。
图2A示出根据本发明的一个实施例的一种控制形变的扇出封装结构200的剖面示意图。
图2B示出根据本发明的一个实施例的一种控制形变的扇出封装结构200的芯片布局俯视示意图。
图3A至图3H示出根据本发明的一个实施例形成一种控制形变的扇出封装结构200的过程剖面示意图。
图4示出的是根据本发明的一个实施例形成一种控制形变的扇出封装结构200的流程图400。
图5示出根据本发明又一个施例的一种控制形变的扇出封装结构500的剖面和布局俯视示意图。
具体实施方式
在以下的描述中，参考各实施例对本发明进行描述。然而，本领域的技术人员将认识到可在没有一个或多个特定细节的情况下或者与其它替换和/或附加方法、材料或组件一起实施各实施例。在其它情形中，未示出或未详细描述公知的结构、材料或操作以免使本发明的各实施例的诸方面晦涩。类似地，为了解释的目的，阐述了特定数量、材料和配置，以便提供对本发明的实施例的全面理解。然而，本发明可在没有特定细节的情况下实施。此外，应理解附图中示出的各实施例是说明性表示且不一定按比例绘制。
在本说明书中，对“一个实施例”或“该实施例”的引用意味着结合该实施例描述的特定特征、结构或特性被包括在本发明的至少一个实施例 中。在本说明书各处中出现的短语“在一个实施例中”并不一定全部指代同一实施例。
需要说明的是，本发明的实施例以特定顺序对工艺步骤进行描述，然而这只是为了方便区分各步骤，而并不是限定各步骤的先后顺序，在本发明的不同实施例中，可根据工艺的调节来调整各步骤的先后顺序。
本发明提供一种控制形变的扇出封装结构及其制造方法，利用载片塑封重构含有芯片和空芯片(Dummy Die)基板，再结合重新布局布线等工艺形成扇出型封装结构，提高整体扇出型封装结构中的硅材质占比以平衡塑封材料热膨胀系数的影响，减小封装体的等效热膨胀系数，从而降低了封装体翘曲。
下面结合图2A和图2B来详细介绍根据本发明的一个实施例的一种控制形变的扇出封装结构。图2A示出根据本发明的一个实施例的一种控制形变的扇出封装结构200的剖面示意图；图2B示出根据本发明的一个实施例的一种控制形变的扇出封装结构200的芯片布局俯视示意图。如图2A和图2B所示，该控制形变的扇出封装结构200进一步包括芯片210、空芯片(Dummy Die)220、塑封层230、重新布局布线层(Re-Distribution Layout,RDL)240以及外接焊球250。
芯片210位于该控制形变的扇出封装结构200中间位置，如图2A、图2B所示，芯片210的正面具有芯片焊盘，与重新布局布线层(Re-Distribution Layout,RDL)240形成电和或信号连接，与正面相对的背面及侧面被塑封层230包围。
空芯片(Dummy Die)220位于该控制形变的扇出封装结构200边缘位置，具有多个，且基本布局成关于芯片210对称。空芯片(Dummy Die)主要起到提高整体封装结构的硅材质占比的作用，从而平衡塑封材料的热膨胀系数影响，降低整体封装结构的等效热膨胀系数。
塑封层230从芯片210和空芯片(Dummy Die)220的背面和侧面方向包封住芯片210和空芯片(Dummy Die)220。塑封层230一方面起到对芯片的保护作用，另一方面也起到重构芯片210和空芯片(Dummy Die)220为一个封装体的作用。
重新布局布线层(Re-Distribution Layout,RDL)240位于芯片210的正面，其与现有的扇出型封装结构的重新布局布线层的形成方法类似，结构和功能也 类似。在本发明的一个实施例中，重新布局布线层240可以为单层或多层，具体根据设计的需要。重新布局布线层的材料一般为铜，其形成方式一般通过图形化电镀形成。此外，在最外层的重新布局布线层中，还同时设计形成外接焊盘，外接焊盘用于与外接系统形成电和/或信号连接。
外接焊球250形成在上述的外接焊盘上，用于与外接系统形成电和或信号连接。外接焊球可以为锡铅焊球、锡银焊球、锡银铜焊球以及铜柱等，其形成方式可以通过电镀、植球、回流焊等工艺实现。
下面结合图3A至图3H以及图4来详细描述形成控制形变的扇出封装结构200的过程。图3A至图3H示出根据本发明的一个实施例形成一种控制形变的扇出封装结构200的过程剖面示意图；图4示出的是根据本发明的一个实施例形成一种控制形变的扇出封装结构200的流程图400。
首先，在步骤401，如图3A所示，在载板310上贴装芯片320和空芯片330。在本发明的一个实施例中，芯片320正面(器件、焊盘321所在面)与载板310临近，且位于载板的中心位置；空芯片330位于载板的边缘位置且关于芯片320形成基本对称关系。在本发明的又一实施例中，在载板310上贴装芯片320和空芯片330是通过临时键合实现，载板310为临时键合基板，芯片320和空芯片330通过键合胶层键合到临时键合基板上，该键合胶层可以为激光或UV照射可剥离材料。
接下来，在步骤402，如图3B所示，通过塑封层340塑封芯片320和空芯片330，重新构建形成有芯封装基板。在本发明的一个实施例中，塑封层340需要覆盖住整个芯片320和空芯片330，并具有一定盈余厚度，在固化后具有一定的结构强度，从而满足后续的工艺要求。
然后，在步骤403，如图3C所示，将重构形成的有芯封装基板与载板310拆键合。在本发明的一个实施例中，载板为透光材料，键合层为激光可剥离材料，拆键合的方法是通过在载板透光面照射激光来进行拆键合。此外，在拆键合后如果存在键合残留物等，可以采用清洗等工艺予以去除。
接下来，在步骤404，如图3D所示，在有芯封装基板上的芯片焊盘所在面形成电镀种子层350。形成电镀种子层的方法可以通过溅射、化学镀等，在本发明的一个具体实施例中，通过溅射约200埃的铬与约2000埃的铜形 成铜电镀种子层。
然后，在步骤405，如图3E所示，在电镀种子层350上形成光刻胶电镀掩膜360，图形化电镀形成重新布局布线(RDL)及焊盘370。在本发明的一个实施例中，重新布局布线层可以有多层，可根据具体设计需要制作，其中焊盘位于最外层，可以和最外层重新布局布线层同时形成，也可以独自形成。重新布局布线(RDL)及焊盘370的材料通常为铜。
接下来，在步骤406，如图3F所示，去除光刻胶电镀掩膜层360及电镀种子层350。在本发明的一个实施例中，先通过去胶工艺去除光刻胶掩膜层360并清洗，再通过刻蚀工艺去除电镀种子层350。在去除电镀种子层350的工艺过程中，需要控制刻蚀时间、参数等工艺，以防止过刻问题导致重新布局布线层结合力弱甚至脱离的风险。
然后，在步骤407，如图3G所示，在形成的有芯封装基板的焊盘上形成外接焊球380。外接焊球380用于与外接系统形成电和/或信号连接。外接焊球380可以为锡铅焊球、锡银焊球、锡银铜焊球以及铜柱等，其形成方式具体可以通过电镀、植球、回流焊等工艺实现。
最后，在步骤408，如图3H所示，划片形成单颗封装结构。在本发明的一个实施例中，划片的位置按照图3G所示的AA’、BB’进行。在划片后的封装结构中，空芯片330从封装体边缘部分漏出，具有较好的导热效果。
除了上述介绍的实施例之外，下面结合图5在介绍基于本发明的又一种控制形变的扇出封装结构。图5示出根据本发明又一个施例的一种控制形变的扇出封装结构500的剖面和布局俯视示意图。如图5所示，该种控制形变的扇出封装结构500包括芯片510、塑封层520和空芯片530，与前述种控制形变的扇出封装结构200的主要区别是，空芯片530只是接近封装体的边缘，并未裸露出来。
基于本发明提供的该种控制形变的扇出封装结构及其制造方法，利用载片塑封重构含有芯片和空芯片(Dummy Die)基板，再结合重新布局布线等工艺形成扇出型封装结构，提高整体扇出型封装结构中的硅材质占比以平衡塑封材料热膨胀系数的影响，减小封装体的等效热膨胀系数，从而降低了封装体翘曲。
尽管上文描述了本发明的各实施例，但是，应该理解，它们只是作为示例 来呈现的，而不作为限制。对于相关领域的技术人员显而易见的是，可以对其做出各种组合、变型和改变而不背离本发明的精神和范围。因此，此处所公开的本发明的宽度和范围不应被上述所公开的示例性实施例所限制，而应当仅根据所附权利要求书及其等同替换来定义。

Claims (10)

  1. 一种控制形变的扇出封装结构，包括：
    芯片；
    塑封层，所述芯片设置在所述塑封层的中间部位，且所述塑封层覆盖于所述芯片的第一面及侧面；
    空芯片，所述空芯片设置在所述塑封层内，且关于所述芯片成基本对称布局；
    重新布局布线，所述重新布局布线设置在所述芯片的第二面，且电连接至所述芯片的焊盘，所述第二面与所述第一面相对；
    基板焊盘，所述基板焊盘通过所述重新布局布线与所述芯片焊盘形成电连接；以及
    外接焊球。
  2. 如权利要求1所述的控制形变的扇出封装结构，其特征在于，所述空芯片位于所述塑封层的边缘，且所述空芯片的一个侧边从所述塑封层裸露出来。
  3. 如权利要求1所述的控制形变的扇出封装结构，其特征在于，所述空芯片位于所述塑封层的边缘，且所述空芯片的侧边被所述塑封层包裹。
  4. 如权利要求1所述的控制形变的扇出封装结构，其特征在于，所述重新布局布线为一层或多层。
  5. 如权利要求1所述的控制形变的扇出封装结构，其特征在于，还包括电连接所述芯片至所述重新布局布线的导电通孔和/或电连接相邻层所述重新布局布线的导电通孔。
  6. 如权利要求1所述的控制形变的扇出封装结构，其特征在于，所述外接焊球为锡铅焊球、锡银焊球、锡银铜焊球、铜柱。
  7. 一种控制形变的扇出封装结构的制造方法，包括：
    在载板上贴装芯片和空芯片；
    通过塑封材料塑封所述芯片和所述空芯片，重构形成有芯封装基板；
    将所述有芯封装基板与所述载板分离；
    形成电镀种子层；
    在所述电镀种子层上图形化电镀掩膜层并电镀形成重新布局布线及焊盘；
    去除所述电镀掩膜层及所述电镀种子层；
    在所述焊盘上形成外接焊球；以及
    划片形成单颗封装结构。
  8. 如权利要求7所述的方法，其特征在于，所述在载板上贴装芯片和空芯片时通过键合胶将所述芯片和所述空芯片临时键合到临时键合载板上，所述键合胶通过热拆、机械、激光或UV照射拆键合分离。
  9. 如权利要求7所述的方法，其特征在于，所述在所述电镀种子层上图形化电镀掩膜层并电镀形成重新布局布线及焊盘进一步包括：
    涂胶、光刻、显影形成电镀窗口和光刻胶电镀掩膜；
    电镀填充所述电镀窗口形成所述重新布局布线及所述焊盘。
  10. 如权利要求7所述的方法，其特征在于，所述在所述焊盘上形成外接焊球的方法为植球后进行回流，或电镀焊球材料后进行回流。
PCT/CN2018/121703 2018-06-25 2018-12-18 一种控制形变的扇出封装结构及其制造方法 WO2020000933A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810658730.9 2018-06-25
CN201810658730.9A CN108831866A (zh) 2018-06-25 2018-06-25 一种控制形变的扇出封装结构及其制造方法

Publications (1)

Publication Number Publication Date
WO2020000933A1 true WO2020000933A1 (zh) 2020-01-02

Family

ID=64138415

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/121703 WO2020000933A1 (zh) 2018-06-25 2018-12-18 一种控制形变的扇出封装结构及其制造方法

Country Status (2)

Country Link
CN (1) CN108831866A (zh)
WO (1) WO2020000933A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108831866A (zh) * 2018-06-25 2018-11-16 华进半导体封装先导技术研发中心有限公司 一种控制形变的扇出封装结构及其制造方法
CN112054036B (zh) * 2020-09-25 2024-02-09 上海先方半导体有限公司 图像传感芯片集成结构及其制造方法
CN117334639A (zh) * 2023-12-01 2024-01-02 长电集成电路(绍兴)有限公司 芯片封装结构及芯片封装方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103117279A (zh) * 2011-11-16 2013-05-22 台湾积体电路制造股份有限公司 形成芯片在晶圆的总成的方法
CN108122861A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 具有虚设管芯的扇出型封装结构
US20180174865A1 (en) * 2016-12-15 2018-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out structure and method of fabricating the same
CN108831866A (zh) * 2018-06-25 2018-11-16 华进半导体封装先导技术研发中心有限公司 一种控制形变的扇出封装结构及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212315A (ja) * 2008-03-04 2009-09-17 Elpida Memory Inc 半導体装置及びその製造方法
TWI597786B (zh) * 2013-12-19 2017-09-01 矽品精密工業股份有限公司 半導體封裝結構及其製法
US9922964B1 (en) * 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103117279A (zh) * 2011-11-16 2013-05-22 台湾积体电路制造股份有限公司 形成芯片在晶圆的总成的方法
CN108122861A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 具有虚设管芯的扇出型封装结构
US20180174865A1 (en) * 2016-12-15 2018-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out structure and method of fabricating the same
CN108831866A (zh) * 2018-06-25 2018-11-16 华进半导体封装先导技术研发中心有限公司 一种控制形变的扇出封装结构及其制造方法

Also Published As

Publication number Publication date
CN108831866A (zh) 2018-11-16

Similar Documents

Publication Publication Date Title
TWI576927B (zh) 半導體裝置及其製造方法
US11742327B2 (en) Semiconductor devices and methods of manufacturing semiconductor devices
CN109937476B (zh) 晶片级封装和方法
JP3142723B2 (ja) 半導体装置及びその製造方法
US7132312B2 (en) Method for fabricating semiconductor package having conductive bumps on chip
US8759964B2 (en) Wafer level package structure and fabrication methods
TWI582937B (zh) 封裝結構
TWI582921B (zh) 半導體封裝結構及其製作方法
TWI437674B (zh) 半導體導線元件、半導體封裝元件與半導體裝置
TW201405735A (zh) 柵格扇出晶圓級封裝和製造柵格扇出晶圓級封裝的方法
US8569885B2 (en) Stacked semiconductor packages and related methods
US8061024B2 (en) Method of fabricating a circuit board and semiconductor package.
KR101235498B1 (ko) 집적 수동 컴포넌트를 구비한 집적 회로를 패키징하기 위한 방법 및 시스템
WO2020000933A1 (zh) 一种控制形变的扇出封装结构及其制造方法
JP2003197856A (ja) 半導体装置
US9934989B1 (en) Process for forming leadframe having organic, polymerizable photo-imageable adhesion layer
US7906424B2 (en) Conductor bump method and apparatus
JP2010010174A (ja) 半導体装置の製造方法
US20060068332A1 (en) Method for fabricating carrier structure integrated with semiconductor element
CN110970381A (zh) 半导体器件和形成半导体器件的方法
US20150262920A1 (en) Integrated circuit package
KR20140086531A (ko) 패키지 기판 및 그 제조방법, 그리고 패키지 온 패키지 기판
TWI420610B (zh) 半導體裝置及其製造方法
CN111199924A (zh) 半导体封装结构及其制作方法
JP2016066649A (ja) 電子装置及び電子装置の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18924449

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18924449

Country of ref document: EP

Kind code of ref document: A1