CN110970381A - 半导体器件和形成半导体器件的方法 - Google Patents
半导体器件和形成半导体器件的方法 Download PDFInfo
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- CN110970381A CN110970381A CN201910926998.0A CN201910926998A CN110970381A CN 110970381 A CN110970381 A CN 110970381A CN 201910926998 A CN201910926998 A CN 201910926998A CN 110970381 A CN110970381 A CN 110970381A
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- 238000000034 method Methods 0.000 title claims abstract description 120
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000001465 metallisation Methods 0.000 claims abstract description 124
- 150000001875 compounds Chemical class 0.000 claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 claims abstract description 23
- 238000000465 moulding Methods 0.000 claims abstract description 22
- 230000008569 process Effects 0.000 claims description 100
- 229920002120 photoresistant polymer Polymers 0.000 claims description 98
- 239000004020 conductor Substances 0.000 claims description 45
- 238000007747 plating Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 13
- 239000010410 layer Substances 0.000 description 224
- 239000000758 substrate Substances 0.000 description 60
- 239000000463 material Substances 0.000 description 33
- 238000000059 patterning Methods 0.000 description 27
- 229910052802 copper Inorganic materials 0.000 description 18
- 239000010949 copper Substances 0.000 description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 17
- 238000001459 lithography Methods 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 230000003287 optical effect Effects 0.000 description 14
- 239000004593 Epoxy Substances 0.000 description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 12
- 230000007547 defect Effects 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000010936 titanium Substances 0.000 description 12
- 229910052719 titanium Inorganic materials 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 10
- 230000001186 cumulative effect Effects 0.000 description 9
- 230000007423 decrease Effects 0.000 description 9
- 238000005538 encapsulation Methods 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 239000011162 core material Substances 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 239000012778 molding material Substances 0.000 description 7
- 238000012360 testing method Methods 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 238000004528 spin coating Methods 0.000 description 6
- 238000002834 transmittance Methods 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000007772 electroless plating Methods 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000012876 topography Methods 0.000 description 5
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 239000005388 borosilicate glass Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 238000001723 curing Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 239000008393 encapsulating agent Substances 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000004380 ashing Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011152 fibreglass Substances 0.000 description 3
- 230000004907 flux Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 238000000748 compression moulding Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- -1 SOI Chemical compound 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- ZTXONRUJVYXVTJ-UHFFFAOYSA-N chromium copper Chemical compound [Cr][Cu][Cr] ZTXONRUJVYXVTJ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- CGZLUZNJEQKHBX-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti][Ti][W] CGZLUZNJEQKHBX-UHFFFAOYSA-N 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H01L2224/93—Batch processes
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- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
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- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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Abstract
半导体器件包括密封第一集成电路管芯和第二集成电路管芯的模塑料;位于模塑料、第一集成电路管芯和第二集成电路管芯上方的介电层;以及位于介电层上方并且将第一集成电路管芯电连接到第二集成电路管芯的金属化图案。金属化图案包括多条导线。多条导线中的每条导线从金属化图案的第一区域穿过金属化图案的第二区域连续延伸至金属化图案的第三区域;并且在金属化图案的第二区域中具有相同类型的制造异常。本发明的实施例还涉及形成半导体器件的方法。
Description
技术领域
本发明的实施例涉及半导体器件和形成半导体器件的方法。
背景技术
由于各个电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的不断改进,半导体工业经历了快速增长。在大多数情况下,集成密度的改进是由于最小部件尺寸的重复减小,这允许将更多组件集成到给定的区域。随着对缩小电子器件的需求的增长,出现了对半导体管芯的更小且更具创造性的封装技术的需求。这种封装系统的实例是叠层封装(PoP)技术。在PoP器件中,顶部半导体封装件堆叠件在底部半导体封装件的顶部上,以提供高水平的集成度和组件密度。PoP技术通常能够在印刷电路板(PCB)上生产具有功能增强和占用面积小的半导体器件。
发明内容
本发明的实施例提供了一种半导体器件,包括:模塑料,密封第一集成电路管芯和第二集成电路管芯;介电层,位于所述模塑料、所述第一集成电路管芯和所述第二集成电路管芯上方;以及金属化图案,位于所述介电层上方并且将所述第一集成电路管芯电连接到所述第二集成电路管芯,其中,所述金属化图案包括多条导线,并且其中,所述多条导线中的每条导线:从所述金属化图案的第一区域穿过所述金属化图案的第二区域连续延伸至所述金属化图案的第三区域;以及在所述金属化图案的第二区域中具有相同类型的制造异常。
本发明的另一实施例提供了一种形成半导体器件的方法,包括:将第一集成电路管芯和第二集成电路管芯密封在模塑料中;在所述第一集成电路管芯、所述第二集成电路管芯和所述模塑料上方沉积晶种层;在所述晶种层上方沉积光刻胶;对所述光刻胶的第一图案化区域实施第一曝光工艺以限定第一曝光区域;在实施所述第一曝光工艺后,对所述光刻胶的第二图案化区域实施第二曝光工艺,以限定第二曝光区域,其中,所述第一图案化区域与所述第二图案化区域在拼接区域中重叠;显影所述光刻胶以限定从所述第一图案区域穿过所述拼接区域延伸到所述第二图案区域的第一开口;在所述第一开口中镀导电材料,其中,所述导电材料电连接所述第一集成电路管芯和所述第二集成电路管芯;以及去除所述光刻胶。
本发明的又一实施例提供了一种形成半导体器件的方法,包括:在所述第一管芯、所述第二管芯和所述模塑料上方沉积光刻胶,其中,所述模塑料设置在所述第一管芯和所述第二管芯周围;使用所述第一光掩模掩模版对所述光刻胶的第一图案化区域实施第一曝光工艺;在实施所述第一曝光工艺之后,使用第二光掩模掩模版对所述光刻胶的第二图案化区域实施第二曝光工艺,其中,所述第一图案化区域和所述第二图案化区域在拼接区域中重叠,其中,实施所述第一曝光工艺包括将所述第一光掩模掩模版的第一三角形开口放置在所述拼接区域正上方,并且其中,实施所述第二曝光工艺包括将所述第二光掩模掩模版的第二三角形开口放置在所述拼接区域正上方;显影所述光刻胶以在所述光刻胶中形成第三开口,其中,所述第三开口从所述第一图案区域穿过所述拼接区域延伸到所述第二图案化区域;以及在所述第三开口中电导电材料,其中,所述导电材料将所述第一管芯电连接到所述第二管芯。
附图说明
当结合附图进行阅读时,从以下详细描述可以最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1至图3、图4A、图4B、图5至图10、图11A、图11B、图11C、图12A、图12B和图12C示出了根据各个实施例的制造半导体封装件的中间步骤的变化视图。
图12D示出了根据各个实施例的光刻工艺的曝光强度的曲线图。
图13A、图13B、图13C、图13D、图14A、图14B、图15、图16A、图16B、图16C、图16D、图16E、图16F和图17至图27示出了根据各个实施例的制造半导体封装件的中间步骤的变化视图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同部件的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可以在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
以下将各个实施例描述为针对集成扇出(InFO)光刻工艺。然而,应该理解的是,本文描述的各个实施例方法和所得到的结构可以应用于任何类型的半导体封装件,包括例如衬底上晶圆上芯片(CoWoS)封装件、扇入封装件等。
各个实施例提供用于大型集成芯片封装件的拼接光刻工艺以实现多功能系统。示例性拼接光刻工艺不受光刻步进器的曝光场尺寸的限制。从上到下的角度来看,光刻步进器的场尺寸取决于光学透镜的尺寸。例如,使用单个曝光步骤可实现的光刻胶掩模的所得图案受到光学透镜直径的限制,并且通常进一步受到其在光轴上的放置的限制以减少光学像差。此外,掩模的图案边缘通常与光学透镜的物理边缘间隔开以避免图像失真。这进一步限制了使用单个曝光步骤可实现的图案的尺寸。
对于大的场尺寸集成,所需的图案尺寸通常很大,并且增加光学透镜尺寸来容纳所需的图案尺寸是昂贵的并且可能是不切实际的。示例性拼接光刻工艺采用具有多个光掩模掩模版的多个曝光步骤以限定大的场尺寸集成图案,而不需要增加光学透镜尺寸。例如,使用第一光掩模掩模版将层曝光于该层的第一图案化区域中的第一图案,并且使用第二光掩模掩模版将该层曝光于该层的第二图案化区域中的第二图案。该层的第一和第二图案化区域重叠,这允许第一图案和第二图案互连并且限定整体期望的图案,该图案拼接在一起并且延伸贯穿第一和第二图案化区域。第一和第二图案化区域重叠的区域可以称为拼接区域。在拼接区域(例如,称为灰色调图案)内的每个曝光步骤期间的图案的形状(例如,三角形)可以适于减少由例如对拼接区域实施的多个曝光步骤引起的过曝光导致的图案化缺陷。
此外,实施例可以使用低数值孔径(NA)步进器来减少拼接误差,因为与高NA步进器相比,与低NA步进器相关的景深(DoF)相对较大。低NA步进器可以用于大临界尺寸(CD)应用,并且与高NA步进器相比,还具有减小的成本的额外优势。
通过使用拼接光刻,场集成尺寸不再受曝光场尺寸(例如,每个光学透镜的尺寸)的限制。例如,可以通过在不同的拼接区域内拼接掩模的不同图案来扩大层中的图案的尺寸。进一步使用灰色调图案和低NA步进器可以增加拼接区域的公差并且减少拼接区域处的制造缺陷。
各个实施例可以实现以下一个或多个非限制性优势/特征:通过在拼接区域处的互连件跨越拼接区域的位置拼接不同的掩模图案来实现半导体封装件的大的场尺寸;如果先前工艺的对准标记放置在场的外部,则沿一个方向扩大封装尺寸;如果对准标记放置在场的内部,则无边界的扩大封装件的尺寸;灰色调图案和低NA步进器控制拼接区域处的互连件的临界尺寸(CD)具有更高的容差;更低的花费;以及高良率。
图1至图27示出了根据一些实施例的用于形成第一封装结构的工艺期间的中间步骤的截面图(例如,以形成InFO封装件的组件)。图1示出了载体衬底100和形成在载体衬底100上的释放层102。分别示出了用于形成第一封装件和第二封装件的第一封装区域100A和第二封装区域100B。
载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆,从而使得可以同时在载体衬底100上形成多个封装件。释放层102可以由基于聚合物的材料形成,其可以与将在后续步骤中形成的上面的结构一起从载体衬底100去除。在一些实施例中,释放层102是基于环氧树脂的热释放材料,其在加热时失去其粘合性,诸如光-热-转换(LTHC)释放涂层。在其他实施例中,释放层102可以是紫外(UV)胶,当曝光于UV光时其失去其粘合性。释放层102可以作为液体分配并且固化,可以是层压到载体衬底100上的层压膜等。释放层102的顶面可以是水平的并且可以具有高度的平面度。
在图2中,形成介电层104和金属化图案106。如图2所示,介电层104形成在释放层102上。介电层104的底面可以与释放层102的顶面接触。在一些实施例中,介电层104由聚合物形成,诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等。在其他实施例中,介电层104由诸如氮化硅的氮化物;诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等的氧化物;等形成。介电层104可以通过任何可接受的沉积工艺形成,诸如旋涂、化学汽相沉积(CVD)、层压等,或它们的组合。
金属化图案106形成在介电层104上。作为形成金属化图案106的实例,在介电层104上方形成晶种层(未示出)。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案106。可以将一个或多个曝光步骤应用于光刻胶以限定金属化图案106。在一个或多个曝光之后,显影光刻胶以形成穿过光刻胶的开口以曝光晶种层。可以采用示例性拼接光刻工艺(例如,如关于图10至图16F所讨论的)来限定金属化图案106。可选地,可以使用多个曝光步骤来限定金属化图案106,其中,每个曝光步骤限定例如任何拼接区域处的不互连的单独图案。
在光刻胶的开口中和晶种层的曝光部分上形成导电材料。导电材料可以通过镀形成,诸如电镀或化学镀等。导电材料可以包括金属,如铜、钛、钨、铝等。然后,去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,就去除晶种层的曝光部分,诸如通过使用可接受的蚀刻工艺,诸如通过湿或干蚀刻。晶种层的剩余部分和导电材料形成金属化图案106。
在图3中,在金属化图案106和介电层104上形成可选的介电层108。在一些实施例中,介电层108由与介电层106类似的材料并且使用与介电层106类似的方法形成。然后图案化介电层108以形成开口以曝光金属化图案106的部分。可以通过可接受的工艺图案化,诸如通过在介电层是光敏材料时将介电层108暴露于光,或者通过使用例如各向异性蚀刻的蚀刻。
介电层104和108以及金属化图案106可以被称为背侧再分布结构110。如图所示,背侧再分布结构110包括两个介电层104和108以及一个金属化图案106。在其他实施例中,背侧再分布结构110可以包括任何数量的介电层、金属化图案和通孔。通过重复用于形成金属化图案106和介电层108的工艺,可以在背侧再分布结构110中形成一个或多个额外的金属化图案和介电层。通过在下面的介电层的开口中形成金属化图案的晶种层和导电材料,可以在形成金属化图案期间形成通孔。因此通孔可以互连并且电耦合各个金属化图案。在其他实施例中,可以完全省略背侧再分布结构110,从而使得随后描述的部件直接形成在释放层102上。
此外在图3中,形成通孔112。作为形成通孔112的实例,在背侧再分布结构110(例如介电层108和金属化图案106的暴露部分)上方形成可选的晶种层。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成,并且可以暴露于光以用于图案化。光刻胶的图案对应于通孔112。可以将一个或多个曝光步骤应用于光刻胶以限定通孔112。在一个或多个曝光之后,显影光刻胶以形成穿过光刻胶的开口以暴露晶种层。
在光刻胶的开口中和晶种层的曝光部分上形成导电材料。导电材料可以通过镀形成,诸如电镀或化学镀等。导电材料可以包括金属,如铜、钛、钨、铝等。去除光刻胶和其上未形成导电材料的晶种层部分。可以通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,则去除晶种层的曝光部分,诸如通过使用可接受的蚀刻工艺,诸如通过湿或干蚀刻。晶种层的剩余部分和导电材料形成通孔112。可选地,在省略介电层108的实施例中(见例如图4B),也可以省略晶种层,并且金属化图案106可以用作晶种层以镀通孔112。例如,在这样的实施例中,通孔112可以直接镀在金属化图案106上。
在图4A中,集成电路管芯114通过粘合剂116粘合至介电层108。如图4A所示,两个集成电路管芯114粘合在第一封装区域100A和第二封装区域100B中的每个中,并且在其他实施例中,可以在每个区域中粘合更多或更少的集成电路管芯114。例如,在实施例中,可以在每个区域中仅粘合一个集成电路管芯114,或者可以在每个区域中粘合三个或更多集成电路管芯114。集成电路管芯114可以是逻辑管芯(例如,中央处理单元、微控制器等)、存储器管芯(例如,动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如,电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如,数字信号处理(DSP)管芯)、前端管芯(例如,模拟前端(AFE)管芯)等,或它们的组合。而且,在一些实施例中,集成电路管芯114可以是不同的尺寸(例如,不同的高度和/或表面区域),并且在其他实施例中,集成电路管芯114可以是相同的尺寸(例如,相同的高度和/或表面区域)。
在粘合到载体100之前,可以根据适用的制造工艺处理集成电路管芯114,以在集成电路管芯114中形成集成电路。例如,每个集成电路管芯114包括半导体衬底118,诸如掺杂或未掺杂的硅或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其他半导体材料,诸如锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。也可以使用其他衬底,诸如多层或梯度衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底118中和/或上,并且可以通过互连结构120互连,互连结构120通过例如半导体衬底118上的一个或多个介电层中的金属化图案形成,以形成集成电路。
集成电路管芯114还包括焊盘122,诸如铝焊盘,以制成外部连接。焊盘122位于可称为集成电路管芯114的相应有源侧的位置上。钝化膜124位于集成电路管芯114上和焊盘122的部分上。开口穿过钝化膜124到达焊盘122。诸如导电柱(例如,包括诸如铜的金属)的管芯连接件126延伸穿过钝化膜124并且机械地和电耦合到相应的焊盘122。管芯连接件126可以通过例如镀等形成。管芯连接件126电耦合集成电路管芯114的相应集成电路。
介电材料128位于集成电路管芯114的有源侧上,诸如钝化膜124和管芯连接件126上。介电材料128横向密封管芯连接件126,并且介电材料128与相应的集成电路管芯114横向共末端。介电材料128可以是聚合物,诸如PBO、聚酰亚胺、BCB等;氮化物,诸如氮化硅等;氧化物,诸如氧化硅、PSG、BSG、BPSG等;等,或它们的组合,并且可以例如通过旋涂、层压、CVD等形成。
粘合剂116位于集成电路管芯114的背侧上,并且将集成电路管芯114粘合到背侧再分布结构110,诸如图4A中的介电层108。可选地,在省略介电层108的实施例中,粘合剂116可以将集成电路管芯粘合到金属化图案106和介电层104,诸如图4B所示。在这样的实施例中,粘合剂116可以沿着金属化图案106的顶面和侧壁延伸。粘合剂116可以是任何合适的粘合剂、环氧树脂、管芯附接膜(DAF)等。粘合剂116可以施加到集成电路管芯114的背侧,诸如施加到相应半导体晶圆的背侧,或可以施加在载体衬底100的表面上方。集成电路管芯114可以诸如通过锯切或切割来分割,并且使用例如拾取和放置工具通过粘合剂116粘合到背侧再分布结构110。
在图5中,在各个组件上形成密封剂130。密封剂130可以是模塑料、环氧树脂等,并且可以通过压缩模塑、传递模塑等施加。在固化之后,密封剂130可以经历研磨工艺以暴露通孔112和管芯连接件126。在研磨工艺之后,通孔112、管芯连接件126和密封剂130的顶面共面。在一些实施例中,例如,如果通孔112和管芯连接件126已经暴露,则可以省略研磨。
在图6至图21中,形成前侧再分布结构160。如图21中所示,前侧再分布结构160包括介电层132、140、148和156以及金属化图案138、146和154。
在图6中,在密封剂130、通孔112和管芯连接件126上沉积介电层132。在一些实施例中,介电层132由聚合物形成,该聚合物可以是光敏材料,诸如PBO、聚酰亚胺、BCB等,其可以使用光刻掩模图案化。在其他实施例中,介电层132由氮化物,诸如氮化硅;氧化物,诸如氧化硅、PSG、BSG、BPSG;等形成。介电层132可以通过旋涂、层压、CVD等或它们的组合形成。
在图7至图9中,然后图案化介电层132。图案化形成开口以暴露通孔112和管芯连接件126的部分。当介电层132是光敏材料时,可以使用光刻工艺实现图案化。
用于图案化介电层132的示例性光刻工艺可以包括在载体衬底100上方的每个封装区域(例如,第一封装区域100A和第二封装区域100B)中实施多个曝光步骤。例如,在图7中,第一封装区域100A被分成第一图案化区域200A和第二图案化区域200B。第一图案化区域200A在拼接区域200C中与第二图案化区域200B重叠。
在图7中,使用第一光掩模掩模版202A对第一图案化区域200A中的介电层132实施第一曝光。由此形成介电层132的曝光区域132A。光掩模掩模版202A的尺寸可以对应于NA步进器用于曝光第一图案化区域200A中的介电层132的透镜的尺寸(例如,直径)。例如,在俯视图(未示出)中,光掩模掩模版202A可具有约52mm的长度和约34mm的宽度,以对应于用于曝光介电层132的光学透镜。光掩模掩模版202A的其他尺寸也是可能的。此外,低NA步进器(例如,具有小于0.2的NA)可用于增加图案化工艺的DoF并且减小成本。由于增加的DoF,可以有利地减少由各个部件的翘曲引起的图案化缺陷。因为封装晶圆相对较大,所以它可能特别容易翘曲,这增加了介电层132的顶面处的形貌。通过提供增加的DoF,可以减少由翘曲和增加的形貌引起的图案化缺陷。由于再分布结构160(见图21)中的图案化部件的相对大的部件尺寸(例如,临界尺寸),可以在各个实施例中使用低NA步进器。
下一步,在图8中,使用第二光掩模掩模版202B对第二图案化区域200B中的介电层132实施第二曝光。由此形成介电层132的曝光区域132B。光掩模掩模版202B的尺寸可以对应于NA步进器用于曝光图案化区域200B中的介电层132的透镜的尺寸(例如,直径)。例如,在俯视图(未示出)中,光掩模掩模版202B可具有约52mm的长度和约34mm的宽度,以对应于用于曝光介电层132的光学透镜。光掩模掩模版202B的其他尺寸也是可能的。此外,低NA步进器(例如,具有小于0.2的NA)可用于增加图案化工艺的DoF并且减小成本。由于增加的DoF,可以减少由介电层132的翘曲和增加的形貌引起的图案化缺陷。由于再分布结构160(见图21)中的图案化部件的相对大的部件尺寸(例如,临界尺寸),可以在各个实施例中使用低NA步进器。
以这种方式,在第一封装区域100A中限定用于穿过介电层132的开口的图案。第一封装区域100A中的开口的图案的整体尺寸不必限于用于曝光介电层132的光学透镜的物理尺寸,因为多个曝光步骤和光掩模掩模版可以扩展形成在每个封装区域100A和100B中的封装件的尺寸。
可以对载体衬底100上方的其他封装区域(例如,在第二封装区域100B)实施类似的曝光步骤,以在介电层132中限定期望的图案。可以在完成第一封装区域100A中的所有曝光步骤之后实施曝光第二封装区域100B。可选地,在随后的光掩模掩模版(例如,第二光掩模掩模版202B)用于曝光介电层132之前,每个光掩模掩模版(例如,第一光掩模掩模版202A)可用于曝光载体衬底100B上方的每个封装区域。
在图9中,在曝光介电层132的各个图案化区域和封装区域之后,显影介电层132以形成延伸穿过介电层132的开口。开口可以曝光通孔112和管芯连接件126的部分。图9示出了作为正光刻胶材料的介电层132,其中由于介电层132被显影而去除曝光区域132A/132B。在其他实施例中,介电层132可以是负性光刻胶,其中介电层132的曝光区域132A/132B保留,而介电层132的未曝光区域由于显影而被去除。
在图10至图16F中,在介电层132上形成具有通孔的金属化图案138。作为形成金属化图案138的实例,在介电层132上方和穿过介电层132的开口中形成晶种层133。在一些实施例中,晶种层133是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层133包括钛层和钛层上的铜层。晶种层133可以使用例如PVD等形成。
然后在晶种层133上形成并且图案化光刻胶204。光刻胶204可以通过旋涂等形成,并且可以暴露于光以用于图案化。如下所述的多个曝光工艺(例如,拼接光刻)将用于曝光光刻胶的多个区域。在多个曝光工艺之后,将实施单个显影工艺以根据使用的是负性还是正性光刻胶来去除光刻胶的曝光或未曝光部分。
在图11A中,使用第一光掩模掩模版206A对第一图案化区域200A中的光刻胶204实施第一曝光。由此形成光刻胶204的曝光区域204A。光掩模掩模版202A的尺寸可以对应于NA步进器用于曝光第一图案化区域200A中的光刻胶204的透镜的尺寸(例如,直径)。例如,在俯视图(未示出)中,光掩模掩模版206A可以具有约52mm的长度和约34mm的宽度,以对应于用于曝光光刻胶204的光学透镜。光掩模掩模版206A的其他尺寸也是可能的。此外,低NA步进器(例如,具有小于0.2的NA)可用于增加图案化工艺的DoF并且减小成本。由于增加的DoF,可以减少由介电层132的翘曲和增加的形貌引起的图案化缺陷。由于再分布结构160(见图21)中的图案化部件的相对大的部件尺寸(例如,临界尺寸),可以在各个实施例中使用低NA步进器。
曝光区域204A延伸到拼接区域200C中(例如,第一图案化区域200A和第二图案化区域200B重叠的位置)。与拼接区域200C外部的第一图案化区域200A的区域相比,光掩模掩模版206A可以被设计为减少施加到拼接区域200C中的光刻胶204的曝光剂量。例如,在曝光步骤期间,光(例如,紫外(UV)光)通过光掩模掩模版206A投射到光刻胶204上。光掩模掩模版206A中的开口允许光照射到光掩模204上,而光掩模掩模版206A的实心区域阻挡光照射到光掩模204上。与拼接区域200C外部的第一图案化区域200A的区域相比,光掩模掩模版206A中的开口的形状和尺寸可以减小拼接区域200C中的光的透射率。例如,光掩模掩模版206A可以允许拼接区域200C外部的第一图案化区域200A中的光的透射率为100%,而光掩模掩模版206A可以允许拼接区域200C中的光的透射率在朝向第二图案化区域200B的方向上从100%逐渐减小至约0%。这可以通过选择拼接区域200C上方的光掩模掩模版206A的开口的适当形状并且减小拼接区域200C上方的光掩模掩模版206A中的开口的面积来实现。
图11B和图11C示出了根据各个实施例的拼接区域200C外部和内部的第一图案化区域200A中的曝光区域204A的俯视图。曝光区域204A的形状对应于光掩模掩模版206A中的开口的形状。如图11B和图11C所示,曝光区域204A的宽度随着曝光区域204A延伸到拼接区域200C中而减小,从而使得曝光区域204A在拼接区域200C中具有三角形形状。曝光区域204A的三角形形状可以跨越整个拼接区域200C。例如,三角形形状可以在拼接区域200C的第一边缘处开始并且在拼接区域200C的第二边缘处变窄到顶点,第二边缘与第一边缘相对。在拼接区域200C中,曝光区域204A的宽度可以恒定地减小(例如,如图11B所示)或者以设定的间隔离散地减小(例如,如图11C所示)。
由于曝光区域204A的示例性形状和变化的宽度,曝光区域204A的曝光强度随着曝光区域204A延伸到拼接区域200C中而减小。通过将曝光区域204A配置成在拼接区域200C中具有图示的形状(例如,通过在拼接区域200C上方的光掩模掩模版206A中配置相应的开口),拼接区域200C内的曝光强度也可以逐渐减小,这减少了过曝光缺陷并且增加了重叠容差,如下面将详细描述的。
下一步,在图12A中,使用第二光掩模掩模版206B对第二图案化区域200B中的光刻胶204实施第二曝光。由此形成光刻胶204的曝光区域204B。光掩模掩模版202B的尺寸可以对应于NA步进器用于曝光第一图案化区域200A中的光刻胶204的透镜的尺寸(例如,直径)。例如,在俯视图(未示出)中,光掩模掩模版206B可具有约52mm的长度和约34mm的宽度,以对应于用于曝光光刻胶204的光学透镜。光掩模掩模版206B的其他尺寸也是可能的。此外,低NA步进器(例如,具有小于0.2的NA)可用于增加图案化工艺的DoF并且减小成本。由于增加的DoF,可以减少由介电层132的翘曲和增加的形貌引起的图案化缺陷。由于再分布结构160(见图21)中的图案化部件的相对大的部件尺寸(例如,临界尺寸),可以在各个实施例中使用低NA步进器。
曝光区域204B延伸到拼接区域200C中(例如,第一图案化区域200A和第二图案化区域200B重叠的位置)。曝光区域204B可以与拼接区域200C中的曝光区域204A重叠,从而使得光刻胶204包括从第一图案化区域200A(具体地,拼接区域200C外部的第一图案化区域200A的区域)通过拼接区域200C连续延伸至第二图案化区域200B(具体地,拼接区域200C外部的第二图案化区域200B的区域)的拼接的曝光区域。
类似于第一图案化区域200A,与在拼接区域200C外部的第二图案化区域200B的区域相比,光掩模掩模版206B可以被设计为减少施加到拼接区域200C中的光刻胶204的曝光剂量。与拼接区域200C外部的第二图案化区域200B的区域相比,光掩模掩模版206B中的开口的形状和尺寸可以减小拼接区域200C中的光的透射率。例如,光掩模掩模版206B可以允许拼接区域200C外部的第二图案化区域200B中的光的透射率为100%,而光掩模掩模版206B可以允许拼接区域200C中的光的透射率在朝向第一图案化区域200A的方向上从100%逐渐减小至约0%。这可以通过选择拼接区域200C上方的光掩模掩模版206B的开口的适当形状并且减小拼接区域200C上方的光掩模掩模版206B中的开口的面积来实现。
图12B和图12C示出了根据各个实施例的第一图案化区域200A中的曝光区域204A和第二图案化区域200B中的曝光区域204B的俯视图。曝光区域204B的形状对应于光掩模掩模版206B中的开口的形状。如图12B和图12C所示,曝光区域204B的宽度随着曝光区域204B延伸到拼接区域200C中减小,从而使得曝光区域204B在拼接区域200C中具有三角形形状。曝光区域204B的三角形形状可以跨越整个拼接区域200C。例如,三角形形状可以在拼接区域200C的第二边缘处开始并且在拼接边缘200C的第一边缘处变窄到顶点。在拼接区域200C中,曝光区域204B的宽度可以恒定地减小(例如,如图12B所示)或者以设定的间隔离散地减小(例如,如图12C所示)。
由于曝光区域204B的示例性形状和变化的宽度,曝光区域204B的曝光强度随着曝光区域204B延伸到拼接区域200C中而减小。通过将曝光区域204B配置成在拼接区域200C(例如,通过在拼接区域200C上方的光掩模掩模版206B中配置相应的开口)中具有图示的形状,拼接区域200C内的曝光区域204B的曝光强度也可以逐渐减小,这减少了过曝光缺陷并且增加了重叠容差。
曝光区域204A和204B在重叠区域208处重叠。当在拼接区域200C中曝光强度没有减小时,重叠区域208可能过曝光(例如,具有约200%的曝光强度)。通过逐渐减小拼接区域200C中的曝光区域204A和204B的曝光强度,因为减小了由第一曝光(例如,限定曝光区域204A)和第二曝光(例如,限定曝光区域204B)产生的重叠区域208的累积曝光强度,所以减少了过曝光重叠区域208的风险。例如,图12D示出了整个第一图案化区域200A和第二图案化区域200B中的曝光区域204A和204B的曝光强度。在图12D中,x轴表示位置,并且y轴表示曝光强度。曲线210A对应于曝光区域204A的曝光强度,曲线210B对应于曝光区域204B的曝光强度。拼接区域200C中的曲线210A和210B的斜率可以对应于跨越拼接区域200C的距离并且由该距离确定,该距离确定每个曝光区域204A/204B的三角形形状的长度。可以通过添加曲线210A和210B的对应强度来获得光刻胶204的任何给定位置的累积曝光强度。从图12D中可以看出,第一图案化区域200A和第二图案化区域200B中的任何给定位置处的累积曝光强度在约1(例如,100%)和约1.2(例如,120%)的范围内。具体地,在拼接区域200C中的累积曝光强度(实施了两个曝光步骤)与拼接区域200C外部的累积曝光强度(只实施了一个曝光步骤)基本相同。通过减少过曝光,还可以减少由过曝光引起的缺陷(例如,限定过大的部件)。
此外,拼接区域200C中的曝光区域204A和204B的三角形形状也可以增加重叠容差。图13A、图13B、图13C和图13D示出了示例性重叠误差,其可以由光掩模掩模版206A和光掩模掩模版206B之间的对准误差引起。图13A示出了其中光掩模掩模版206B在朝向第一图案化区域200A的方向上横向移动,如箭头209A所示的实施例。因此,曝光区域204B可以延伸到拼接区域200C外部的第一图案化区域200A的区域中。图13B示出了其中光掩模掩模版206B在朝向第二图案化区域200B的方向上横向移动,如箭头209B所示的实施例。因此,曝光区域204B没有延伸完全横跨拼接区域200C。图13C和图13D示出了其中光掩模掩模版206B垂直移位从而使得曝光区域204A和204B的边缘不再对准,如箭头209C和209D所示的实施例。虽然图13A、图13B、图13C和图13D中的每个示出了单个重叠误差,但是应该理解,这些误差也可以组合在一起。已经观察到,通过提供具有三角形形状的曝光区域204A和204B,允许在任何方向上高达10%的重叠误差,同时仍然在制造公差内。
拼接区域200C中的曝光区域204A和204B的三角形形状允许曝光强度的线性变化,从而使得任何偏移都不会显着影响累积曝光强度。例如,在图13A中,在拼接区域200C外部的第一图案化区域200A中的曝光区域204B的部分可以具有相对低的曝光强度(例如,小于约20%)。因此,虽然重叠区域200C外部的第一图案化区域200A中的曝光区域204A被完全曝光(例如,曝光强度为约100%),但是曝光区域204A和204B的累积曝光强度保持在120%左右,即使图13A所示的重叠误差也在制造公差内。作为另一实例,在图13B中,曝光区域204B不延伸到拼接区域200C的区域200D中。例如,在区域200D中,仅实施一个曝光(即,对应于曝光区域204A的曝光)。然而,因为曝光区域204A在区域200D中具有几乎完全的曝光强度(例如,至少80%),所以来自第二曝光步骤的曝光不足不会导致不可接受的曝光不足区域。例如,在区域200D中,曝光区域204A和204B的累积曝光强度保持在80%左右,即使图13B所示的重叠误差也在制造公差内。
因此,使用多个光掩模掩模版206A/206B曝光光刻胶214,以使图案的尺寸延伸为横跨拼接区域。尽管上面仅描述了两个曝光步骤,但是应该理解,可以对光刻胶214应用任何数量的曝光步骤。例如,如果需要更大的区域,则可以应用额外的曝光步骤。每个附加曝光步骤可以与额外的拼接区域中的先前曝光步骤重叠。例如,图14A和图14B示出了多个拼接区域。不同的光掩模掩模版206A、206B、206D和206F用于分别在晶圆的不同图案化区域200A、200B、200D和200F中限定图案。图案化区域200A和200B在拼接区域200C中重叠;图案化区域200A和200D在拼接线200E中重叠;图案化区域200B和200F在拼接区域200G中重叠;并且图案化区域200D和200F在拼接区域200H中重叠。曝光区域204A和204B延伸穿过拼接区域200C;曝光区域204A和204D延伸穿过拼接区域200E;曝光区域204B和204F延伸穿过拼接区域200G;曝光区域204D和204F延伸穿过拼接区域200H。对准标记302用于使光掩模掩模版206A、206B、206D和206F与下层的图案(例如,介电层132的图案,见图10)对准。重叠标记304用于将光掩模掩模版206A、206B、206D和206F的图案与其他光掩模掩模版206A、206B、206D和206F对准。例如,重叠标记304A可用于对准光掩模掩模版206A和206B;重叠标记304B可用于对准光掩模掩模版206B和206F;并且重叠标记304C可以用于对准光掩模掩模版206A和206D。对准标记302和304可以重叠以减小用于准标记所需的面积。当对准标记302和304放置在图案化区域(例如,200A、200B等)外部时,图案的尺寸可以在一个方向(例如,如图14A中的箭头306所示)上延伸。当对准标记302和304放置在图案化区域(例如,200A、200B等)内部时,图案的尺寸可以在多个方向(例如,如图14B中的箭头308所示)上延伸。此外,由于使用多个光掩模掩模版将层的图案拼接在一起,对准标记302和重叠标记304可以在图案周围(例如,如图14A所示)或在整个图案(例如,如图14B所示)上以规则间隔设置。相邻对准标记302/重叠标记304之间的间隔可以对应于光掩模掩模版的尺寸。
因此,通过提供多个曝光步骤,可以通过使用多个光掩模掩模版来图案化较大的晶圆,以在拼接区域中限定重叠图案。可以使用具有高DoF的低NA光刻工具来施加多个曝光步骤,这允许即使在翘曲的情况下也限定图案。重叠图案的形状可以是三角形,以减小拼接区域中的曝光强度。通过减小曝光强度,可以改进制造公差并且可以减少缺陷。可选地,可以采用其他形状来减少拼接区域中的曝光强度以适应多个曝光步骤。
可以对载体衬底100上方的其他封装区域(例如,在第二封装区域100B)实施类似的曝光步骤,以在光刻胶204中限定期望的图案。可以在完成第一封装区域100A中的所有曝光步骤之后实施曝光第二封装区域100B。可选地,在随后的光掩模掩模版(例如,第二光掩模掩模版206B)用于曝光光刻胶204之前,每个光掩模掩模版(例如,第一光掩模掩模版206A)可用于曝光载体衬底100B上方的每个封装区域。
在图15中,在光刻胶204的各个图案化区域和封装区域被曝光之后,显影光刻胶204以形成延伸穿过光刻胶204的开口212。图15示出了作为正光刻胶材料的光刻胶204,其中曝光区域204A/204B由于显影光刻胶204而被去除。在其他实施例中,光刻胶204可以是负性光刻胶,其中光刻胶204的曝光区域204A/204B保留,而光刻胶204的未曝光区域由于显影而被去除。
随后,在图16A中,通过镀,诸如电镀或化学镀等,在开口212中形成导电材料。导电材料可以包括金属,如铜、钛、钨、铝等。然后,去除光刻胶204和其上未形成导电材料的晶种层133的部分。可以通过可接受的灰化或剥离工艺去除光刻胶204,诸如使用氧等离子体等。一旦去除光刻胶204,则去除晶种层133的曝光部分,诸如通过使用可接受的蚀刻工艺,诸如通过湿或干蚀刻。晶种层的剩余部分和导电材料形成金属化图案138和通孔。通孔形成在穿过介电层132至例如通孔112和/或管芯连接件126的开口中。
图16A示出了金属化图案138的截面图。图16B、图16C、图16D、图16E和图16F示出了区域100C中的金属化图案138的俯视图(见图16A)。区域100C包括第一图案化区域200A、第二图案化区域200B和拼接区域200C的部分。金属化图案138的位置可以进一步对应于图14A和图14B所示的曝光区域204A/204B/204D/204F。例如,金属化图案138可以包括设置在相邻对准标记302/重叠标记304之间的导线。
在图16B中,形成金属化图案138A、138B和138C而没有制造异常以限定导电再分布线,其从图案化区域200A通过拼接区域200C连续延伸至图案化区域200B。在图16C、图16D、图16E和图16F中,金属化图案138A、138B和138C形成有制造异常以限定导电再分布线,其从图案化区域200A通过拼接区域200C延伸到图案化区域200B。因为制造异常是由于光掩模掩模版(例如,206A和206B)之间的重叠误差引起的,所以金属化图案138A、138B和138C中的每个可以在拼接区域200C内具有相同类型的制造异常。在图16C中,拼接区域200C发生移位误差,其限定了制造异常,其中金属化图案138A/138B/138C的侧壁不再对准。在图16D中,在拼接区域200C中的每个金属化图案138A、138B和138C中存在间隙。例如,当金属化图案138A、138B和138C限定伪图案时,该间隙可以是可接受的。每个金属化图案138A、138B和138C中的间隙的尺寸可以相同。在图16E中,拼接区域200C中的每个金属化图案138A、138B和138C具有较窄的区域(例如,称为颈缩)。拼接区域200C的每个金属化图案138A、138B和138C变窄的量可以是相同的。图16D和图16E所示的制造异常可能是由于拼接区域200C中的曝光不足(例如,如上关于图13B所述)引起的。在图16F中,拼接区域200C中的每个金属化图案138A、138B和138C具有更宽的区域(例如,称为凸出)。拼接区域200C中的每个金属化图案138A、138B和138C变宽的量可以相同。图16F所示的制造异常可能是由于拼接区域200C中的过曝光(例如,如上关于图13A所述)引起的。其他制造异常也是可能的,但是通常由于上述实施方式的图案化方法,异常在制造公差内。在各个实施例中,拼接区域(例如,拼接区域200C)中的每个金属化图案可以具有相同类型的制造异常,因为这些异常是由多个曝光步骤引起的重叠误差引起的,并且相同的重叠误差将应用于整个拼接区域200C。通常,制造异常可以被检测为在光掩模或布局文件中限定的导电部件的预期图案和制造的导电部件的物理图案之间的形状差异。在各个实施例中,单个拼接区域内的制造异常可以包括不均匀的导线、在每个导线内具有非线性边缘的导线、在每个导线内具有变化宽度的导线等。
在图17中,在金属化图案138和介电层132上沉积介电层140。介电层140可以由与介电层132类似的材料制成,并且使用与介电层132类似的工艺沉积。在沉积介电层140之后,可以将其图案化以形成暴露金属化图案138的部分的开口。介电层140的图案化可以通过可接受的工艺,诸如与上述关于图案化介电层132的多个曝光图案化工艺类似的工艺。
在图18中,在介电层140上形成具有通孔的金属化图案146。金属化图案146可以由与金属化图案138类似的材料制成,并且使用与金属化图案138类似的工艺形成。例如,可以沉积晶种层,可以在晶种层上沉积光刻胶,可以将如上所述的多个曝光光刻工艺应用于光刻胶以限定暴露晶种层的开口,可以实施镀工艺以将导电材料镀在晶种层的暴露部分上,并且去除光刻胶和其上未形成导电材料的晶种层的部分。晶种层的剩余部分和导电材料形成金属化图案146和通孔。通孔形成在穿过介电层140至例如金属化图案138的部分的开口中。
在图19中,在金属化图案146和介电层140上沉积介电层148。介电层148可以由与介电层132类似的材料制成,并且使用与介电层132类似的工艺沉积。在沉积介电层148之后,可以将其图案化以形成暴露金属化图案146的部分的开口。介电层148的图案化可以通过可接受的工艺,诸如与上述关于图案化介电层132的多个曝光图案化工艺类似的工艺。
在图20中,在介电层148上形成具有通孔的金属化图案154。金属化图案154可以由与金属化图案138类似的材料制成,并且使用与金属化图案138类似的工艺形成。例如,可以沉积晶种层,可以在晶种层上沉积光刻胶,可以将如上所述的多个曝光光刻工艺应用于光刻胶以限定暴露晶种层的开口,可以实施镀工艺以将导电材料镀在晶种层的暴露部分上,并且去除光刻胶和其上没有形成导电材料的晶种层的部分。晶种层的剩余部分和导电材料形成金属化图案154和通孔。通孔形成在穿过介电层148至例如金属化图案146的部分的开口中。
在图21中,在金属化图案154和介电层148上沉积介电层156。介电层156可以由与介电层132类似的材料制成,并且使用与介电层132类似的工艺沉积。在沉积介电层156之后,可以将其图案化以形成暴露金属化图案154的部分的开口。介电层156的图案化可以通过可接受的工艺,诸如与上述关于图案化介电层132的多个曝光图案化工艺类似的工艺。
前侧再分布结构160示出为实例。可以在前侧再分布结构160中形成更多或更少的介电层和金属化图案。如果要形成更少的介电层和金属化图案,则可以省略上面讨论的步骤和工艺。如果要形成更多的介电层和金属化图案,则可以重复上面讨论的步骤和工艺。本领域普通技术人员将容易理解将省略或重复哪些步骤和工艺。
虽然参考前侧再分布结构160讨论了本文描述的RDL布线设计,但是RDL布线工艺的教导也可以应用于背侧再分布结构110。
在图22中,焊盘162形成在前侧再分布结构160的外侧上。焊盘162用于耦合到导电连接件166(见图23),并且可以称为凸块下金属(UBM)162。在所示实施例中,焊盘162穿过穿过介电层156至金属化图案154的开口形成。焊盘162可以由与金属化图案138类似的材料制成,并且使用与金属化图案138类似的工艺形成。例如,可以沉积晶种层,可以在晶种层上沉积光刻胶,可以将如上所述的多个曝光光刻工艺应用于光刻胶以限定暴露晶种层的开口,可以实施镀工艺以将导电材料镀在晶种层的暴露部分上,并且去除光刻胶和其上没有形成导电材料的晶种层的部分。晶种层的剩余部分和导电材料形成焊盘162。
在图23中,导电连接件166形成在焊盘162上。导电连接件166可以是BGA连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯-浸金技术(ENEPIG)形成的凸块等。导电连接件166可以包括导电材料,诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中,导电连接件166通过首先通过诸如蒸发、电镀、印刷、焊料转移、球放置等常用方法形成焊料层而形成。一旦在结构上形成了焊料层,则可以实施回流以将材料成形为期望的凸块形状。在另一实施例中,导电连接件166是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中,金属覆盖层(未示出)形成在金属柱连接件166的顶部上。金属覆盖层可以包括镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合,并且可以通过镀工艺形成。
在图24中,实施载体衬底脱粘以使载体衬底100与背侧再分布结构例如介电层104分离(脱粘)。根据一些实施例,脱粘包括在释放层102上投射诸如激光或UV光的光,使得释放层102在光的热量下分解,并且可以去除载体衬底100。然后将结构翻转并且放置在带190上方。
如图25中进一步所示,穿过介电层104形成开口以暴露金属化图案106的部分。例如,可以使用激光钻孔、蚀刻等形成开口。
在图26中,通过沿着划线区域,例如在相邻区域100A和100B之间,通过锯切来实施分割工艺。锯切将第二封装区域100B与第一封装区域100A分割。
图26示出了得到的分割的封装件400,其可以来自第一封装区域100A或第二封装区域100B。封装件400还可以称为集成扇出(InFO)封装件200。
图27示出了封装结构570,其包括封装件400(可以称为第一封装件400)、第二封装件500和衬底550。第二封装件500包括衬底502和耦合到衬底502的一个或多个堆叠管芯508(508A和508B)。衬底502可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中,还可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟等化合物材料,以及它们的组合等。可选地,衬底502可以是绝缘体上硅(SOI)衬底。通常,SOI衬底包括半导体材料层,诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合。在一个可选实施例中,衬底502是基于诸如玻璃纤维增强树脂芯的绝缘芯。一种示例性芯材料是玻璃纤维树脂,诸如FR4。芯材料的可选物质包括双马来酰亚胺-三嗪(BT)树脂,或者可选地,其他印刷电路板(PCB)材料或膜。诸如味之素增强膜(ABF)或其他层压板的构建膜可用于衬底502。
衬底502可以包括有源和无源器件。如本领域普通技术人员将意识到,诸如晶体管、电容器、电阻器、这些的组合等的各种器件可用于产生用于半导体封装件500的设计的结构和功能要求。可以使用任何合适的方法形成器件。
衬底502还可以包括金属化层(未示出)和通孔506。金属化层可以形成在有源和无源器件上方,并且设计成连接各种器件以形成功能电路。金属化层可以由电介质(例如低k介电材料)和导电材料(例如,铜)的交替层形成,其中通孔互连导电材料层并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中,衬底502基本上没有有源和无源器件。
衬底502可以在衬底502的第一侧上具有接合焊盘503以耦合到堆叠管芯508,并且在衬底502的第二侧上具有接合焊盘504,衬底502的第二侧与第一侧相对,以耦合到导电连接件514。在一些实施例中,通过在衬底502的第一侧和第二侧上形成至介电层(未示出)中的凹槽(未示出)来形成接合焊盘503和504。可以形成凹槽以允许接合焊盘503和504嵌入介电层中。在其他实施例中,省略凹槽,因为接合焊盘503和504可以形成在介电层上。在一些实施例中,接合焊盘503和504包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层(未示出)。接合焊盘503和504的导电材料可以沉积在薄晶种层上。导电材料可以通过电化学镀工艺、化学镀工艺、CVD、ALD、PVD等或它们的组合形成。在实施例中,接合焊盘503和504的导电材料是铜、钨、铝、银、金等或它们的组合。
在实施例中,接合焊盘503和504是UBM,其包括三个导电材料层,诸如钛层、铜层和镍层。然而,本领域普通技术人员将意识到,存在适合于形成UBM 503和504的许多合适的材料和层的布置,诸如铬/铬铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于UBM 503和504的任何合适的材料或材料层完全旨在包括在本申请的范围内。在一些实施例中,通孔506延伸穿过衬底502并且将至少一个接合焊盘503耦合到至少一个接合焊盘504。
在所示实施例中,堆叠管芯508通过引线接合510耦合到衬底502,但是可以使用其他连接,诸如导电凸块。在实施例中,堆叠管芯508是堆叠的存储器管芯。例如,堆叠的存储器管芯508可以包括低功率(LP)双倍数据速率(DDR)存储器模块,诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等存储器模块。
在一些实施例中,堆叠管芯508和引线接合510可以由模塑材料512密封。模塑材料512可以例如,使用压缩模塑而模塑在堆叠管芯508和引线接合510上。在一些实施例中,模塑材料512是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可以实施固化步骤以固化模塑材料512,其中固化可以是热固化、UV固化等或它们的组合。
在一些实施例中,堆叠管芯508和引线接合510埋在模塑材料512中,并且在模塑材料512的固化之后,实施诸如研磨的平坦化步骤,以去除模塑材料512的多余部分,并且为第二封装件500提供基本平坦的表面。
在形成第二封装件500之后,通过导电连接件514、接合焊盘504和金属化图案106将封装件500接合到第一封装件400。在一些实施例中,堆叠的存储器管芯508可以通过引线接合310、接合焊盘503和504、通孔506、导电连接件514和通孔112耦合到集成电路管芯114。
导电连接件514可以类似于上述导电连接件166,并且此处不再重复描述,但是导电连接件514和166不需要相同。在一些实施例中,在接合导电连接件514之前,导电连接件514涂覆有焊剂(未示出),诸如免清洗焊剂。导电连接件514可以浸入焊剂中,或可以将焊剂喷射到导电连接件514上。在另一实施例中,可以将焊剂施加到金属化图案106的表面。
在一些实施例中,导电连接件514可以具有在其上形成的可选环氧树脂焊剂(未示出),然后回流,在将第二封装件500附接至第一封装件400之后剩余的环氧树脂焊剂的至少一些环氧树脂部分。剩余的环氧树脂部分可以用作底部填充物以减小应力并且保护由导电连接件514的回流产生的接头。在一些实施例中,底部填充物(未示出)可以形成在第二封装件500和第一封装件400之间并且围绕导电连接件514。底部填充物可以在附接第二封装件500之后通过毛细管流动工艺形成,或可以在附接第二封装件500之前通过合适的沉积方法形成。
第二封装件500和第一封装件400之间的接合可以是焊料接合或直接金属至金属(诸如铜至铜或锡至锡)接合。在实施例中,通过回流工艺将第二封装件500接合至第一封装件400。在该回流工艺期间,导电连接件514与接合焊盘504和金属化图案106接触,以将第二封装件500物理和电连接至第一封装件400。在接合工艺之后,IMC(未示出)可以形成在金属化图案106和导电连接件514的界面处并且也形成在导电连接件514和接合焊盘504之间的界面(未示出)处。
虽然在将第一封装件400从晶圆中的其他封装件中分割之后,第二封装件500示出为附接到第一封装件400,但是在其他实施例中,在分割之前,第二封装件500可以附接到第一封装件400。例如,第二封装件500可以附接到第一封装件400,并且然后可以分割第一封装件400(例如,如图26中所描述的)。
半导体封装件570包括安装到封装衬底550的封装件400和500。使用导电连接件166将封装件400安装到封装衬底550。
封装衬底550可以由诸如硅、锗、金刚石等的半导体材料制成。可选地,也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外,封装衬底550可以是SOI衬底。通常,SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中,封装衬底550是基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的可选物质包括双马来酰亚胺-三嗪(BT)树脂或者其他PCB材料或薄膜。对于封装衬底550可以使用诸如ABF或其它层压材料的增强膜。
封装衬底550可以包括有源和无源器件。如本领域普通技术人员将意识到,诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于封装结构500的设计的结构和功能需求。可以使用任何合适的方法形成该器件。
封装衬底550也可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘552。金属化层可以形成在有源和无源器件上方并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如,低k介电材料)和导电材料(例如,铜)(其中,通孔互连导电材料层)的交替层形成,并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中,封装衬底550基本上没有有源和无源器件。
在一些实施例中,可以回流导电连接件166以将第一封装件400附接至接合焊盘552。导电连接件166将包括封装衬底550中的金属化层的封装衬底550电和/或物理连接至第一封装件400。
导电连接件166可以具有形成在其上的可选环氧树脂焊剂(未示出),然后回流,在将第一封装件400附接至封装衬底550之后,剩余环氧树脂焊剂的至少一些环氧树脂部分。该剩余的环氧树脂部分可以用作底部填充物以减小应力并且保护由导电连接件166的回流产生的接头。在一些实施例中,底部填充物(未示出)可以形成在第一封装件400和封装衬底550之间并且围绕导电连接件166。底部填充物可以在附接第一封装件400之后通过毛细管流动工艺形成,或可以在附接第一封装件400之前通过合适的沉积方法形成。
也可以包括其它部件和工艺。例如,可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘,以允许使用探针和/或探针卡等测试3D封装件或3DIC。可以在中间结构以及最终结构上实施验证测试。此外,本文公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合使用以提高良率和降低成本。
各个实施例使用拼接光刻工艺将由横跨不同的图案化区域的不同光掩模掩模版限定的不同图案拼接在一起。通过使用拼接光刻,场集成尺寸不再受曝光场尺寸(例如,每个光学透镜的尺寸)的限制。例如,可以通过在不同的拼接区域内拼接不同图案的掩模来扩大层中图案的尺寸。进一步使用灰色调图案和低NA步进器可以增加拼接区域处的公差并且减少拼接区域处的制造缺陷。
在实施例中,器件包括密封第一集成电路管芯和第二集成电路管芯的模塑料;位于模塑料、第一集成电路管芯和第二集成电路管芯上方的介电层;以及位于介电层上方并且将第一集成电路管芯电连接到第二集成电路管芯的金属化图案,其中,金属化图案包括多条导线,并且其中多条导线中的每条导线:从金属化图案的第一区域穿过金属化图案的第二区域连续延伸至金属化图案的第三区域;并且在金属化图案的第二区域中具有相同类型的制造异常。在实施例中,与金属化图案的第一区域和金属化图案的第三区域相比,金属化图案的第二区域中的多条导线中的每条导线的宽度增加。在实施例中,与金属化图案的第一区域和金属化图案的第三区域相比,金属化图案的第二区域中的多条导线中的每条导线的宽度减小。在实施例中,多个导线中的每条导线的侧壁在金属化图案的第二区域中未对准。在实施例中,金属化图案的第二区域设置在第一对准标记和第二对准标记之间。在实施例中,该器件还包括第三对准标记和第四对准标记,其中金属化图案包括位于第三对准标记和第四对准标记之间的第二多条导线,并且其中第一对准标记和第三对准标记之间的距离等于第二对准标记和第四对准标记之间的距离。在实施例中,金属化图案包括在第一对准标记和第三对准标记之间的第三多条导线。
在实施例中,方法包括将第一集成电路管芯和第二集成电路管芯密封在模塑料中;在第一集成电路管芯、第二集成电路管芯和模塑料上方沉积晶种层;在晶种层上方沉积光刻胶;对光刻胶的第一图案化区域实施第一曝光工艺以限定第一曝光区域;在实施第一曝光工艺后,对光刻胶的第二图案化区域实施第二曝光工艺,以限定第二曝光区域,其中,第一图案化区域与第二图案化区域在拼接区域重叠;显影光刻胶以限定从第一图案区域穿过拼接区域延伸至第二图案区域的第一开口;在第一开口中镀导电材料,其中,导电材料电连接第一集成电路管芯和第二集成电路管芯;以及去除光刻胶。在实施例中,第一曝光区域的形状在拼接区域中是三角形。在实施例中,第二曝光区域的形状在拼接区域中是三角形。在实施例中,实施第一曝光工艺包括减小由拼接区域中的第一曝光工艺施加的曝光强度,其中,由第一曝光工艺施加的曝光强度在朝向第二图案化区域的方向上减小。在实施例中,由第一曝光工艺施加的曝光强度在朝向第二图案化区域的方向上连续减小。在实施例中,由第一曝光工艺施加的曝光强度在朝向第二图案化区域的方向上以离散间隔减小。在实施例中,在整个拼接区域中由第一曝光工艺和第二曝光工艺产生的累积曝光强度不大于120%。在实施例中,第一图案化区域的尺寸对应于在第一曝光工艺期间使用的光掩模掩模版的尺寸。在实施例中,实施第一曝光工艺包括使用具有小于0.2的数值孔径(NA)的光刻步进工具。
在实施例中,方法包括在第一管芯、第二管芯和模塑料上方沉积光刻胶,其中模塑料围绕第一管芯和第二管芯设置;使用第一光掩模掩模版对光刻胶的第一图案化区域实施第一曝光工艺;在实施第一曝光工艺之后,使用第二光掩模掩模版对光刻胶的第二图案化区域实施第二曝光工艺,其中第一图案化区域和第二图案化区域在拼接区域中重叠,其中实施第一曝光工艺包括将第一光掩模掩模版的第一三角形开口直接放置在拼接区域上方,并且其中实施第二曝光工艺包括将第二光掩模掩模版的第二三角形开口放置在拼接区域正上方;显影光刻胶以在光刻胶中形成第三开口,其中第三开口从第一图案区域穿过拼接区域延伸到第二图案化区域;以及在第三开口中镀导电材料,其中,导电材料将第一管芯电连接到第二管芯。在实施例中,实施第一曝光工艺包括:将第一三角形开口的一侧放置在拼接区域的第一边缘处;将第一三角形开口的顶点放置在拼接区域的第二边缘处;将第二三角形开口的一侧放置在拼接区域的第二边缘处;并且将第二三角形开口的顶点放置在拼接区域的第一边缘处。在实施例中,该方法还包括使用第一对准标记将第一光掩模掩模版与光刻胶下面的层对准;并且使用重叠标记将第二光掩模掩模版与由第一光掩模掩模版限定的图案对准。在实施例中,第一对准标记和重叠标记重叠。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种半导体器件,包括:
模塑料,密封第一集成电路管芯和第二集成电路管芯;
介电层,位于所述模塑料、所述第一集成电路管芯和所述第二集成电路管芯上方;以及
金属化图案,位于所述介电层上方并且将所述第一集成电路管芯电连接到所述第二集成电路管芯,其中,所述金属化图案包括多条导线,并且其中,所述多条导线中的每条导线:
从所述金属化图案的第一区域穿过所述金属化图案的第二区域连续延伸至所述金属化图案的第三区域;以及
在所述金属化图案的第二区域中具有相同类型的制造异常。
2.根据权利要求1所述的半导体器件,其中,与所述金属化图案的第一区域和所述金属化图案的第三区域相比,所述金属化图案的第二区域中的多条导线中的每条导线的宽度增加。
3.根据权利要求1所述的半导体器件,其中,与所述金属化图案的第一区域和所述金属化图案的第三区域相比,所述金属化图案的第二区域中的所述多条导线中的每条导线的宽度减小。
4.根据权利要求1所述的半导体器件,其中,所述多条导线中的每条导线的侧壁在所述金属化图案的第二区域中未对准。
5.根据权利要求1所述的半导体器件,其中,所述金属化图案的第二区域设置在所述第一对准标记和所述第二对准标记之间。
6.根据权利要求5所述的半导体器件,还包括,所述第三对准标记和所述第四对准标记,其中,所述金属化图案包括位于所述第三对准标记和所述第四对准标记之间的第二多条导线,并且其中,所述第一对准标记和所述第三对准标记之间的距离等于所述第二对准标记和所述第四对准标记之间的距离。
7.根据权利要求6所述的半导体器件,其中,所述金属化图案包括位于所述第一对准标记和所述第三对准标记之间的第三多条导线。
8.一种形成半导体器件的方法,包括:
将第一集成电路管芯和第二集成电路管芯密封在模塑料中;
在所述第一集成电路管芯、所述第二集成电路管芯和所述模塑料上方沉积晶种层;
在所述晶种层上方沉积光刻胶;
对所述光刻胶的第一图案化区域实施第一曝光工艺以限定第一曝光区域;
在实施所述第一曝光工艺后,对所述光刻胶的第二图案化区域实施第二曝光工艺,以限定第二曝光区域,其中,所述第一图案化区域与所述第二图案化区域在拼接区域中重叠;
显影所述光刻胶以限定从所述第一图案区域穿过所述拼接区域延伸到所述第二图案区域的第一开口;
在所述第一开口中镀导电材料,其中,所述导电材料电连接所述第一集成电路管芯和所述第二集成电路管芯;以及
去除所述光刻胶。
9.根据权利要求8所述的方法,其中,所述第一曝光区域的形状在所述拼接区域中是三角形。
10.一种形成半导体器件的方法,包括:
在所述第一管芯、所述第二管芯和所述模塑料上方沉积光刻胶,其中,所述模塑料设置在所述第一管芯和所述第二管芯周围;
使用所述第一光掩模掩模版对所述光刻胶的第一图案化区域实施第一曝光工艺;
在实施所述第一曝光工艺之后,使用第二光掩模掩模版对所述光刻胶的第二图案化区域实施第二曝光工艺,其中,所述第一图案化区域和所述第二图案化区域在拼接区域中重叠,其中,实施所述第一曝光工艺包括将所述第一光掩模掩模版的第一三角形开口放置在所述拼接区域正上方,并且其中,实施所述第二曝光工艺包括将所述第二光掩模掩模版的第二三角形开口放置在所述拼接区域正上方;
显影所述光刻胶以在所述光刻胶中形成第三开口,其中,所述第三开口从所述第一图案区域穿过所述拼接区域延伸到所述第二图案化区域;以及
在所述第三开口中电导电材料,其中,所述导电材料将所述第一管芯电连接到所述第二管芯。
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US20200105711A1 (en) | 2020-04-02 |
CN110970381B (zh) | 2021-10-15 |
KR102311442B1 (ko) | 2021-10-14 |
US11158600B2 (en) | 2021-10-26 |
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