TW202111907A - 以矽中介層作為互連橋的封裝晶片結構 - Google Patents

以矽中介層作為互連橋的封裝晶片結構 Download PDF

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TW202111907A
TW202111907A TW108132054A TW108132054A TW202111907A TW 202111907 A TW202111907 A TW 202111907A TW 108132054 A TW108132054 A TW 108132054A TW 108132054 A TW108132054 A TW 108132054A TW 202111907 A TW202111907 A TW 202111907A
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semiconductor die
fan
package
connection line
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蔡佩君
徐宏欣
張簡上煜
林南君
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力成科技股份有限公司
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Priority to TW108132054A priority Critical patent/TW202111907A/zh
Priority to US16/679,326 priority patent/US11088080B2/en
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Abstract

本發明的封裝晶片結構將多晶片晶粒上提拉出設置於扇出型封裝體之上，透過預先形成的矽中介層作為互連橋結構以進行晶片間的微細間距高I/O訊號連接。於扇出型封裝體上下側分別具有第一重佈線層以及第二重佈線層，以提供上層的半導體晶粒透過重佈線層以及扇出型封裝體中的連接線路連接至基板上。

Description

以矽中介層作為互連橋的封裝晶片結構
本發明有關一種封裝結構，尤指一種以矽中介層作為互連橋的封裝晶片結構。
目前因應高階晶片的需求量大增，與其對小面積、高輸出(I/O)、高散熱、低雜訊等特性的產品需求，後段封裝製程不斷朝向縮小晶片體積或在同等面積內整合更多晶片的方向發展。隨著功能增強、尺寸小型化的需求，將多個裸晶整合在同一個封裝的多晶片（multi die）封裝技術已經是成熟作法。
目前的多晶片封裝是將2個或2個以上的晶片，透過整合（水平放置）以及/或堆疊的方式封裝在同一個封裝裡。就整合的水平放置架構來說，傳統的晶片間連接（interconnection）由底層的基板（substrate）以及重佈線層（RDL）來實現，而基板與重佈線層可接受的線寬/線距比有其製程能力的限制，因而在同一層扇出型封裝製程中，限制了多晶片的整合能力，使得晶片間連接往往需要更長的路徑或更多的重佈線層才能滿足設計上的需求。而更長的連接路徑以及/或更多的重佈線層也就意味著裝置的訊號以及功耗表現都會受到影響。
為了解決上述問題，本發明的實施例中提供了以矽中介層作為互連橋的封裝晶片結構。
根據本發明的一實施例，以矽中介層作為互連橋的封裝晶片結構包含有一扇出型封裝體、一第一半導體晶粒以及一第二半導體晶粒。該扇出型封裝體包含有一互連橋結構、一第一連接線路以及一第二連接線路，該互連橋結構嵌入封裝於一封膠體中，該扇出型封裝體具有彼此相對的一下表面以及一上表面。該第一半導體晶粒以及該第二半導體晶粒彼此相鄰設置於該扇出型封裝體的該上表面上，該第一半導體晶粒具有複數個第一接點以及複數個第二接點，該第二半導體晶粒具有複數個第三接點以及複數個第四接點。該互連橋結構對應設置於該第一半導體晶粒的該複數個第一接點以及該第二半導體晶粒的該複數個第三接點下方，且該複數個第一接點透過該互連橋結構與該複數個第三接點形成晶片間連接。該扇出型封裝體以該下表面設置於一基板上，該複數個第二接點以及該複數個第四接點分別透過該第一連接線路以及該第二連接線路電性連接於該基板上。
於本發明實施例中，該封裝晶片結構另包含一第一重佈線層，設置於該扇出型封裝體的該上表面，該第一半導體晶粒以及該第二半導體晶粒設置於該第一重佈線層上，該複數個第二接點以及該複數個第四接點透過該第一重佈線層分別連接該第一連接線路以及該第二連接線路。
於本發明實施例中，該封裝晶片結構另包含一第二重佈線層，設置於該扇出型封裝體的該下表面與該基板之間，該第二重佈線層包含複數個接觸墊，該複數個第二接點以及該複數個第四接點分別透過該第一連接線路以及該第二連接線路由該複數個接觸墊電性連接於該基板上。
於本發明實施例所提供的封裝晶片結構中，其中該第一連接線路以及該第二連接線路為銅柱或直通樹脂導孔。
於本發明實施例所提供的封裝晶片結構中，其中該互連橋結構另以矽穿孔封裝電性連接該基板與至少一部分該複數個第一接點或至少一部分該複數個第三接點。
於本發明實施例所提供的封裝晶片結構中，其中該互連橋結構為矽中介層，該互連橋結構係局部設置於該封膠體內，且該矽中介層係於封膠前以矽製程形成。
於本發明實施例所提供的封裝晶片結構中，其中該互連橋結構的最小線寬/線距比不大於1/1微米。
於本發明實施例所提供的封裝晶片結構中，其中該第一半導體晶粒的該複數個第一接點以及該第二半導體晶粒的該複數個第三接點為微細間距的信號接點，且該複數個第一接點以及該複數個第三接點的間距不大於30微米。
於本發明實施例所提供的封裝晶片結構中，其中該第一半導體晶粒的該複數個第二接點以及該第二半導體晶粒的該複數個第四接點為廣間距的電力或接地接點，且該複數個第二接點以及該複數個第二接點的間距大於30微米。
於本發明實施例所提供的封裝晶片結構中，其中一保護封膠體另設置於該扇出型封裝體的該上表面上且覆蓋該第一半導體晶粒以及該第二半導體晶粒。
本發明的封裝晶片結構透過局部的矽中介互連橋結構，讓多晶片整合或是系統級封裝(SiP)更加容易，並且最短化的連接路徑也增加訊號/功耗表現。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解，製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。此外，「耦接」或「連接」一詞在此係包含任何直接及間接的電氣或結構連接手段。因此，若文中描述一第一裝置耦接/連接於一第二裝置，則代表該第一裝置可直接電氣/結構連接於該第二裝置，或透過其他裝置或連接手段間接地電氣/結構連接至該第二裝置。
請參考第1圖，第1圖為本發明以矽中介層作為互連橋的封裝晶片結構一第一實施例的剖面示意圖。封裝晶片結構100將半導體晶粒上拉設置於扇出型封裝體上，在第一實施例中，封裝晶片結構100包含一扇出型封裝體10、至少一第一半導體晶粒21以及一第二半導體晶粒22。扇出型封裝體10以封膠體13將一互連橋結構20嵌入封裝(molding)於內，扇出型封裝體10具有彼此相對的一下表面18以及一上表面19，半導體晶粒則疊置於上表面19上，並與扇出型封裝體10透過下表面18一同設置於基板50上。本發明的封裝晶片結構100屬於多晶片封裝，將2個或2個以上的晶粒，透過水平放置整合方式封裝為一，除了於第1圖的實施例中的封裝晶片結構100包含第一半導體晶粒21以及第二半導體晶粒22以外，也可包含更多的半導體晶粒而為多晶片封裝架構。第一半導體晶粒21以及第二半導體晶粒22彼此相鄰設置於扇出型封裝體10的上表面19上，其中第一半導體晶粒21以及第二半導體晶粒22可包含複合型態的輸出入連接點結構，例如第一半導體晶粒21具有複數個第一接點211以及複數個第二接點212，第二半導體晶粒22具有複數個第三接點223以及複數個第四接點224，其中於一實施例中，第一半導體晶粒21的複數個第一接點211以及第二半導體晶粒22的複數個第三接點223為微細間距(pitch)的信號接點，第一接點211以及第三接點223為晶片間連接的訊號接點，較佳地，其間距不大於30微米，但不以此為限。另外，於第一半導體晶粒21以及第二半導體晶粒22的底部另可設置底部填充物24(underfill, UF)，用以增強接點的信賴度。
為了在第一半導體晶粒21與第二半導體晶粒22之間進行晶片間連接，透過先進製程的互連橋結構20作為晶粒之間的互連橋(interconnection bridge)，而在第一實施例中，可使用最小線寬/線距比達1/1微米或小於1/1微米的矽中介層(Si interposer)作為互連橋結構20，並且於封膠前以矽製程形成後，局部設置於封膠體13內。互連橋結構20對應設置於第一半導體晶粒21的複數個第一接點211以及第二半導體晶粒22的複數個第三接點223下方，使具有微細間距的第一接點211以及第三接點223可透過互連橋結構20以最短路徑形成晶片間連接。如前所述，以矽中介層製程的互連橋結構20可提供的最小線寬/線距比可小於1/1微米，因此能在不需要額外的繞線(routing)或重佈線(redistribution)的前提下，即能高效建立晶片間的高I/O連接。特別說明的是，在本發明的實施例中以一個互連橋結構20連接兩個半導體晶粒，但本發明不以此為限，於其他實施例中，也可以在同一個扇出型封裝體10中嵌入2個或多個互連橋結構20，以作為扇出型封裝體10上層2個或多個半導體晶粒之間不同功能的互連橋。
請繼續參考第1圖。除了上述微細間距的信號接點外，第一半導體晶粒21以及第二半導體晶粒22也分別另外可具有較大間距（例如大於30微米，但不以此為限）的複數個第二接點212以及複數個第四接點224，例如可為廣間距的訊號、電力或接地接點，因此第一半導體晶粒21以及第二半導體晶粒22均可為複合接點設計(hybrid bump design)的結構，但不以此為限。這些較大間距的信號接點則可分別透過扇出型封裝體10中的第一連接線路11以及第二連接線路12電性連接於基板50上。於一實施例中，複數個第二接點212以及複數個第四接點224藉由扇出型封裝體10的扇出重佈線結構與基板50連接。
例如，封裝晶片結構100另可包含一第一重佈線層30以及一第二重佈線層40。第一重佈線層30設置於扇出型封裝體10的上表面19，而第一半導體晶粒21以及第二半導體晶粒22則設置於第一重佈線層30上，第一半導體晶粒21以及第二半導體晶粒22的複數個第二接點212以及複數個第四接點224透過第一重佈線層30分別連接至第一連接線路11以及第二連接線路12。第二重佈線層40設置於扇出型封裝體10的下表面18與基板50之間，第二重佈線層40包含複數個接觸墊41，而複數個第二接點212以及複數個第四接點224在連接至第一連接線路11以及第二連接線路12後，再經由第二重佈線層40由複數個接觸墊41電性連接於基板50上。
特別說明的是，在第1圖的第一實施例中，第一連接線路11以及第二連接線路12可為銅柱(cu pillar)結構，並且除了作為第一重佈線層30與第二重佈線層40之間的訊號連接通道外，於其他實施例中，亦可在封裝晶片結構100上另外疊加一或多個上層的封裝晶片結構，而上層的封裝晶片結構也透過第一連接線路11以及第二連接線路12，再經由第二重佈線層40由複數個接觸墊41電性連接於基板50上。除了銅柱外，在第2圖中，第二實施例的封裝晶片結構200的第一連接線路11’以及第二連接線路12’也可以是直通樹脂導孔(through mold via, TMV)的結構。
請參考第3圖。在第3圖的第三實施例中，封裝晶片結構300大致與封裝晶片結構100相同，其中相同元件以相同的編號表示。在第三實施例的互連橋結構20中，可另外以矽穿孔封裝23電性連接於基板50，也就是說，因應設計需求，第一半導體晶粒21中的至少一部分第一接點211以及/或第二半導體晶粒22至少一部分第三接點223也能透過矽穿孔封裝23直接連接至第二重佈線層40，或是經由第二重佈線層40連接基板50。
請參考第4圖。在第4圖的第四實施例中，封裝晶片結構400大致與前述各實施例的封裝晶片結構100、200、300相同，其中相同元件以相同的編號表示。在第四實施例中，另可將一保護封膠體60設置於扇出型封裝體10的上表面19上，並且覆蓋第一半導體晶粒21以及第二半導體晶粒22，以對頂層的半導體晶粒提供保護。
本發明的封裝晶片結構將多晶片晶粒上提拉出設置於扇出型封裝體之上，其中多晶片晶粒中至少有兩個晶粒是屬於複合接點設計(hybrid bump design)的結構，也就是同時具有微細間距和廣間距的設計。透過預先形成的矽中介層作為互連橋結構以進行晶片間的微細間距高I/O訊號連接。於扇出型封裝體上下側分別具有第一重佈線層以及第二重佈線層，以提供上層的半導體晶粒透過重佈線層以及扇出型封裝體中的連接線路連接至基板上。透過局部的矽中介互連橋結構，讓多晶片整合或是系統級封裝(SiP)更加容易，並且最短化的連接路徑也增加訊號/功耗表現。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10:扇出型封裝體 11、11':第一連接線路 12、12':第二連接線路 13:封膠體 18:下表面 19:上表面 20:互連橋結構 21:第一半導體晶粒 211:第一接點 212:第二接點 22:第二半導體晶粒 223:第三接點 224:第四接點 23:矽穿孔封裝 24:底部填充物 30:第一重佈線層 40:第二重佈線層 41:接觸墊 50:基板 60:保護封膠體 100、200、300、400:封裝晶片結構
第1圖為本發明以矽中介層作為互連橋的封裝晶片結構一第一實施例的剖面示意圖。 第2圖為本發明以矽中介層作為互連橋的封裝晶片結構一第二實施例的剖面示意圖。 第3圖為本發明以矽中介層作為互連橋的封裝晶片結構一第三實施例的剖面示意圖。 第4圖為本發明以矽中介層作為互連橋的封裝晶片結構一第四實施例的剖面示意圖。
10:扇出型封裝體
11:第一連接線路
12:第二連接線路
13:封膠體
18:下表面
19:上表面
20:互連橋結構
21:第一半導體晶粒
211:第一接點
212:第二接點
22:第二半導體晶粒
223:第三接點
224:第四接點
24:底部填充物
30:第一重佈線層
40:第二重佈線層
41:接觸墊
50:基板
100:封裝晶片結構

Claims (10)

  1. 一種以矽中介層作為互連橋的封裝晶片結構，包含有： 一扇出型封裝體，包含有一互連橋結構、一第一連接線路以及一第二連接線路，該互連橋結構嵌入封裝於一封膠體中，該扇出型封裝體具有彼此相對的一下表面以及一上表面；以及 一第一半導體晶粒以及一第二半導體晶粒，彼此相鄰設置於該扇出型封裝體的該上表面上，該第一半導體晶粒具有複數個第一接點以及複數個第二接點，該第二半導體晶粒具有複數個第三接點以及複數個第四接點； 其中該互連橋結構對應設置於該第一半導體晶粒的該複數個第一接點以及該第二半導體晶粒的該複數個第三接點下方，且該複數個第一接點透過該互連橋結構與該複數個第三接點形成晶片間連接； 其中該扇出型封裝體以該下表面設置於一基板上，該複數個第二接點以及該複數個第四接點分別透過該第一連接線路以及該第二連接線路電性連接於該基板上。
  2. 如請求項1所述的封裝晶片結構，另包含一第一重佈線層，設置於該扇出型封裝體的該上表面，該第一半導體晶粒以及該第二半導體晶粒設置於該第一重佈線層上，該複數個第二接點以及該複數個第四接點透過該第一重佈線層分別連接該第一連接線路以及該第二連接線路。
  3. 如請求項1所述的封裝晶片結構，另包含一第二重佈線層，設置於該扇出型封裝體的該下表面與該基板之間，該第二重佈線層包含複數個接觸墊，該複數個第二接點以及該複數個第四接點分別透過該第一連接線路以及該第二連接線路由該複數個接觸墊電性連接於該基板上。
  4. 如請求項3所述的封裝晶片結構，其中該第一連接線路以及該第二連接線路為銅柱或直通樹脂導孔。
  5. 如請求項3所述的封裝晶片結構，其中該互連橋結構另以矽穿孔封裝電性連接該基板與至少一部分該複數個第一接點或至少一部分該複數個第三接點。
  6. 如請求項1所述的封裝晶片結構，其中該互連橋結構為矽中介層，該互連橋結構係局部設置於該封膠體內，且該矽中介層係於封膠前以矽製程形成。
  7. 如請求項6所述的封裝晶片結構，其中該互連橋結構的最小線寬/線距比不大於1/1微米。
  8. 如請求項1所述的封裝晶片結構，其中該第一半導體晶粒的該複數個第一接點以及該第二半導體晶粒的該複數個第三接點為微細間距的信號接點，且該複數個第一接點以及該複數個第三接點的間距不大於30微米。
  9. 如請求項1所述的封裝晶片結構，其中該第一半導體晶粒的該複數個第二接點以及該第二半導體晶粒的該複數個第四接點為廣間距的電力或接地接點，且該複數個第二接點以及該複數個第二接點的間距大於30微米。
  10. 如請求項1所述的封裝晶片結構，其中一保護封膠體另設置於該扇出型封裝體的該上表面上且覆蓋該第一半導體晶粒以及該第二半導體晶粒。
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