TW201923989A - 具有探針後可組態度之半導體裝置 - Google Patents

具有探針後可組態度之半導體裝置 Download PDF

Info

Publication number
TW201923989A
TW201923989A TW107136282A TW107136282A TW201923989A TW 201923989 A TW201923989 A TW 201923989A TW 107136282 A TW107136282 A TW 107136282A TW 107136282 A TW107136282 A TW 107136282A TW 201923989 A TW201923989 A TW 201923989A
Authority
TW
Taiwan
Prior art keywords
die
circuit
contact pad
semiconductor
contact
Prior art date
Application number
TW107136282A
Other languages
English (en)
Other versions
TWI695457B (zh
Inventor
詹姆斯 Ｅ 戴维斯
凱文 Ｇ 都斯曼
傑佛瑞 P 萊特
瓦倫 Ｌ 包爾
Original Assignee
美商美光科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商美光科技公司 filed Critical 美商美光科技公司
Publication of TW201923989A publication Critical patent/TW201923989A/zh
Application granted granted Critical
Publication of TWI695457B publication Critical patent/TWI695457B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/041—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00
    • H01L25/043—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種半導體裝置總成包含一基板及經耦合至該基板之一晶粒。該晶粒包含：一第一接觸墊，其經電耦合至該晶粒上之一第一電路，該第一電路包含至少一個主動電路元件；一第二接觸墊，其經電耦合至該晶粒上之一第二電路，該第二電路僅包含被動電路元件；及一電鍍墊，其將該第一接觸墊之至少一部分電耦合至該第二接觸墊之至少一部分。該基板包含經電耦合至該晶粒上之該電鍍墊之一基板接觸件。

Description

具有探針後可組態度之半導體裝置
本發明大體上係關於半導體裝置，且更特定言之係關於具有探針後可組態度之半導體裝置。
封裝式半導體晶粒(包含記憶體晶片、微處理器晶片及成像器晶片)通常包含安裝於一基板上且圍封於一塑膠保護罩中或由一導熱蓋覆蓋之一或多個半導體晶粒。晶粒可包含主動電路(例如，提供功能構件，諸如記憶體胞元、處理器電路及/或成像器裝置)及/或被動構件(例如，電容器、電阻器等)以及電連接至該等電路之接合墊。接合墊可電連接至保護罩外部之端子以容許晶粒連接至更高階電路。
例如，圖1係一半導體裝置總成100之一簡化部分橫截面視圖，其包含以一疊瓦(shingled)方式堆疊於一基板101上且由一囊封劑170覆蓋之多個半導體晶粒102及103。各晶粒包含一或多個接觸墊(諸如接觸墊122及123)以提供至一對應積體電路(諸如電路162及163)之連接能力。接觸墊122及123可藉由線接合131及132 (展示為一菊鍊組態)連接至一基板接觸件121以經由焊球151 (藉由通孔152)提供至電路162及163之連接能力。
在一些半導體晶粒之情況下，各種接合墊可連接至一晶粒中之多個電路。例如，在一NAND記憶體晶粒中，一單一接合墊可連接至一主動驅動器電路及一被動ESD保護電路(例如，包含一或多個電容器)兩者。ESD保護電路可經設計以提供一所要量之電容以保護單一主動驅動器電路。在包含具有並聯連接之主動驅動器電路之多個此等NAND記憶體晶粒之一半導體裝置總成中(例如，其中來自各NAND記憶體晶粒之對應接合墊連接至相同外部端子)，由來自並聯連接之各晶粒之ESD保護電路提供之過量電容可使裝置效能降級。此可藉由針對不同封裝密度設計不同NAND記憶體晶粒而解決(例如，一NAND記憶體晶粒經組態以單獨封裝，具有較少電容式ESD保護電路之一不同NAND記憶體晶粒經組態以封裝為兩個之一堆疊，具有甚至更少電容式ESD保護電路之又一NAND記憶體晶粒經組態以封裝為四個之一堆疊等)，但針對各可能封裝組態設計及製造多個不同半導體晶粒係極其昂貴的。因此，需要可經組態為取決於封裝晶粒之組態而具有不同量之ESD保護之一半導體晶粒。
在一實施例中，一種半導體裝置總成包括：一基板；及一晶粒，其耦合至該基板；該晶粒包含：一第一接觸墊，其電耦合至該晶粒上之一第一電路，該第一電路包含至少一個主動電路元件；一第二接觸墊，其電耦合至該晶粒上之一第二電路，該第二電路僅包含被動電路元件；及一電鍍墊，其將該第一接觸墊之至少一部分電耦合至該第二接觸墊之至少一部分；其中該基板包含電耦合至該晶粒上之該電鍍墊之一基板接觸件。
在另一實施例中，一種半導體裝置總成包括：一基板，其包含一基板接觸件；及複數個半導體晶粒，其等各包含：一第一接觸墊，其電耦合至該半導體晶粒上之一第一電路，該第一電路包含至少一個主動電路元件；及一第二接觸墊，其電耦合至該半導體晶粒上之一第二電路，該第二電路僅包含被動電路元件；其中全部該複數個半導體晶粒之該等第一接觸墊電耦合至該基板接觸件，且其中該複數個半導體晶粒之至少一者進一步包含將該第一接觸墊之至少一部分電耦合至該第二接觸墊之至少一部分之一電鍍墊。
在另一實施例中，一種製造一半導體裝置之方法包括：提供包含複數個半導體晶粒之一晶圓，其中該複數個半導體晶粒之各者包含：一第一接觸墊，其電耦合至該半導體晶粒上之一第一電路，該第一電路包含至少一個主動電路元件；及一第二接觸墊，其電耦合至該半導體晶粒上之一第二電路，該第二電路僅包含被動電路元件；針對該複數個半導體晶粒之各者，電鍍將該第一接觸墊之至少一部分電耦合至該第二接觸墊之至少一部分之一電鍍墊；及從該晶圓單粒化該複數個半導體晶粒。
相關申請案之交叉參考
本申請案含有與James E. Davis、John B. Pusey、Zhiping Yin及Kevin G. Duesman之標題為「SEMICONDUCTOR DEVICES WITH PACKAGE-LEVEL CONFIGURABILITY」之一同時申請之美國專利申請案相關的標的物。相關申請案(其之揭示內容係以引用的方式併入本文中)經讓渡給Micron Technology, Inc.，且係由代理人檔案編號第010829-9242.US00號識別。
在以下描述中，論述許多特定細節以提供對本發明之實施例之一透徹且實現描述。然而，熟習相關技術者將認知，可在不具有特定細節之一或多者之情況下實踐本發明。在其他例項中，未展示或未詳細描述通常與半導體裝置相關聯之熟知結構或操作以避免模糊本發明之其他態樣。一般言之，應理解，除本文中揭示之彼等特定實施例以外的各種其他裝置、系統及方法可在本發明之範疇內。
如上文論述，當具有連接至與一主動電路(例如，一驅動器電路)相同之接合墊之一ESD保護電路之半導體晶粒以不同封裝密度連接在一起時，無法針對各封裝密度最佳化由ESD保護電路提供之電容量。因此，根據本發明之半導體裝置之若干實施例可提供一所提供電容之封裝級可組態度以克服此挑戰。
本發明之若干實施例係關於半導體裝置總成，其等包含一基板及耦合至該基板之一晶粒。該晶粒包含：一第一接觸墊，其電耦合至該晶粒上之一第一電路，該第一電路包含至少一個主動電路元件；一第二接觸墊，其電耦合至該晶粒上之一第二電路，該第二電路僅包含被動電路元件；及一電鍍墊，其將該第一接觸墊之至少一部分電耦合至該第二接觸墊之至少一部分。該基板包含電耦合至該晶粒上之該電鍍墊之一基板接觸件。該等半導體裝置總成可進一步包含一第二晶粒，該第二晶粒包含：一第三接觸墊，其電耦合至該第二晶粒上之一第三電路，該第三電路包含至少一第二主動電路元件；及一第四接觸墊，其電耦合至該第二晶粒上之一第四電路，該第四電路僅包含被動電路元件。該基板接觸件可電耦合至該第二晶粒上之該第三接觸墊，且可從該第二晶粒上之該第四接觸墊電斷開或藉由將該第三接觸墊之至少一部分電耦合至該第四接觸墊之至少一部分之另一電鍍墊電耦合至該第二晶粒上之該第四接觸墊。
下文描述半導體裝置之若干實施例之特定細節。術語「半導體裝置」通常指包含一半導體材料之一固態裝置。一半導體裝置可包含例如一半導體基板、晶圓或從一晶圓或基板單粒化之晶粒。貫穿本發明，通常在半導體晶粒之內容脈絡中描述半導體裝置；然而，半導體裝置不限於半導體晶粒。
術語「半導體裝置封裝」可指具有經併入至一共同封裝中之一或多個半導體裝置之一配置。一半導體封裝可包含部分或完全囊封至少一個半導體裝置之一外殼或殼體。一半導體裝置封裝亦可包含攜載一或多個半導體裝置且經附接至殼體或以其他方式被併入至殼體中之一中介基板。術語「半導體裝置總成」可指一或多個半導體裝置、半導體裝置封裝及/或基板(例如，中介層、支撐件或其他適合基板)之一總成。例如，可以離散封裝形式、條狀或矩陣形式及/或晶圓面板形式來製造半導體裝置總成。如本文中使用，術語「垂直」、「橫向」、「上部」及「下部」可指半導體裝置或裝置總成中的構件鑑於圖中展示之定向的相對方向或位置。例如，「上部」及「最上部」可指分別經定位成比另一構件或相同構件之部分更靠近一頁之頂部或最靠近頁之頂部之一構件。然而，此等術語應廣泛地解釋為包含具有其他定向之半導體裝置，諸如倒置或傾斜定向，其中頂部/底部、在……上/在……下、在……上方/在……下方、向上/向下及左/右可隨定向而互換。
圖2係一半導體裝置總成200之一簡化示意圖，其包含經耦合至一基板201之一半導體晶粒202。晶粒包含接觸墊，諸如接觸墊211及212，其等各經連接至具有主動組件之一積體電路(示意性地經繪示為一驅動器(DRV)電路)及具有被動組件之一積體電路(示意性地經繪示為一靜電放電(ESD)保護電路)兩者。接觸墊211及212係藉由線接合230電耦合至基板接觸件221及222。如參考圖2可見，若半導體晶粒202已經組態為具有適合於為一單一驅動器電路提供ESD保護之一電容量，則將另一此半導體晶粒添加至總成200可能不期望地增加基板接觸件221及222所「看見」的電容。
為解決此問題，本發明之實施例可提供一半導體晶粒，其中一主動電路及經組態以為其提供ESD保護之被動電路經連接至單獨接觸墊，使得可提供一所要量之電容而無關於一封裝總成中提供之晶粒數目。例如，圖3係根據本發明之一實施例之一半導體裝置300之一簡化示意圖。半導體裝置300包含複數個接觸墊(諸如第一接觸墊311至第四接觸墊314)以提供至半導體裝置300中之電路的連接能力。例如，第一接觸墊311提供至具有主動組件之一第一電路371 (例如，一驅動器電路)之連接能力，且第二接觸墊312提供至具有被動組件之一第二電路372 (例如，一ESD保護電路)之連接能力。類似地，第三接觸墊313提供至具有主動組件之一第三電路373 (例如，一驅動器電路)之連接能力，且第四接觸墊314提供至具有被動組件之一第四電路374 (例如，一ESD保護電路)之連接能力。藉由為各被動電路提供一專用接觸墊，半導體裝置300利用多個相同半導體晶粒來實現不同封裝密度，同時提供一所要量之ESD保護，且不具有(例如)導致驅動器電路371及373消耗過量電力之過量電容。
此可參考圖4更好地理解，圖4係根據本發明之一實施例之一半導體裝置總成400之一簡化示意圖。總成400包含一基板401及兩個半導體晶粒402及403 (例如，相同半導體晶粒)。如同上文圖3中繪示之半導體裝置300，各半導體晶粒402及403包含多個接觸墊，諸如第一接觸墊411至第四接觸墊414，其等各提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)之連接能力。由於各ESD保護電路具備一專用接觸墊，所以總成400可經組態為具有針對各驅動器電路之一所要量之ESD保護。
如參考圖4可見，基板401包含兩個基板接觸件421及422。第一基板接觸件421 (例如，藉由一線接合430)連接至一電鍍墊440，該電鍍墊440將下部半導體晶粒402之第一接觸墊411 (對應於一驅動器電路)之至少一部分連接至第二接觸墊412 (對應於一ESD保護電路)之至少一部分。電鍍墊440進一步藉由另一線接合連接至上部半導體晶粒403之僅第一接觸墊411。以此方式，第一基板接觸件421電耦合至下部半導體晶粒402之第一接觸墊411及第二接觸墊412兩者及上部半導體晶粒403之僅第一接觸墊411。類似地，第二基板接觸件422 (例如，藉由一線接合430)連接至總成400中之各半導體晶粒402及403之第三接觸墊413 (對應於一驅動器電路)，但連接至總成400中之僅一個半導體晶粒402之第四接觸墊414 (對應於一ESD保護電路)。藉由使上部半導體晶粒403上之第二接觸墊412及第四接觸墊414 (對應於ESD保護電路)從基板接觸件421及422電斷開(例如，藉由不用一電鍍墊(諸如下部半導體晶粒402上之電鍍墊440)將此等墊連接至對應驅動器墊411及413)，各基板接觸件421及422所連接之電路之電容小於若連接來自總成400中之各晶粒之ESD保護電路的情況。
根據本發明之一個態樣，可使用晶圓級重佈層(RDL)製造技術(例如，在晶粒已從其面板或晶圓單粒化之前)將電鍍墊440提供於一半導體晶粒(諸如下部半導體晶粒402)之第一接觸墊411及第二接觸墊412上方。電鍍墊之製造可在一探針操作之後執行，其中已測試且分組一晶圓或面板上之晶粒以判定其等之最終封裝密度。例如，在一探測操作中判定為能夠具有一較高操作速度之晶粒可經分組用於一較高封裝密度(例如，雙裝置封裝(DDP)、四裝置封裝(QDP)或甚至更高密度)，而在一探測操作中判定為能夠具有較低操作速度之晶粒可經分組用於較低封裝密度(例如，單裝置封裝(SDP)密度)。基於一晶圓中之晶粒待組裝之所判定封裝密度，可(例如，在預定用於SDP密度之全部晶粒中、在預定用於DDP或QDP密度之下部晶粒中)包含或(例如，在預定用於DDP或QDP密度之上部晶粒中或在預定用於更高封裝密度之全部晶粒中)省略電鍍墊。在一探針操作之後將ESD電路連接至驅動器電路之能力容許對用於多裝置封裝中之其他相同晶粒設計執行有效晶圓級操作。
儘管圖4已經描述及繪示為包含多個相同半導體晶粒，然在本發明之其他實施例中，具有不同類型之晶粒之半導體裝置總成可具備類似特徵。例如，在一項實施例中，一半導體裝置總成可包含一邏輯晶粒及一記憶體晶粒，其等之一者或兩者可包含用於將被動電路連接為所要探針後之離散接觸墊。再者，儘管圖4已經描述及繪示為包含具有兩個驅動器電路之半導體晶粒，然熟習此項技術者將容易地明白，此實施例僅為一個實例，且亦可提供具有不同數目個驅動器電路之半導體晶粒。此外，圖4已經描述及繪示為與用於驅動器電路之接觸墊分開地提供用於ESD保護電路之接觸墊，但在其他實施例中，可提供具有除驅動器以外的其他主動元件之電路，且同樣可提供僅包含被動組件(例如，電阻器、電容器、電感器等)之其他電路。
儘管在前述實例中已將半導體晶粒描述及繪示為包含對應於各驅動器電路之一單一ESD保護電路，然在本發明之其他實施例中，可藉由包含具有對應於一半導體晶粒上之各驅動器電路之專用接觸墊之多個ESD保護電路而提供額外可組態度。例如，圖5係根據本發明之一實施例之一半導體裝置500之一簡化示意圖。半導體裝置500包含複數個接觸墊(諸如第一接觸墊511至第六接觸墊516)以提供至半導體裝置500中之電路之連接能力。例如，第一接觸墊511提供至具有主動組件之一第一電路571 (例如，一驅動器電路)之連接能力，且第二接觸墊512及第三接觸墊513分別提供至僅包含被動組件之第二電路572及第三電路573 (例如，ESD保護電路)之連接能力。類似地，第四接觸墊514提供至具有主動組件之一第四電路574 (例如，一驅動器電路)之連接能力，且第五接觸墊515及第六接觸墊516分別提供至僅包含被動組件之第五電路575及第六電路576 (例如，ESD保護電路)之連接能力。藉由為各主動電路提供多個對應被動電路(各具有其等自身專用接觸墊)，半導體裝置500利用多個相同半導體晶粒實現不同封裝密度，同時提供一所要量之ESD保護而不具有例如導致驅動器電路571及574消耗過量電力之過量電容。
此可參考圖6更好地理解，圖6係根據本發明之一實施例之一半導體裝置總成600之一簡化示意圖。總成600包含一基板601及兩個半導體晶粒602及603 (例如，相同半導體晶粒)。如同上文圖5中繪示之半導體裝置500，各半導體晶粒602及603包含多個接觸墊，諸如第一接觸墊611至第六接觸墊616，其等各提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)之連接能力。由於各ESD保護電路具備一專用接觸墊，所以總成600可經組態為具有針對各驅動器電路之一所要量之ESD保護。
如參考圖6可見，基板601包含兩個基板接觸件621及622。第一基板接觸件621 (例如，藉由一線接合630)連接至一第一電鍍墊640，該第一電鍍墊640將下部半導體晶粒602之第一接觸墊611 (對應於一驅動器電路)之至少一部分連接至第二接觸墊612 (對應於一ESD保護電路)之至少一部分及第三接觸墊613 (對應於另一ESD保護電路)之至少一部分。第一電鍍墊640進一步藉由另一線接合連接至上部半導體晶粒603之一第二電鍍墊642，該第二電鍍墊642連接上部半導體晶粒603之第一接觸墊611及第二接觸墊612 (但並非第三接觸墊613)之至少一部分。以此方式，第一基板接觸件621電耦合至下部半導體晶粒602之第一、第二及第三接觸墊611至613及上部半導體晶粒之僅第一接觸墊612及第二接觸墊612。類似地，第二基板接觸件622連接至總成600中之各半導體晶粒602及603之第四接觸墊614 (對應於一驅動器電路)，且連接至總成600中之各半導體晶粒602及603之第五接觸墊615 (對應於一ESD保護電路)，但連接至總成600中之僅一個半導體晶粒602之第六接觸墊616 (對應於另一ESD保護電路)。藉由使上部半導體晶粒603上之第三接觸墊613及第六接觸墊616 (對應於ESD保護電路)從基板接觸件621及622電斷開，各基板接觸件621及622所連接之電路之電容小於若連接來自總成600中之各晶粒之ESD保護電路的情況。
儘管在前述實施例中已繪示及描述具有兩個半導體晶粒之半導體裝置總成，然在本發明之其他實施例中，半導體裝置總成可包含不同數目個晶粒。例如，圖7係根據本發明之一實施例之包含四個半導體晶粒之一半導體裝置總成700之一簡化示意圖。總成700包含一基板701及四個半導體晶粒702至705 (例如，相同半導體晶粒)。如同上文圖3中繪示之半導體裝置300，各半導體晶粒702至705包含多個接觸墊，諸如第一接觸墊711至第四接觸墊714，其等各提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)之連接能力。由於各ESD保護電路具備一專用接觸墊，所以總成700可經組態為具有針對各驅動器電路之一所要量之ESD保護。
如參考圖7可見，基板701包含兩個基板接觸件721及722。第一基板接觸件721 係(例如，藉由一線接合730)連接至一電鍍墊770，該電鍍墊770將一第一半導體晶粒702之第一接觸墊711 (對應於一驅動器電路)之至少一部分連接至第二接觸墊712 (對應於一ESD保護電路)之至少一部分。電鍍墊740進一步係藉由額外線接合連接至總成700中之其他三個晶粒703至705之僅第一接觸墊711。以此方式，第一基板接觸件721經電耦合至第一半導體晶粒702之第一接觸墊711及第二接觸墊712兩者，以及總成700中之其他半導體晶粒703至705之僅第一接觸墊711。類似地，第二基板接觸件722係 (例如，藉由一線接合730)連接至總成700中之各半導體晶粒702至705之第三接觸墊713 (對應於一驅動器電路)，但係連接至總成700中之三個半導體晶粒703至705之第四接觸墊714 (對應於一ESD保護電路)。藉由使三個半導體晶粒703至705上之第二接觸墊712及第四接觸墊714 (對應於ESD保護電路)從基板接觸件721及722電斷開，各基板接觸件721及722所連接之電路的電容小於若連接來自總成700中之各晶粒之ESD保護電路的情況。
儘管在圖7中繪示之實施例中，總成中之僅一個晶粒的ESD保護電路經連接至基板接觸件，然在其他實施例中，一半導體裝置總成可包含具有經連接至其之(若干)基板接觸件之ESD保護電路的多個晶粒。例如，圖8係根據本發明之一實施例之一半導體裝置總成800之一簡化示意圖。總成800包含一基板801及四個半導體晶粒802至805 (例如，相同半導體晶粒)，各半導體晶粒包含多個接觸墊(諸如第一接觸墊811至第四接觸墊814)，以提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)的連接能力。
如參考圖8可見，基板801包含兩個基板接觸件821及822。第一基板接觸件821係 (例如，藉由線接合830)連接至總成800中之各半導體晶粒802至805之第一接觸墊811 (對應於一驅動器電路)，但係(例如，藉由電鍍墊840及842)連接至總成800中之僅兩個半導體晶粒802及803之第二接觸墊812 (對應於一ESD保護電路)。類似地，第二基板接觸件822 係(例如，藉由線接合830)連接至總成800中之各半導體晶粒802至805之第三接觸墊813 (對應於一驅動器電路)，但係(例如，藉由電鍍墊840及842)連接至總成800中之僅兩個半導體晶粒802及803之第四接觸墊814 (對應於一ESD保護電路)。藉由使兩個半導體晶粒804及805上之第二接觸墊812及第四接觸墊814 (對應於ESD保護電路)從基板接觸件821及822電斷開，各基板接觸件821及822所連接之電路的電容小於若連接來自總成800中之各晶粒之ESD保護電路的情況。
儘管在前述實施例中已繪示其中至少一個晶粒包含經附接ESD保護電路之半導體裝置總成，然在本發明之其他實施例中，半導體裝置總成可包含多個晶粒，其等全部包含未連接之ESD保護電路(例如，依賴於多個驅動器電路之固有電容，使得無需額外電容)。例如，圖9係根據本發明之一實施例之一半導體裝置總成900之一簡化示意圖。總成900包含一基板901及四個半導體晶粒902至905 (例如，相同半導體晶粒)，各半導體晶粒包含多個接觸墊(諸如第一接觸墊911至第四接觸墊914)，以提供至具有主動組件之一電路(例如，一驅動器電路)或具有被動組件之一電路(例如，一ESD保護電路)的連接能力。
如參考圖9可見，基板901包含兩個基板接觸件921及922。第一基板接觸件921 (例如，藉由線接合930)連接至總成900中之各半導體晶粒902至905之第一接觸墊911 (對應於一驅動器電路)，但(例如，歸因於缺少電鍍墊)不連接至總成900中之半導體晶粒902至905之任一者之第二接觸墊912 (對應於一ESD保護電路)。類似地，第二基板接觸件922 (例如，藉由線接合930)連接至總成900中之各半導體晶粒902至905之第三接觸墊913 (對應於一驅動器電路)，但(例如，歸因於缺少電鍍墊)不連接至總成900中之半導體晶粒902至905之任一者之第四接觸墊914 (對應於一ESD保護電路)。藉由使全部半導體晶粒902至905上之第二接觸墊912及第四接觸墊914 (對應於ESD保護電路)從基板接觸件921及922電斷開，各基板接觸件921及922所連接之電路之電容小於若連接來自總成900中之晶粒之任一者之ESD保護電路的情況。
儘管在前述例示性實施例中，半導體晶粒經描述為包含可視情況連接以增加一驅動器電路之電容之多個離散接觸墊，然本發明亦適用於其他電路設計。就此而言，本發明之其他實施例可為半導體晶粒提供多個接觸墊以視情況連接任何數目個不同電路，具有除ESD保護電路及驅動器電路以外或代替其等之任何所要功能。
根據本發明之各種實施例，可形成電鍍墊以用各種方式連接一半導體晶粒上之離散接觸墊。例如，圖10繪示根據本發明之一實施例之一半導體裝置之一簡化部分橫截面視圖。在圖10中繪示之半導體裝置1001中，接觸墊1002及1003 (例如，連接至半導體裝置中之離散電路，諸如一驅動器電路及一ESD保護電路)提供於鈍化或聚醯亞胺材料1005之一層下方，且因此由鈍化或聚醯亞胺材料之一小區域1006分離。為形成電連接此等接觸墊1002及1003之各者之至少一部分之一電鍍墊1008，可在各接觸墊上形成一晶種層1007 (例如，一Ti材料或類似物)，且可執行一電鍍操作以在各接觸墊1002及1003上之晶種層1007上方將一材料(例如，Cu、Al或類似物)電鍍至大於鈍化或聚醯亞胺材料之小區域1006之高度之一高度。一單一焊球1004可接著用於(例如，藉由電鍍墊1008)將接觸墊1002及1003兩者連接至另一半導體裝置或基板(例如，用一線接合)。
藉由進一步實例，圖11繪示根據本發明之一實施例之另一半導體裝置之一簡化部分橫截面視圖。在圖11中繪示之半導體裝置1101中，接觸墊1102及1103提供於鈍化或聚醯亞胺材料1105之一層下方，但已進行額外程序步驟(例如，遮罩及蝕刻)以從接觸墊1102及1103之間消除鈍化或聚醯亞胺材料1105 (例如，藉由在接觸墊1102及1103之間的區域下方包含一蝕刻停止材料1106以容許從其等之間蝕刻掉鈍化或聚醯亞胺材料1105)。此配置促進(例如，在各接觸墊1102及1103上之一晶種層1107上方)製造一單一電鍍墊1108，其中一頂表面大體上與鈍化或聚醯亞胺材料1105之一頂表面共面或低於該頂表面(例如，藉此不促成半導體裝置1100之一增加封裝高度)。一單一焊球1104可接著用於(例如，藉由電鍍墊1108)將接觸墊1102及1103兩者連接至另一半導體裝置或基板(例如，用一線接合)。
儘管在前述實例中已將半導體裝置總成描述為包含一單一半導體晶粒堆疊，然在本發明之其他實施例中，一半導體裝置總成可包含多個半導體晶粒堆疊，其中可視情況經由專用接觸墊連接被動電路。例如，在本發明之一項實施例中，一半導體裝置總成可包含多個橫向分離之半導體晶粒堆疊(例如，各具有四個晶粒之兩個堆疊、各具有八個晶粒之兩個堆疊、各具有四個晶粒之四個堆疊等)，其中各堆疊中之可用ESD電路並非全部電耦合至一主動電路。在另一實施例中，一半導體裝置總成可包含一單一半導體晶粒堆疊，其中堆疊中之晶粒子組單獨連接至基板(例如，一疊瓦堆疊，其中八個晶粒分組為電耦合至基板之一第一子組，其中第一子組中之可用晶粒並非全部具有電耦合ESD電路，且前八個晶粒上方之另外八個晶粒(具有與第一子組相反之一疊瓦偏移方向)分組為電耦合至基板之一第二子組(與第一子組分離)，其中第二子組中之可用晶粒並非全部具有電耦合ESD電路等)。
上文參考圖3至圖11描述之半導體裝置總成之任一者可併入至大量更大及/或更複雜系統之任一者中，該等系統之一代表性實例係圖12中示意性展示之系統1200。系統1200可包含一半導體裝置總成1202、一電源1204、一驅動器1206、一處理器1208及/或其他子系統或組件1210。半導體裝置總成1202可包含大體上類似於上文參考圖3至圖11描述之半導體裝置之構件之構件。所得系統1200可執行多種功能之任一者，諸如記憶體儲存、資料處理及/或其他適合功能。因此，代表性系統1200可包含(但不限於)手持式裝置(例如，行動電話、平板電腦、數位閱讀器及數位音訊播放器)、電腦、車輛、設備及其他產品。系統1200之組件可容置於一單一單元中或分佈遍及多個、互連單元(例如，透過一通信網路)。系統1200之組件亦可包含遠端裝置及多種電腦可讀媒體之任一者。
圖13係繪示製造一半導體裝置之一方法之一流程圖。該方法包含提供包含複數個半導體晶粒之一晶圓(方塊1310)。複數個半導體晶粒之各者包含：一第一接觸墊，其電耦合至半導體晶粒上之一第一電路，該第一電路包含至少一個主動電路元件；及一第二接觸墊，其電耦合至半導體晶粒上之一第二電路，該第二電路僅包含被動電路元件。該方法可進一步包含探測複數個未單粒化半導體晶粒之至少一者之第一電路以判定複數個半導體晶粒之一封裝密度(方塊1320)。該方法可進一步包含針對複數個半導體晶粒之各者電鍍將第一接觸墊之至少一部分電耦合至第二接觸墊之至少一部分之一電鍍墊(方塊1330)。電鍍可至少部分基於所判定封裝密度。該方法可進一步包含從晶圓單粒化複數個半導體晶粒(方塊1340)。在單粒化之前，該方法可進一步包含至少部分基於所判定封裝密度薄化晶圓(例如，其中分組用於較高封裝密度之晶粒可比分組用於較低封裝密度之晶粒薄化更多)。
根據上文，將瞭解，已出於繪示目的在本文中描述本發明之特定實施例，但可在不偏離本發明之範疇之情況下作出各種修改。因此，本發明除如藉由隨附發明申請專利範圍限制外並不受限。
100‧‧‧半導體裝置總成
101‧‧‧基板
102‧‧‧半導體晶粒
103‧‧‧半導體晶粒
121‧‧‧基板接觸件
122‧‧‧接觸墊
123‧‧‧接觸墊
131‧‧‧線接合
132‧‧‧線接合
151‧‧‧焊球
152‧‧‧通孔
162‧‧‧電路
163‧‧‧電路
170‧‧‧囊封劑
200‧‧‧半導體裝置總成
201‧‧‧基板
202‧‧‧半導體晶粒
211‧‧‧接觸墊
212‧‧‧接觸墊
221‧‧‧基板接觸件
222‧‧‧基板接觸件
230‧‧‧線接合
300‧‧‧半導體裝置
311‧‧‧第一接觸墊
312‧‧‧第二接觸墊
313‧‧‧第三接觸墊
314‧‧‧第四接觸墊
371‧‧‧第一電路/驅動器電路
372‧‧‧第二電路
373‧‧‧第三電路/驅動器電路
374‧‧‧第四電路
400‧‧‧半導體裝置總成
401‧‧‧基板
402‧‧‧半導體晶粒/下部半導體晶粒
403‧‧‧半導體晶粒/上部半導體晶粒
411‧‧‧第一接觸墊
412‧‧‧第二接觸墊
413‧‧‧第三接觸墊
414‧‧‧第四接觸墊
421‧‧‧第一基板接觸件
422‧‧‧第二基板接觸件
430‧‧‧線接合
440‧‧‧電鍍墊
500‧‧‧半導體裝置
511‧‧‧第一接觸墊
512‧‧‧第二接觸墊
513‧‧‧第三接觸墊
514‧‧‧第四接觸墊
515‧‧‧第五接觸墊
516‧‧‧第六接觸墊
571‧‧‧第一電路/驅動器電路
572‧‧‧第二電路
573‧‧‧第三電路
574‧‧‧第四電路/驅動器電路
575‧‧‧第五電路
576‧‧‧第六電路
600‧‧‧半導體裝置總成
601‧‧‧基板
602‧‧‧半導體晶粒/下部半導體晶粒
603‧‧‧半導體晶粒/上部半導體晶粒
611‧‧‧第一接觸墊
612‧‧‧第二接觸墊
613‧‧‧第三接觸墊
614‧‧‧第四接觸墊
615‧‧‧第五接觸墊
616‧‧‧第六接觸墊
621‧‧‧第一基板接觸件
622‧‧‧第二基板接觸件
630‧‧‧線接合
640‧‧‧第一電鍍墊
642‧‧‧第二電鍍墊
700‧‧‧半導體裝置總成
701‧‧‧基板
702‧‧‧半導體晶粒
703‧‧‧半導體晶粒
704‧‧‧半導體晶粒
705‧‧‧半導體晶粒
711‧‧‧第一接觸墊
712‧‧‧第二接觸墊
713‧‧‧第三接觸墊
714‧‧‧第四接觸墊
721‧‧‧第一基板接觸件
722‧‧‧第二基板接觸件
730‧‧‧線接合
740‧‧‧電鍍墊
800‧‧‧半導體裝置總成
801‧‧‧基板
802‧‧‧半導體晶粒
803‧‧‧半導體晶粒
804‧‧‧半導體晶粒
805‧‧‧半導體晶粒
811‧‧‧第一接觸墊
812‧‧‧第二接觸墊
813‧‧‧第三接觸墊
814‧‧‧第四接觸墊
821‧‧‧第一基板接觸件
822‧‧‧第二基板接觸件
830‧‧‧線接合
840‧‧‧電鍍墊
842‧‧‧電鍍墊
900‧‧‧半導體裝置總成
901‧‧‧基板
902‧‧‧半導體晶粒
903‧‧‧半導體晶粒
904‧‧‧半導體晶粒
905‧‧‧半導體晶粒
911‧‧‧第一接觸墊
912‧‧‧第二接觸墊
913‧‧‧第三接觸墊
914‧‧‧第四接觸墊
921‧‧‧第一基板接觸件
922‧‧‧第二基板接觸件
930‧‧‧線接合
1001‧‧‧半導體裝置
1002‧‧‧接觸墊
1003‧‧‧接觸墊
1004‧‧‧焊球
1005‧‧‧鈍化或聚醯亞胺材料
1006‧‧‧小區域
1007‧‧‧晶種層
1008‧‧‧電鍍墊
1101‧‧‧半導體裝置
1102‧‧‧接觸墊
1103‧‧‧接觸墊
1104‧‧‧焊球
1105‧‧‧鈍化或聚醯亞胺材料
1106‧‧‧蝕刻停止材料
1107‧‧‧晶種層
1108‧‧‧電鍍墊
1200‧‧‧系統
1202‧‧‧半導體裝置總成
1204‧‧‧電源
1206‧‧‧驅動器
1208‧‧‧處理器
1210‧‧‧子系統或組件
1310‧‧‧方塊
1320‧‧‧方塊
1330‧‧‧方塊
1340‧‧‧方塊
圖1係一半導體裝置總成之一簡化部分橫截面視圖，其包含堆疊於一基板上之多個半導體晶粒。
圖2係一半導體裝置總成之一簡化示意圖。
圖3係根據本發明之一實施例之一半導體裝置之一簡化示意圖。
圖4係根據本發明之一實施例之一半導體裝置總成之一簡化示意圖。
圖5係根據本發明之一實施例之一半導體裝置之一簡化示意圖。
圖6至圖9係根據本發明之實施例之半導體裝置總成之簡化示意圖。
圖10及圖11係根據本發明之實施例之半導體裝置之簡化部分橫截面視圖。
圖12係展示包含根據本發明之一實施例組態之一半導體裝置總成之一系統之一示意圖。
圖13係繪示根據本發明之一實施例之製造一半導體裝置之一方法之一流程圖。

Claims (20)

  1. 一種半導體裝置總成，其包括： 一基板； 一晶粒，其經耦合至該基板，該晶粒包含： 一第一接觸墊，其經電耦合至該晶粒上之一第一電路，該第一電路包含至少一個主動電路元件， 一第二接觸墊，其經電耦合至該晶粒上之一第二電路，該第二電路僅包含被動電路元件，及 一電鍍墊，其將該第一接觸墊之至少一部分電耦合至該第二接觸墊之至少一部分； 其中該基板包含經電耦合至該晶粒上之該電鍍墊之一基板接觸件。
  2. 如請求項1之半導體裝置總成，其中該晶粒係一第一晶粒，該半導體裝置總成進一步包括： 一第二晶粒，其包含： 一第三接觸墊，其經電耦合至該第二晶粒上之一第三電路，該第三電路包含至少一第二主動電路元件，及 一第四接觸墊，其經電耦合至該第二晶粒上之一第四電路，該第四電路僅包含被動電路元件； 其中該基板接觸件經電耦合至該第二晶粒上之該第三接觸墊。
  3. 如請求項2之半導體裝置總成，其中該第二晶粒上之該第四接觸墊從該基板接觸件電斷開。
  4. 如請求項2之半導體裝置總成，其中該第二晶粒進一步包含將該第三接觸墊之至少一部分電耦合至該第四接觸墊之至少一部分之另一電鍍墊。
  5. 如請求項4之半導體裝置總成，其中該第一晶粒及該第二晶粒係相同晶粒，其中該第一晶粒上之該第一接觸墊對應於該第二晶粒上之該第三接觸墊，且該第一晶粒上之該第二接觸墊對應於該第二晶粒上之該第四接觸墊。
  6. 如請求項2之半導體裝置總成，其中該第一晶粒及該第二晶粒經堆疊於一疊瓦組態中。
  7. 如請求項1之半導體裝置總成，其中該第一晶粒進一步包含經電耦合至該第一晶粒上之一第五電路之一第五接觸墊，該第五電路僅包含被動電路元件，且其中該電鍍墊進一步將該第一接觸墊之至少該部分及該第二接觸墊之至少該部分電耦合至該第五接觸墊之至少一部分，使得該基板接觸件經電耦合至該第五接觸墊。
  8. 如請求項1之半導體裝置總成，其中該第一電路係一驅動器電路。
  9. 如請求項1之半導體裝置總成，其中該第二電路包含一或多個電容器以提供靜電放電(ESD)保護。
  10. 如請求項1之半導體裝置總成，其中該基板接觸件係藉由一線接合電耦合至該電鍍墊。
  11. 如請求項1之半導體裝置總成，其中晶粒係一NAND記憶體晶粒。
  12. 一種半導體裝置總成，其包括： 一基板，其包含一基板接觸件；及 複數個半導體晶粒，其等各包含： 一第一接觸墊，其經電耦合至該半導體晶粒上之一第一電路，該第一電路包含至少一個主動電路元件，及 一第二接觸墊，其經電耦合至該半導體晶粒上之一第二電路，該第二電路僅包含被動電路元件； 其中全部該複數個半導體晶粒之該等第一接觸墊經電耦合至該基板接觸件，且 其中該複數個半導體晶粒之至少一者進一步包含將該第一接觸墊之至少一部分電耦合至該第二接觸墊之至少一部分之一電鍍墊。
  13. 如請求項12之半導體裝置總成，其中該複數個半導體晶粒之各者之該第一電路係一驅動器電路。
  14. 如請求項12之半導體裝置總成，其中該複數個半導體晶粒之各者之該第二電路包含一或多個電容器以提供靜電放電(ESD)保護。
  15. 如請求項12之半導體裝置總成，其中該複數個半導體晶粒包括NAND記憶體晶粒。
  16. 如請求項12之半導體裝置總成，其中該複數個半導體晶粒包括兩個以上半導體晶粒。
  17. 一種製造一半導體裝置之方法，其包括： 提供包含複數個半導體晶粒之一晶圓，其中該複數個半導體晶粒之各者包含： 一第一接觸墊，其經電耦合至該半導體晶粒上之一第一電路，該第一電路包含至少一個主動電路元件，及 一第二接觸墊，其經電耦合至該半導體晶粒上之一第二電路，該第二電路僅包含被動電路元件； 針對該複數個半導體晶粒之各者，電鍍將該第一接觸墊之至少一部分經電耦合至該第二接觸墊之至少一部分之一電鍍墊；及 從該晶圓單粒化該複數個半導體晶粒。
  18. 如請求項17之方法，進一步包括： 在電鍍該電鍍墊之前，探測該複數個未單粒化半導體晶粒之至少一者之該第一電路以判定該複數個半導體晶粒之一封裝密度。
  19. 如請求項18之方法，其中該電鍍該電鍍墊係至少部分基於該所判定封裝密度。
  20. 如請求項18之方法，進一步包括： 至少部分基於該所判定封裝密度來薄化該晶圓。
TW107136282A 2017-11-13 2018-10-16 具有探針後可組態度之半導體裝置 TWI695457B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/811,579 2017-11-13
US15/811,579 US10283462B1 (en) 2017-11-13 2017-11-13 Semiconductor devices with post-probe configurability

Publications (2)

Publication Number Publication Date
TW201923989A true TW201923989A (zh) 2019-06-16
TWI695457B TWI695457B (zh) 2020-06-01

Family

ID=66333854

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107136282A TWI695457B (zh) 2017-11-13 2018-10-16 具有探針後可組態度之半導體裝置

Country Status (4)

Country Link
US (3) US10283462B1 (zh)
CN (1) CN111418062A (zh)
TW (1) TWI695457B (zh)
WO (1) WO2019094120A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10128229B1 (en) 2017-11-13 2018-11-13 Micron Technology, Inc. Semiconductor devices with package-level configurability
US10283462B1 (en) 2017-11-13 2019-05-07 Micron Technology, Inc. Semiconductor devices with post-probe configurability
US10483241B1 (en) * 2018-06-27 2019-11-19 Micron Technology, Inc. Semiconductor devices with through silicon vias and package-level configurability
US10867991B2 (en) 2018-12-27 2020-12-15 Micron Technology, Inc. Semiconductor devices with package-level configurability
US11908812B2 (en) 2020-12-17 2024-02-20 Micron Technology, Inc. Multi-die memory device with peak current reduction
US11848278B2 (en) * 2021-10-14 2023-12-19 Nanya Technology Corporation Package device comprising electrostatic discharge protection element

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7166495B2 (en) 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US5982018A (en) 1997-05-23 1999-11-09 Micron Technology, Inc. Thin film capacitor coupons for memory modules and multi-chip modules
US6448865B1 (en) * 1999-02-25 2002-09-10 Formfactor, Inc. Integrated circuit interconnect system
SG97938A1 (en) 2000-09-21 2003-08-20 Micron Technology Inc Method to prevent die attach adhesive contamination in stacked chips
US6972484B2 (en) * 2000-10-13 2005-12-06 Texas Instruments Incorporated Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface
JP3792635B2 (ja) 2001-12-14 2006-07-05 富士通株式会社 電子装置
JP2006135302A (ja) 2004-10-06 2006-05-25 Matsushita Electric Ind Co Ltd 半導体装置
US7737553B2 (en) 2004-10-06 2010-06-15 Panasonic Corporation Semiconductor device
CN1905177B (zh) 2005-07-29 2010-10-20 米辑电子股份有限公司 线路组件结构及其制作方法
US8154134B2 (en) 2008-05-12 2012-04-10 Texas Instruments Incorporated Packaged electronic devices with face-up die having TSV connection to leads and die pad
US8253230B2 (en) 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
JP2009295750A (ja) 2008-06-04 2009-12-17 Toshiba Corp 半導体装置
KR100997787B1 (ko) * 2008-06-30 2010-12-02 주식회사 하이닉스반도체 적층 반도체 패키지 및 이의 제조 방법
KR20120017564A (ko) 2010-08-19 2012-02-29 주식회사 하이닉스반도체 메모리 카드 및 그 제조방법
KR20120088013A (ko) 2010-09-20 2012-08-08 삼성전자주식회사 디커플링 반도체 커패시터를 포함하는 반도체 패키지
KR20130004783A (ko) 2011-07-04 2013-01-14 삼성전자주식회사 정전기 방전 보호회로를 포함하는 적층 반도체 장치 및 적층 반도체 장치의 제조 방법
US20130228867A1 (en) * 2012-03-02 2013-09-05 Kabushiki Kaisha Toshiba Semiconductor device protected from electrostatic discharge
US9030010B2 (en) 2012-09-20 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods
US8906743B2 (en) 2013-01-11 2014-12-09 Micron Technology, Inc. Semiconductor device with molded casing and package interconnect extending therethrough, and associated systems, devices, and methods
US9355892B2 (en) 2013-09-09 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure with active and passive devices in different tiers
US10103128B2 (en) 2013-10-04 2018-10-16 Mediatek Inc. Semiconductor package incorporating redistribution layer interposer
US9111846B1 (en) 2014-04-16 2015-08-18 Gloval Unichip Corp. Assembly structure for connecting multiple dies into a system-in-package chip and the method thereof
US9502369B2 (en) 2015-02-04 2016-11-22 Micron Technology, Inc. Semiconductor devices and packages
US20170025402A1 (en) * 2015-03-06 2017-01-26 Texas Instruments Incorporated Semiconductor esd protection circuit
US9786632B2 (en) 2015-07-30 2017-10-10 Mediatek Inc. Semiconductor package structure and method for forming the same
JP6531603B2 (ja) 2015-10-01 2019-06-19 富士通株式会社 電子部品、電子装置及び電子装置の製造方法
US10134720B1 (en) 2016-02-16 2018-11-20 Darryl G. Walker Package including a plurality of stacked semiconductor devices having area efficient ESD protection
US10727828B2 (en) * 2016-09-12 2020-07-28 Analog Devices, Inc. Input buffer
US10756720B2 (en) * 2016-10-17 2020-08-25 Infineon Technologies Ag Driver circuit for electronic switch
CN108695284A (zh) 2017-04-07 2018-10-23 晟碟信息科技（上海）有限公司 包括纵向集成半导体封装体组的半导体设备
US10319690B2 (en) 2017-04-28 2019-06-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10283462B1 (en) 2017-11-13 2019-05-07 Micron Technology, Inc. Semiconductor devices with post-probe configurability
US10128229B1 (en) 2017-11-13 2018-11-13 Micron Technology, Inc. Semiconductor devices with package-level configurability
US10535636B2 (en) 2017-11-15 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating passive devices in package structures
US10483241B1 (en) 2018-06-27 2019-11-19 Micron Technology, Inc. Semiconductor devices with through silicon vias and package-level configurability

Also Published As

Publication number Publication date
WO2019094120A1 (en) 2019-05-16
US20190273052A1 (en) 2019-09-05
US20190148314A1 (en) 2019-05-16
US10283462B1 (en) 2019-05-07
TWI695457B (zh) 2020-06-01
US10811372B2 (en) 2020-10-20
US10403585B2 (en) 2019-09-03
CN111418062A (zh) 2020-07-14

Similar Documents

Publication Publication Date Title
TWI695457B (zh) 具有探針後可組態度之半導體裝置
US11056467B2 (en) Semiconductor devices with through silicon vias and package-level configurability
US10971486B2 (en) Semiconductor package and method of manufacturing the semiconductor package
US11848323B2 (en) Semiconductor devices with package-level configurability
US20140084456A1 (en) Semiconductor packages, methods of manufacturing semiconductor packages, and systems including semiconductor packages
US20140246781A1 (en) Semiconductor device, method of forming a packaged chip device and chip package
CN115513190A (zh) 包含半导体裸片的多个瓦片式堆叠的半导体装置组合件
US11942455B2 (en) Stacked semiconductor dies for semiconductor device assemblies
US10867991B2 (en) Semiconductor devices with package-level configurability
US7847386B1 (en) Reduced size stacked semiconductor package and method of making the same
KR20160047841A (ko) 반도체 패키지
US20070252256A1 (en) Package-on-package structures
CN113053858A (zh) 具有扇出边沿的面对面半导体装置
US11562987B2 (en) Semiconductor devices with multiple substrates and die stacks
US20240072022A1 (en) Stacked capacitors for semiconductor devices and associated systems and methods