CN111418062A - 具有探针后可配置度的半导体装置 - Google Patents

具有探针后可配置度的半导体装置 Download PDF

Info

Publication number
CN111418062A
CN111418062A CN201880075965.3A CN201880075965A CN111418062A CN 111418062 A CN111418062 A CN 111418062A CN 201880075965 A CN201880075965 A CN 201880075965A CN 111418062 A CN111418062 A CN 111418062A
Authority
CN
China
Prior art keywords
die
circuit
contact pad
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201880075965.3A
Other languages
English (en)
Inventor
J·E·戴维斯
K·G·杜斯曼
J·P·莱特
W·L·博耶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN111418062A publication Critical patent/CN111418062A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/041—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00
    • H01L25/043—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

一种半导体装置组合件包含衬底及经耦合到所述衬底的裸片。所述裸片包含：第一接触垫，其经电耦合到所述裸片上的第一电路，所述第一电路包含至少一个有源电路元件；第二接触垫，其经电耦合到所述裸片上的第二电路，所述第二电路仅包含无源电路元件；及电镀垫，其将所述第一接触垫的至少一部分电耦合到所述第二接触垫的至少一部分。所述衬底包含经电耦合到所述裸片上的所述电镀垫的衬底接点。

Description

具有探针后可配置度的半导体装置
相关申请案的交叉参考
本申请案含有与詹姆斯E.戴维斯(James E.Davis)、约翰B.普赛(John B.Pusey)、尹志平(Zhiping Yin)及凯文G.杜斯曼(Kevin G.Duesman)的标题为“具有封装级可配置度的半导体装置(SEMICONDUCTOR DEVICES WITH PACKAGE-LEVEL CONFIG URABILITY)”的同时申请的美国专利申请案相关的标的物。相关申请案(其揭示内容以引用的方式并入本文中)经转让给美光科技有限公司(Micron Technology,Inc.)，且由代理人档案编号第010829-9242.US00号识别。
技术领域
本发明大体上涉及半导体装置，且更特定来说，涉及具有探针后可配置度的半导体装置。
背景技术
封装式半导体裸片(包含存储器芯片、微处理器芯片及成像器芯片)通常包含安装于衬底上且围封于塑料保护罩中或由导热盖覆盖的一或多个半导体裸片。裸片可包含有源电路(例如，提供功能构件，例如存储器单元、处理器电路及/或成像器装置)及/或无源构件(例如，电容器、电阻器等)以及电连接到所述电路的接合垫。接合垫可电连接到保护罩外部的端子以允许裸片连接到更高级电路。
例如，图1是半导体装置组合件100的简化部分横截面视图，其包含以叠瓦(shingled)方式堆叠于衬底101上且由囊封剂170覆盖的多个半导体裸片102及103。每一裸片包含一或多个接触垫(例如接触垫122及123)以提供到对应集成电路(例如电路162及163)的连接能力。接触垫122及123可通过线接合131及132(展示为呈菊链配置)连接到衬底接点121以经由焊球151(通过通孔152)提供到电路162及163的连接能力。
在一些半导体裸片的情况下，各种接合垫可连接到裸片中的多个电路。例如，在NAND存储器裸片中，单个接合垫可连接到有源驱动器电路及无源ESD保护电路(例如，包含一或多个电容器)两者。ESD保护电路可经设计以提供所要量的电容以保护单个有源驱动器电路。在包含具有并联连接的有源驱动器电路的多个此类NAND存储器裸片的半导体装置组合件中(例如，其中来自每一NAND存储器裸片的对应接合垫连接到相同外部端子)，由来自并联连接的每一裸片的ESD保护电路提供的过量电容可使装置性能降级。此可通过针对不同封装密度设计不同NAND存储器裸片而解决(例如，NAND存储器裸片经配置以单独封装，具有较少电容式ESD保护电路的不同NAND存储器裸片经配置以封装为两个的堆叠，具有甚至更少电容式ESD保护电路的又一NAND存储器裸片经配置以封装为四个的堆叠等)，但针对每一可能封装配置设计及制造多个不同半导体裸片是极其昂贵的。因此，需要可经配置为取决于封装裸片的配置而具有不同量的ESD保护的半导体裸片。
附图说明
图1是半导体装置组合件的简化部分横截面视图，其包含堆叠于衬底上的多个半导体裸片。
图2是半导体装置组合件的简化示意图。
图3是根据本发明的实施例的半导体装置的简化示意图。
图4是根据本发明的实施例的半导体装置组合件的简化示意图。
图5是根据本发明的实施例的半导体装置的简化示意图。
图6到9是根据本发明的实施例的半导体装置组合件的简化示意图。
图10及11是根据本发明的实施例的半导体装置的简化部分横截面视图。
图12是展示包含根据本发明的实施例配置的半导体装置组合件的系统的示意图。
图13是说明根据本发明的实施例的制造半导体装置的方法的流程图。
具体实施方式
在以下描述中，论述许多特定细节以提供对本发明的实施例的透彻且实现描述。然而，相关领域的技术人员将认识到，可在不具有特定细节中的一或多者的情况下实践本发明。在其它例子中，未展示或未详细描述通常与半导体装置相关联的众所周知的结构或操作以避免模糊本发明的其它方面。一般来说，应理解，除本文中揭示的那些特定实施例以外的各种其它装置、系统及方法可在本发明的范围内。
如上文论述，当具有连接到与有源电路(例如，驱动器电路)相同的接合垫的ESD保护电路的半导体裸片以不同封装密度连接在一起时，无法针对每一封装密度优化由ESD保护电路提供的电容量。因此，根据本发明的半导体装置的若干实施例可提供所提供电容的封装级可配置度以克服此挑战。
本发明的若干实施例涉及半导体装置组合件，其包含衬底及耦合到所述衬底的裸片。所述裸片包含：第一接触垫，其电耦合到所述裸片上的第一电路，所述第一电路包含至少一个有源电路元件；第二接触垫，其电耦合到所述裸片上的第二电路，所述第二电路仅包含无源电路元件；及电镀垫，其将所述第一接触垫的至少一部分电耦合到所述第二接触垫的至少一部分。所述衬底包含电耦合到所述裸片上的所述电镀垫的衬底接点。所述半导体装置组合件可进一步包含第二裸片，所述第二裸片包含：第三接触垫，其电耦合到所述第二裸片上的第三电路，所述第三电路包含至少一第二有源电路元件；及第四接触垫，其电耦合到所述第二裸片上的第四电路，所述第四电路仅包含无源电路元件。所述衬底接点可电耦合到所述第二裸片上的所述第三接触垫，且可从所述第二裸片上的所述第四接触垫电断开或通过将所述第三接触垫的至少一部分电耦合到所述第四接触垫的至少一部分的另一电镀垫电耦合到所述第二裸片上的所述第四接触垫。
下文描述半导体装置的若干实施例的特定细节。术语“半导体装置”通常指包含半导体材料的固态装置。半导体装置可包含例如半导体衬底、晶片或从晶片或衬底单粒化的裸片。贯穿本发明，通常在半导体裸片的上下文中描述半导体装置；然而，半导体装置不限于半导体裸片。
术语“半导体装置封装”可指具有经并入到共同封装中的一或多个半导体装置的布置。半导体封装可包含部分或完全囊封至少一个半导体装置的外壳或壳体。半导体装置封装还可包含承载一或多个半导体装置且经附接到壳体或以其它方式被并入到壳体中的中介衬底。术语“半导体装置组合件”可指一或多个半导体装置、半导体装置封装及/或衬底(例如，中介层、支撑件或其它适合衬底)的组合件。例如，可以离散封装形式、条状或矩阵形式及/或晶片面板形式来制造半导体装置组合件。如本文中使用，术语“垂直”、“横向”、“上部”及“下部”可指半导体装置或装置组合件中的构件鉴于图中展示的定向的相对方向或位置。例如，“上部”及“最上部”可指分别经定位成比另一构件或相同构件的部分更靠近一页的顶部或最靠近页的顶部的构件。然而，这些术语应广泛地解释为包含具有其它定向的半导体装置，例如倒置或倾斜定向，其中顶部/底部、在……上/在……下、在……上方/在……下方、向上/向下及左/右可随定向而互换。
图2是半导体装置组合件200的简化示意图，其包含经耦合到衬底201的半导体裸片202。裸片包含接触垫，例如接触垫211及212，其各自经连接到具有有源组件的集成电路(示意性地经说明为驱动器(DRV)电路)及具有无源组件的集成电路(示意性地经说明为静电放电(ESD)保护电路)两者。接触垫211及212通过线接合230电耦合到衬底接点221及222。如参考图2可见，如果半导体裸片202已经配置为具有适合于为单个驱动器电路提供ESD保护的电容量，那么将另一此半导体裸片添加到组合件200可能会不合意地增加衬底接点221及222所“看见”的电容。
为解决此问题，本发明的实施例可提供半导体裸片，其中有源电路及经配置以为其提供ESD保护的无源电路经连接到单独接触垫，使得可提供所要量的电容而与封装组合件中提供的裸片数目无关。例如，图3是根据本发明的实施例的半导体装置300的简化示意图。半导体装置300包含多个接触垫(例如第一接触垫311到第四接触垫314)以提供到半导体装置300中的电路的连接能力。例如，第一接触垫311提供到具有有源组件的第一电路371(例如，驱动器电路)的连接能力，且第二接触垫312提供到具有无源组件的第二电路372(例如，ESD保护电路)的连接能力。类似地，第三接触垫313提供到具有有源组件的第三电路373(例如，驱动器电路)的连接能力，且第四接触垫314提供到具有无源组件的第四电路374(例如，ESD保护电路)的连接能力。通过为每一无源电路提供专用接触垫，半导体装置300利用多个相同半导体裸片来实现不同封装密度，同时提供所要量的ESD保护，且不具有(例如)导致驱动器电路371及373消耗过量电力的过量电容。
此可参考图4更好地理解，图4是根据本发明的实施例的半导体装置组合件400的简化示意图。组合件400包含衬底401及两个半导体裸片402及403(例如，相同半导体裸片)。如同上文图3中说明的半导体装置300，每一半导体裸片402及403包含多个接触垫，例如第一接触垫411到第四接触垫414，其各自提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接能力。由于每一ESD保护电路具备专用接触垫，所以组合件400可经配置为具有针对每一驱动器电路的所要量的ESD保护。
如参考图4可见，衬底401包含两个衬底接点421及422。第一衬底接点421(例如，通过线接合430)连接到电镀垫440，所述电镀垫440将下部半导体裸片402的第一接触垫411(对应于驱动器电路)的至少一部分连接到第二接触垫412(对应于ESD保护电路)的至少一部分。电镀垫440进一步通过另一线接合连接到上部半导体裸片403的仅第一接触垫411。以此方式，第一衬底接点421电耦合到下部半导体裸片402的第一接触垫411及第二接触垫412两者及上部半导体裸片403的仅第一接触垫411。类似地，第二衬底接点422(例如，通过线接合430)连接到组合件400中的每一半导体裸片402及403的第三接触垫413(对应于驱动器电路)，但连接到组合件400中的仅一个半导体裸片402的第四接触垫414(对应于ESD保护电路)。通过使上部半导体裸片403上的第二接触垫412及第四接触垫414(对应于ESD保护电路)从衬底接点421及422电断开(例如，通过不用电镀垫(例如下部半导体裸片402上的电镀垫440)将这些垫连接到对应驱动器垫411及413)，每一衬底接点421及422所连接的电路的电容小于在连接来自组合件400中的每一裸片的ESD保护电路的情况。
根据本发明的一个方面，可使用晶片级重布层(RDL)制造技术(例如，在裸片已从其面板或晶片单粒化之前)将电镀垫440提供于半导体裸片(例如下部半导体裸片402)的第一接触垫411及第二接触垫412上方。电镀垫的制造可在探针操作之后执行，其中已测试且分组晶片或面板上的裸片以确定其最终封装密度。例如，在探测操作中确定为能够具有较高操作速度的裸片可经分组用于较高封装密度(例如，双装置封装(DDP)、四装置封装(QDP)或甚至更高密度)，而在探测操作中确定为能够具有较低操作速度的裸片可经分组用于较低封装密度(例如，单装置封装(SDP)密度)。基于晶片中的裸片待组装的所确定封装密度，可(例如，在预定用于SDP密度的全部裸片中、在预定用于DDP或QDP密度的下部裸片中)包含或(例如，在预定用于DDP或QDP密度的上部裸片中或在预定用于更高封装密度的全部裸片中)省略电镀垫。在探针操作之后将ESD电路连接到驱动器电路的能力允许对用于多装置封装中的其它相同裸片设计执行有效晶片级操作。
尽管图4已经描述及说明为包含多个相同半导体裸片，但在本发明的其它实施例中，具有不同类型的裸片的半导体装置组合件可具备类似特征。例如，在一个实施例中，半导体装置组合件可包含逻辑裸片及存储器裸片，其一者或两者可包含用于将无源电路连接为所要探针后的离散接触垫。此外，尽管图4已经描述及说明为包含具有两个驱动器电路的半导体裸片，但所属领域的技术人员将容易地明白，此实施例仅为一个实例，且还可提供具有不同数目个驱动器电路的半导体裸片。此外，图4已经描述及说明为与用于驱动器电路的接触垫分开地提供用于ESD保护电路的接触垫，但在其它实施例中，可提供具有除驱动器以外的其它有源元件的电路，且同样可提供仅包含无源组件(例如，电阻器、电容器、电感器等)的其它电路。
尽管在前述实例中已将半导体裸片描述及说明为包含对应于每一驱动器电路的单个ESD保护电路，但在本发明的其它实施例中，可通过包含具有对应于半导体裸片上的每一驱动器电路的专用接触垫的多个ESD保护电路而提供额外可配置度。例如，图5是根据本发明的实施例的半导体装置500的简化示意图。半导体装置500包含多个接触垫(例如第一接触垫511到第六接触垫516)以提供到半导体装置500中的电路的连接能力。例如，第一接触垫511提供到具有有源组件的第一电路571(例如，驱动器电路)的连接能力，且第二接触垫512及第三接触垫513分别提供到仅包含无源组件的第二电路572及第三电路573(例如，ESD保护电路)的连接能力。类似地，第四接触垫514提供到具有有源组件的第四电路574(例如，驱动器电路)的连接能力，且第五接触垫515及第六接触垫516分别提供到仅包含无源组件的第五电路575及第六电路576(例如，ESD保护电路)的连接能力。通过为每一有源电路提供多个对应无源电路(各自具有其自身专用接触垫)，半导体装置500利用多个相同半导体裸片实现不同封装密度，同时提供所要量的ESD保护而不具有例如导致驱动器电路571及574消耗过量电力的过量电容。
此可参考图6更好地理解，图6是根据本发明的实施例的半导体装置组合件600的简化示意图。组合件600包含衬底601及两个半导体裸片602及603(例如，相同半导体裸片)。如同上文图5中说明的半导体装置500，每一半导体裸片602及603包含多个接触垫，例如第一接触垫611到第六接触垫616，其各自提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接能力。由于每一ESD保护电路具备专用接触垫，所以组合件600可经配置为具有针对每一驱动器电路的所要量的ESD保护。
如参考图6可见，衬底601包含两个衬底接点621及622。第一衬底接点621(例如，通过线接合630)连接到第一电镀垫640，所述第一电镀垫640将下部半导体裸片602的第一接触垫611(对应于驱动器电路)的至少一部分连接到第二接触垫612(对应于ESD保护电路)的至少一部分及第三接触垫613(对应于另一ESD保护电路)的至少一部分。第一电镀垫640进一步通过另一线接合连接到上部半导体裸片603的第二电镀垫642，所述第二电镀垫642连接上部半导体裸片603的第一接触垫611及第二接触垫612(但并非第三接触垫613)的至少一部分。以此方式，第一衬底接点621电耦合到下部半导体裸片602的第一、第二及第三接触垫611到613及上部半导体裸片的仅第一接触垫611及第二接触垫612。类似地，第二衬底接点622连接到组合件600中的每一半导体裸片602及603的第四接触垫614(对应于驱动器电路)，且连接到组合件600中的每一半导体裸片602及603的第五接触垫615(对应于ESD保护电路)，但连接到组合件600中的仅一个半导体裸片602的第六接触垫616(对应于另一ESD保护电路)。通过使上部半导体裸片603上的第三接触垫613及第六接触垫616(对应于ESD保护电路)从衬底接点621及622电断开，每一衬底接点621及622所连接的电路的电容小于在连接来自组合件600中的每一裸片的ESD保护电路的情况下的电容。
尽管在前述实施例中已说明及描述具有两个半导体裸片的半导体装置组合件，但是在本发明的其它实施例中，半导体装置组合件可包含不同数目个裸片。例如，图7是根据本发明的实施例的包含四个半导体裸片的半导体装置组合件700的简化示意图。组合件700包含衬底701及四个半导体裸片702到705(例如，相同半导体裸片)。如同上文图3中说明的半导体装置300，每一半导体裸片702到705包含多个接触垫，例如第一接触垫711到第四接触垫714，其各自提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接能力。由于每一ESD保护电路具备专用接触垫，所以组合件700可经配置为具有针对每一驱动器电路的所要量的ESD保护。
如参考图7可见，衬底701包含两个衬底接点721及722。第一衬底接点721(例如，通过线接合730)连接到电镀垫770，所述电镀垫770将第一半导体裸片702的第一接触垫711(对应于驱动器电路)的至少一部分连接到第二接触垫712(对应于ESD保护电路)的至少一部分。电镀垫740进一步通过额外线接合连接到组合件700中的其它三个裸片703到705的仅第一接触垫711。以此方式，第一衬底接点721经电耦合到第一半导体裸片702的第一接触垫711及第二接触垫712两者，以及组合件700中的其它半导体裸片703到705的仅第一接触垫711。类似地，第二衬底接点722(例如，通过线接合730)连接到组合件700中的每一半导体裸片702到705的第三接触垫713(对应于驱动器电路)，但连接到组合件700中的三个半导体裸片703到705的第四接触垫714(对应于ESD保护电路)。通过使三个半导体裸片703到705上的第二接触垫712及第四接触垫714(对应于ESD保护电路)从衬底接点721及722电断开，每一衬底接点721及722所连接的电路的电容小于在连接来自组合件700中的每一裸片的ESD保护电路的情况下的电容。
尽管在图7中说明的实施例中，组合件中的仅一个裸片的ESD保护电路经连接到衬底接点，但在其它实施例中，半导体装置组合件可包含具有经连接到其的(若干)衬底接点的ESD保护电路的多个裸片。例如，图8是根据本发明的实施例的半导体装置组合件800的简化示意图。组合件800包含衬底801及四个半导体裸片802到805(例如，相同半导体裸片)，每一半导体裸片包含多个接触垫(例如第一接触垫811到第四接触垫814)，以提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接能力。
如参考图8可见，衬底801包含两个衬底接点821及822。第一衬底接点821(例如，通过线接合830)连接到组合件800中的每一半导体裸片802到805的第一接触垫811(对应于驱动器电路)，但(例如，通过电镀垫840及842)连接到组合件800中的仅两个半导体裸片802及803的第二接触垫812(对应于ESD保护电路)。类似地，第二衬底接点822(例如，通过线接合830)连接到组合件800中的每一半导体裸片802到805的第三接触垫813(对应于驱动器电路)，但(例如，通过电镀垫840及842)连接到组合件800中的仅两个半导体裸片802及803的第四接触垫814(对应于ESD保护电路)。通过使两个半导体裸片804及805上的第二接触垫812及第四接触垫814(对应于ESD保护电路)从衬底接点821及822电断开，每一衬底接点821及822所连接的电路的电容小于在连接来自组合件800中的每一裸片的ESD保护电路的情况下的电容。
尽管在前述实施例中已说明其中至少一个裸片包含经附接ESD保护电路的半导体装置组合件，但在本发明的其它实施例中，半导体装置组合件可包含多个裸片，其全部包含未连接的ESD保护电路(例如，依赖于多个驱动器电路的固有电容，使得无需额外电容)。例如，图9是根据本发明的实施例的半导体装置组合件900的简化示意图。组合件900包含衬底901及四个半导体裸片902到905(例如，相同半导体裸片)，每一半导体裸片包含多个接触垫(例如第一接触垫911到第四接触垫914)，以提供到具有有源组件的电路(例如，驱动器电路)或具有无源组件的电路(例如，ESD保护电路)的连接能力。
如参考图9可见，衬底901包含两个衬底接点921及922。第一衬底接点921(例如，通过线接合930)连接到组合件900中的每一半导体裸片902到905的第一接触垫911(对应于驱动器电路)，但(例如，归因于缺少电镀垫)不连接到组合件900中的半导体裸片902到905中的任一者的第二接触垫912(对应于ESD保护电路)。类似地，第二衬底接点922(例如，通过线接合930)连接到组合件900中的每一半导体裸片902到905的第三接触垫913(对应于驱动器电路)，但(例如，归因于缺少电镀垫)不连接到组合件900中的半导体裸片902到905中的任一者的第四接触垫914(对应于ESD保护电路)。通过使全部半导体裸片902到905上的第二接触垫912及第四接触垫914(对应于ESD保护电路)从衬底接点921及922电断开，每一衬底接点921及922所连接的电路的电容小于在连接来自组合件900中的裸片中的任一者的ESD保护电路的情况下的电容。
尽管在前述实例实施例中，半导体裸片经描述为包含可任选地连接以增加驱动器电路的电容的多个离散接触垫，但本发明还适用于其它电路设计。就此来说，本发明的其它实施例可为半导体裸片提供多个接触垫以任选地连接任何数目个不同电路，具有除ESD保护电路及驱动器电路以外或代替其的任何所要功能。
根据本发明的各种实施例，可形成电镀垫以用各种方式连接半导体裸片上的离散接触垫。例如，图10说明根据本发明的实施例的半导体装置的简化部分横截面视图。在图10中说明的半导体装置1001中，接触垫1002及1003(例如，连接到半导体装置中的离散电路，例如驱动器电路及ESD保护电路)提供于钝化或聚酰亚胺材料1005的层下方，且因此由钝化或聚酰亚胺材料的小区域1006分离。为形成电连接这些接触垫1002及1003中的每一者的至少一部分的电镀垫1008，可在每一接触垫上形成晶种层1007(例如，Ti材料或类似物)，且可执行电镀操作以在每一接触垫1002及1003上的晶种层1007上方将材料(例如，Cu、Al或类似物)电镀到大于钝化或聚酰亚胺材料的小区域1006的高度的高度。单个焊球1004可接着用于(例如，通过电镀垫1008)将接触垫1002及1003两者连接到另一半导体装置或衬底(例如，用线接合)。
通过进一步实例，图11说明根据本发明的实施例的另一半导体装置的简化部分横截面视图。在图11中说明的半导体装置1101中，接触垫1102及1103提供于钝化或聚酰亚胺材料1105的层下方，但已进行额外工艺步骤(例如，屏蔽及蚀刻)以从接触垫1102及1103之间消除钝化或聚酰亚胺材料1105(例如，通过在接触垫1102及1103之间的区域下方包含蚀刻停止材料1106以允许从其之间蚀刻掉钝化或聚酰亚胺材料1105)。此布置促进(例如，在每一接触垫1102及1103上的晶种层1107上方)制造单个电镀垫1108，其中顶表面大体上与钝化或聚酰亚胺材料1105的顶表面共面或低于所述顶表面(例如，借此不促成半导体装置1100的增加封装高度)。单个焊球1104可接着用于(例如，通过电镀垫1108)将接触垫1102及1103两者连接到另一半导体装置或衬底(例如，用线接合)。
尽管在前述实例中已将半导体装置组合件描述为包含单个半导体裸片堆叠，但在本发明的其它实施例中，半导体装置组合件可包含多个半导体裸片堆叠，其中可任选地经由专用接触垫连接无源电路。例如，在本发明的一个实施例中，半导体装置组合件可包含多个横向分离的半导体裸片堆叠(例如，各自具有四个裸片的两个堆叠、各自具有八个裸片的两个堆叠、各自具有四个裸片的四个堆叠等)，其中每一堆叠中的可用ESD电路并非全部电耦合到有源电路。在另一实施例中，半导体装置组合件可包含单个半导体裸片堆叠，其中堆叠中的裸片子组单独连接到衬底(例如，叠瓦堆叠，其中八个裸片分组为电耦合到衬底的第一子组，其中第一子组中的可用裸片并非全部具有电耦合ESD电路，且前八个裸片上方的另外八个裸片(具有与第一子组相反的叠瓦偏移方向)分组为电耦合到衬底的第二子组(与第一子组分离)，其中第二子组中的可用裸片并非全部具有电耦合ESD电路等)。
上文参考图3到11描述的半导体装置组合件中的任一者可并入到大量更大及/或更复杂系统中的任一者中，所述系统的代表性实例是图12中示意性展示的系统1200。系统1200可包含半导体装置组合件1202、电源1204、驱动器1206、处理器1208及/或其它子系统或组件1210。半导体装置组合件1202可包含大体上类似于上文参考图3到11描述的半导体装置的构件的构件。所得系统1200可执行多种功能中的任一者，例如存储器存储、数据处理及/或其它适合功能。因此，代表性系统1200可包含(但不限于)手持式装置(例如，移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机、车辆、设备及其它产品。系统1200的组件可容置于单个单元中或分布遍及多个、互连单元(例如，通过通信网络)。系统1200的组件还可包含远程装置及多种计算机可读媒体中的任一者。
图13是说明制造半导体装置的方法的流程图。所述方法包含提供包含多个半导体裸片的晶片(框1310)。多个半导体裸片中的每一者包含：第一接触垫，其电耦合到半导体裸片上的第一电路，所述第一电路包含至少一个有源电路元件；及第二接触垫，其电耦合到半导体裸片上的第二电路，所述第二电路仅包含无源电路元件。所述方法可进一步包含探测多个未单粒化半导体裸片中的至少一者的第一电路以确定多个半导体裸片的封装密度(框1320)。所述方法可进一步包含针对多个半导体裸片中的每一者电镀将第一接触垫的至少一部分电耦合到第二接触垫的至少一部分的电镀垫(框1330)。电镀可至少部分基于所确定封装密度。所述方法可进一步包含从晶片单粒化多个半导体裸片(框1340)。在单粒化之前，所述方法可进一步包含至少部分基于所确定封装密度薄化晶片(例如，其中分组用于较高封装密度的裸片可比分组用于较低封装密度的裸片薄化更多)。
根据上文，将了解，已出于说明目的在本文中描述本发明的特定实施例，但可在不偏离本发明的范围的情况下作出各种修改。因此，本发明除由所附权利要求书外限制外并不受限。

Claims (20)

1.一种半导体装置组合件，其包括：
衬底；
裸片，其经耦合到所述衬底，所述裸片包含：
第一接触垫，其经电耦合到所述裸片上的第一电路，所述第一电路包含至少一个有源电路元件，
第二接触垫，其经电耦合到所述裸片上的第二电路，所述第二电路仅包含无源电路元件，及
电镀垫，其将所述第一接触垫的至少一部分电耦合到所述第二接触垫的至少一部分；
其中所述衬底包含经电耦合到所述裸片上的所述电镀垫的衬底接点。
2.根据权利要求1所述的半导体装置组合件，其中所述裸片是第一裸片，所述半导体装置组合件进一步包括：
第二裸片，其包含：
第三接触垫，其经电耦合到所述第二裸片上的第三电路，所述第三电路包含至少一第二有源电路元件，及
第四接触垫，其经电耦合到所述第二裸片上的第四电路，所述第四电路仅包含无源电路元件；
其中所述衬底接点经电耦合到所述第二裸片上的所述第三接触垫。
3.根据权利要求2所述的半导体装置组合件，其中所述第二裸片上的所述第四接触垫从所述衬底接点电断开。
4.根据权利要求2所述的半导体装置组合件，其中所述第二裸片进一步包含将所述第三接触垫的至少一部分电耦合到所述第四接触垫的至少一部分的另一电镀垫。
5.根据权利要求4所述的半导体装置组合件，其中所述第一及第二裸片是相同裸片，其中所述第一裸片上的所述第一接触垫对应于所述第二裸片上的所述第三接触垫，且所述第一裸片上的所述第二接触垫对应于所述第二裸片上的所述第四接触垫。
6.根据权利要求2所述的半导体装置组合件，其中所述第一及第二裸片以叠瓦配置堆叠。
7.根据权利要求1所述的半导体装置组合件，其中所述第一裸片进一步包含经电耦合到所述第一裸片上的第五电路的第五接触垫，所述第五电路仅包含无源电路元件，且其中所述电镀垫进一步将所述第一接触垫的至少所述部分及所述第二接触垫的至少所述部分电耦合到所述第五接触垫的至少一部分，使得所述衬底接点经电耦合到所述第五接触垫。
8.根据权利要求1所述的半导体装置组合件，其中所述第一电路是驱动器电路。
9.根据权利要求1所述的半导体装置组合件，其中所述第二电路包含一或多个电容器以提供静电放电ESD保护。
10.根据权利要求1所述的半导体装置组合件，其中所述衬底接点通过线接合电耦合到所述电镀垫。
11.根据权利要求1所述的半导体装置组合件，其中裸片是NAND存储器裸片。
12.一种半导体装置组合件，其包括：
衬底，其包含衬底接点；及
多个半导体裸片，其各自包含：
第一接触垫，其经电耦合到所述半导体裸片上的第一电路，所述第一电路包含至少一个有源电路元件，及
第二接触垫，其经电耦合到所述半导体裸片上的第二电路，所述第二电路仅包含无源电路元件；
其中全部所述多个半导体裸片的所述第一接触垫经电耦合到所述衬底接点，且
其中所述多个半导体裸片中的至少一者进一步包含将所述第一接触垫的至少一部分电耦合到所述第二接触垫的至少一部分的电镀垫。
13.根据权利要求12所述的半导体装置组合件，其中所述多个半导体裸片中的每一者的所述第一电路是驱动器电路。
14.根据权利要求12所述的半导体装置组合件，其中所述多个半导体裸片中的每一者的所述第二电路包含一或多个电容器以提供静电放电ESD保护。
15.根据权利要求12所述的半导体装置组合件，其中所述多个半导体裸片包括NAND存储器裸片。
16.根据权利要求12所述的半导体装置组合件，其中所述多个半导体裸片包括多于两个半导体裸片。
17.一种制造半导体装置的方法，其包括：
提供包含多个半导体裸片的晶片，其中所述多个半导体裸片中的每一者包含：
第一接触垫，其经电耦合到所述半导体裸片上的第一电路，所述第一电路包含至少一个有源电路元件，及
第二接触垫，其经电耦合到所述半导体裸片上的第二电路，所述第二电路仅包含无源电路元件；
针对所述多个半导体裸片中的每一者，电镀将所述第一接触垫的至少一部分经电耦合到所述第二接触垫的至少一部分的电镀垫；及
从所述晶片单粒化所述多个半导体裸片。
18.根据权利要求17所述的方法，其进一步包括：
在电镀所述电镀垫之前，探测所述多个未单粒化半导体裸片中的至少一者的所述第一电路以确定所述多个半导体裸片的封装密度。
19.根据权利要求18所述的方法，其中所述电镀所述电镀垫是至少部分基于所述所确定封装密度。
20.根据权利要求18所述的方法，其进一步包括：
至少部分基于所述所确定封装密度来薄化所述晶片。
CN201880075965.3A 2017-11-13 2018-10-02 具有探针后可配置度的半导体装置 Pending CN111418062A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/811,579 2017-11-13
US15/811,579 US10283462B1 (en) 2017-11-13 2017-11-13 Semiconductor devices with post-probe configurability
PCT/US2018/053862 WO2019094120A1 (en) 2017-11-13 2018-10-02 Semiconductor devices with post-probe configurability

Publications (1)

Publication Number Publication Date
CN111418062A true CN111418062A (zh) 2020-07-14

Family

ID=66333854

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880075965.3A Pending CN111418062A (zh) 2017-11-13 2018-10-02 具有探针后可配置度的半导体装置

Country Status (4)

Country Link
US (3) US10283462B1 (zh)
CN (1) CN111418062A (zh)
TW (1) TWI695457B (zh)
WO (1) WO2019094120A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10128229B1 (en) 2017-11-13 2018-11-13 Micron Technology, Inc. Semiconductor devices with package-level configurability
US10283462B1 (en) 2017-11-13 2019-05-07 Micron Technology, Inc. Semiconductor devices with post-probe configurability
US10483241B1 (en) * 2018-06-27 2019-11-19 Micron Technology, Inc. Semiconductor devices with through silicon vias and package-level configurability
US10867991B2 (en) 2018-12-27 2020-12-15 Micron Technology, Inc. Semiconductor devices with package-level configurability
US11908812B2 (en) 2020-12-17 2024-02-20 Micron Technology, Inc. Multi-die memory device with peak current reduction
US11848278B2 (en) * 2021-10-14 2023-12-19 Nanya Technology Corporation Package device comprising electrostatic discharge protection element

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040140860A1 (en) * 1999-02-25 2004-07-22 Formfactor, Inc. Integrated circuit interconnect system
US20130228867A1 (en) * 2012-03-02 2013-09-05 Kabushiki Kaisha Toshiba Semiconductor device protected from electrostatic discharge
US20150311094A1 (en) * 2014-04-16 2015-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Assembly structure for connecting multiple dies into a system-in-package chip and the method thereof

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7166495B2 (en) 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US5982018A (en) 1997-05-23 1999-11-09 Micron Technology, Inc. Thin film capacitor coupons for memory modules and multi-chip modules
SG97938A1 (en) 2000-09-21 2003-08-20 Micron Technology Inc Method to prevent die attach adhesive contamination in stacked chips
US6972484B2 (en) * 2000-10-13 2005-12-06 Texas Instruments Incorporated Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface
JP3792635B2 (ja) 2001-12-14 2006-07-05 富士通株式会社 電子装置
JP2006135302A (ja) 2004-10-06 2006-05-25 Matsushita Electric Ind Co Ltd 半導体装置
US7737553B2 (en) 2004-10-06 2010-06-15 Panasonic Corporation Semiconductor device
CN1905176B (zh) 2005-07-29 2010-10-20 米辑电子股份有限公司 线路组件结构及其制作方法
US8154134B2 (en) 2008-05-12 2012-04-10 Texas Instruments Incorporated Packaged electronic devices with face-up die having TSV connection to leads and die pad
US8253230B2 (en) 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
JP2009295750A (ja) 2008-06-04 2009-12-17 Toshiba Corp 半導体装置
KR100997787B1 (ko) * 2008-06-30 2010-12-02 주식회사 하이닉스반도체 적층 반도체 패키지 및 이의 제조 방법
KR20120017564A (ko) 2010-08-19 2012-02-29 주식회사 하이닉스반도체 메모리 카드 및 그 제조방법
KR20120088013A (ko) 2010-09-20 2012-08-08 삼성전자주식회사 디커플링 반도체 커패시터를 포함하는 반도체 패키지
KR20130004783A (ko) 2011-07-04 2013-01-14 삼성전자주식회사 정전기 방전 보호회로를 포함하는 적층 반도체 장치 및 적층 반도체 장치의 제조 방법
US9030010B2 (en) 2012-09-20 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods
US8906743B2 (en) 2013-01-11 2014-12-09 Micron Technology, Inc. Semiconductor device with molded casing and package interconnect extending therethrough, and associated systems, devices, and methods
US9355892B2 (en) 2013-09-09 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure with active and passive devices in different tiers
US10103128B2 (en) 2013-10-04 2018-10-16 Mediatek Inc. Semiconductor package incorporating redistribution layer interposer
US9502369B2 (en) 2015-02-04 2016-11-22 Micron Technology, Inc. Semiconductor devices and packages
US20170025402A1 (en) * 2015-03-06 2017-01-26 Texas Instruments Incorporated Semiconductor esd protection circuit
US9786632B2 (en) 2015-07-30 2017-10-10 Mediatek Inc. Semiconductor package structure and method for forming the same
JP6531603B2 (ja) 2015-10-01 2019-06-19 富士通株式会社 電子部品、電子装置及び電子装置の製造方法
US10134720B1 (en) 2016-02-16 2018-11-20 Darryl G. Walker Package including a plurality of stacked semiconductor devices having area efficient ESD protection
US10727828B2 (en) * 2016-09-12 2020-07-28 Analog Devices, Inc. Input buffer
US10756720B2 (en) * 2016-10-17 2020-08-25 Infineon Technologies Ag Driver circuit for electronic switch
CN108695284A (zh) 2017-04-07 2018-10-23 晟碟信息科技（上海）有限公司 包括纵向集成半导体封装体组的半导体设备
US10319690B2 (en) 2017-04-28 2019-06-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10283462B1 (en) 2017-11-13 2019-05-07 Micron Technology, Inc. Semiconductor devices with post-probe configurability
US10128229B1 (en) 2017-11-13 2018-11-13 Micron Technology, Inc. Semiconductor devices with package-level configurability
US10535636B2 (en) 2017-11-15 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating passive devices in package structures
US10483241B1 (en) 2018-06-27 2019-11-19 Micron Technology, Inc. Semiconductor devices with through silicon vias and package-level configurability

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040140860A1 (en) * 1999-02-25 2004-07-22 Formfactor, Inc. Integrated circuit interconnect system
US20130228867A1 (en) * 2012-03-02 2013-09-05 Kabushiki Kaisha Toshiba Semiconductor device protected from electrostatic discharge
US20150311094A1 (en) * 2014-04-16 2015-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Assembly structure for connecting multiple dies into a system-in-package chip and the method thereof

Also Published As

Publication number Publication date
US10403585B2 (en) 2019-09-03
US20190273052A1 (en) 2019-09-05
US10811372B2 (en) 2020-10-20
TWI695457B (zh) 2020-06-01
TW201923989A (zh) 2019-06-16
WO2019094120A1 (en) 2019-05-16
US10283462B1 (en) 2019-05-07
US20190148314A1 (en) 2019-05-16

Similar Documents

Publication Publication Date Title
US11056467B2 (en) Semiconductor devices with through silicon vias and package-level configurability
CN110914984B (zh) 具有封装级可配置性的半导体装置
CN111418062A (zh) 具有探针后可配置度的半导体装置
KR102592640B1 (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
US20060216868A1 (en) Package structure and fabrication thereof
US11239200B2 (en) Methods and systems for improving power delivery and signaling in stacked semiconductor devices
US20130320560A1 (en) Distributed on-chip decoupling apparatus and method using package interconnect
CN110692132B (zh) 具有环形中介件的半导体装置组合件
CN111384041B (zh) 半导体装置组合件及相关制造方法
US11942455B2 (en) Stacked semiconductor dies for semiconductor device assemblies
US7847386B1 (en) Reduced size stacked semiconductor package and method of making the same
US11056465B2 (en) Semiconductor package having singular wire bond on bonding pads
CN117637729A (zh) 具有共面互连结构的半导体装置组合件及其制造方法
CN117637693A (zh) 用于半导体装置的封装衬底
CN115224012A (zh) 具有多个衬底和裸片堆叠的半导体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination