CN117637693A - 用于半导体装置的封装衬底 - Google Patents
用于半导体装置的封装衬底 Download PDFInfo
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- CN117637693A CN117637693A CN202311077456.3A CN202311077456A CN117637693A CN 117637693 A CN117637693 A CN 117637693A CN 202311077456 A CN202311077456 A CN 202311077456A CN 117637693 A CN117637693 A CN 117637693A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 250
- 239000000758 substrate Substances 0.000 title claims abstract description 187
- 238000004806 packaging method and process Methods 0.000 title description 5
- 238000000034 method Methods 0.000 claims abstract description 42
- 230000008878 coupling Effects 0.000 claims description 59
- 238000010168 coupling process Methods 0.000 claims description 59
- 238000005859 coupling reaction Methods 0.000 claims description 59
- 229910000679 solder Inorganic materials 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000008393 encapsulating agent Substances 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- 238000004891 communication Methods 0.000 description 5
- 238000000429 assembly Methods 0.000 description 4
- 230000000712 assembly Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 but not limited to Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
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- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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Abstract
本文档公开了与用于半导体装置的封装衬底相关的技术、设备和系统。描述一种半导体装置组合件,其包含封装半导体装置,所述封装半导体装置具有耦合到封装级衬底的一或多个半导体裸片。所述封装级衬底具有第一表面,在所述第一表面处以第一配置安置第一接触衬垫。所述封装半导体装置与额外封装级衬底耦合,所述额外封装级衬底包含具有以所述第一配置安置的第二接触衬垫的第二表面和具有以不同于所述第一配置的第二配置安置的第三接触衬垫的第三表面。所述额外封装级衬底包含电路系统,所述电路系统耦合所述第二接触衬垫与所述第三接触衬垫以在所述第三接触衬垫处提供连接性。在这样做时,可组装自适应地兼容的半导体装置。
Description
技术领域
本公开大体上涉及半导体装置组合件,且更特定地说涉及用于凹入式半导体裸片的穿衬底连接。
背景技术
微电子装置大体上具有裸片(即,芯片),所述裸片包含具有高密度的极小部件的集成电路系统。通常,裸片包含电耦合到集成电路系统的极小接合衬垫阵列。接合衬垫是外部电接触件,供应电压、信号等通过所述接合衬垫传输到集成电路系统并从集成电路系统传输。在形成裸片之后,“封装”裸片以将接合衬垫耦合到可较容易地耦合到各种电力供应线、信号线及接地线的较大电端子阵列。用于封装裸片的常规工艺包含将裸片上的接合衬垫电耦合到引线阵列、球衬垫或其它类型的电端子,并且囊封裸片以保护其免受环境因素(例如,湿气、微粒、静电和物理冲击)的影响。
发明内容
在一个方面中,本公开提供一种半导体装置组合件,其包括:一或多个半导体裸片;第一封装级衬底,其包含:第一耦合表面,其具有第一接触衬垫;第二耦合表面,其具有以第一配置安置的第二接触衬垫;以及第一电路系统,其电耦合所述第一接触衬垫和所述第二接触衬垫;第一互连件,其在所述第一接触衬垫处电耦合所述一或多个半导体裸片和所述第一封装级衬底;第二封装级衬底,其包含:第三耦合表面,其具有以所述第一配置安置的第三接触衬垫;第四耦合表面,其具有以不同于所述第一配置的第二配置安置的第四接触衬垫;以及第二电路系统,其电耦合所述第三接触衬垫和所述第四接触衬垫;以及第二互连件,其在所述第二接触衬垫和所述第三接触衬垫处电耦合所述第一封装级衬底和所述第二封装级衬底。
在另一方面中,本公开提供一种制造半导体装置的方法,其包括:提供封装半导体装置,所述封装半导体装置具有第一耦合表面,所述第一耦合表面具有以第一配置安置的第一接触衬垫;从具有带有以各种配置安置的相应第二接触衬垫和第三接触衬垫的相应第二耦合表面和第三耦合表面的多个封装级衬底选择封装级衬底,所述封装级衬底具有:第二耦合表面,其具有以所述第一配置安置的第二接触衬垫;第三耦合表面,其具有以不同于所述第一配置的第二配置安置的第三接触衬垫,所述第二配置对应于所述封装半导体装置将耦合到的印刷电路板上的第四接触衬垫的配置;以及电路系统,其耦合所述第二接触衬垫和所述第三接触衬垫;以及通过电耦合所述第一接触衬垫和所述第二接触衬垫的互连件而耦合所述封装半导体装置和所述封装级衬底。
在另一方面中,本公开提供一种半导体装置组合件,其包括:封装半导体装置,其具有第一耦合表面,所述第一耦合表面具有以第一配置安置的第一接触衬垫;印刷电路板,其包含:第二耦合表面,其具有以所述第一配置安置的第二接触衬垫;第三耦合表面,其具有以不同于所述第一配置的第二配置安置的第三接触衬垫;以及电路系统,其电耦合所述第二接触衬垫和所述第三接触衬垫;以及互连件,其电耦合所述第一接触衬垫和所述第二接触衬垫。
附图说明
图1示出实例半导体装置组合件的简化示意横截面视图。
图2示出根据本发明技术的实施例的半导体装置组合件的简化示意横截面视图。
图3示出根据本发明技术的实施例的半导体装置组合件的简化示意横截面视图。
图4示出根据本发明技术的实施例的半导体装置组合件的简化示意横截面视图。
图5示出根据本发明技术的实施例的半导体装置组合件的示意性部分平面图。
图6示出根据本发明技术的实施例的半导体装置组合件的示意性部分平面图。
图7到8示出根据本发明技术的实施例的半导体装置组合件的一系列制造步骤的简化示意性横截面视图。
图9到12示出根据本发明技术的实施例的半导体装置组合件的简化示意横截面视图。
图13示出展示包含根据本发明技术的实施例配置的半导体装置组合件的系统的示意图。
图14示出根据本发明技术的实施例的用于制造半导体装置组合件的实例方法。
具体实施方式
半导体装置集成在许多装置中以实施存储器单元、处理器电路、成像器装置和其它功能特征。随着发现用于半导体装置的更多应用,设计者负责创建可每秒执行更多数目的操作、存储更大量的数据或以更高安全性等级操作的改进装置。为了实现此任务,设计者持续开发新技术以增加半导体装置上的电路元件的数目,同时不增加装置的大小。然而,此开发由于因设计具有高电路密度的半导体装置带来的各种挑战而可能是不可持续的。因此,可能需要额外技术来继续半导体装置的能力增长。
一种此类技术是在单个封装内实施多个电路组件。这些多个电路组件可有效地布置于封装内以提供能够具有各种功能性的紧凑半导体装置。虽然封装半导体装置可实现封装内的电路组件的复杂布置,但封装装置的外部连接可能需要与其它装置兼容,例如在同一主机装置中实施的其它装置。为了提供此装置兼容性,各种电路组件可通过与主机装置的组件(例如,母板)兼容的外部连接耦合到封装级衬底。在一些情况下,顾客可能请求具有相同功能要求但不同兼容性要求的半导体装置。然而,由于封装级衬底在封装半导体装置内的集成,半导体装置制造商可能被迫设计新封装衬底,且因此设计新封装半导体装置,以满足每一顾客兼容性要求,即使当封装半导体装置的功能性在顾客之间是相同的时也是如此。因此,用于制造封装半导体装置的许多解决方案可能产生制造工艺中的低效率,这会减少装置设计的处理量和交叉兼容性。在图1中借助实例示出一个此类半导体装置组合件。
如参考图1可见,半导体装置组合件100包含实施于存储器装置内的多个电路组件。所述多个电路组件包含实施于封装层级底108处的存储器裸片102、逻辑裸片104和电容器106。所述多个电路组件可耦合到封装级衬底108的上部表面处的接触件。举例来说,存储器裸片102可使用连接到存储器裸片102处的引脚的导电线耦合到封装级衬底108处的接触件。逻辑裸片104可通过逻辑裸片104的下部表面处的接触衬垫和封装级衬底108的上部表面处的接触衬垫连接到封装级衬底108。电容器106可与封装级衬底108的上部表面处的接触件耦合。所述多个电路组件和封装级衬底108可至少部分地由囊封物110囊封以保护电路组件免受干扰(例如,湿气、微粒、静电和物理冲击)。
所述多个电路组件中的任一个可彼此直接耦合或通过封装级衬底108耦合以对半导体装置提供各种功能性。封装级衬底108可另外包含电路系统,所述电路系统将所述多个电路组件耦合到额外电路组件以对半导体装置提供外部连接性(例如,电力、接地、输入/输出(I/O)信号等)。举例来说,封装级衬底108可包含将上部表面处的接触件耦合到下部表面处的接触衬垫的电路系统(例如,迹线、线、通孔等)。半导体装置可随后连接到在主机装置处实施的额外组件以提供各种功能性。举例来说,电容器106可连接到外部电力源以调节到存储器裸片102或到逻辑裸片104的电力,且逻辑裸片104可控制存储器裸片102的操作以存储或检索用于耦合到封装级衬底108的处理器的数据。以此方式,半导体装置可对兼容主机装置提供功能性。
半导体装置可设计有特定兼容性,例如与其中实施半导体装置的主机装置相同的兼容性。通常主机装置可包含其上实施主机装置的多个组件的印刷电路板(PCB)。PCB可包含以特定配置布置且与具有以相同配置布置的外部连接的装置兼容的接触衬垫。为了使封装半导体装置与PCB兼容,封装级衬底108可被设计成具有类似于PCB上的接触衬垫配置的外部暴露的接触衬垫。然而,因此封装半导体装置可能不与不同主机装置兼容,例如由不同顾客使用的PCB。一旦封装好,电路组件就可固定到封装级衬底108。因此,为了实施具有相同功能性(例如,具有相同功能规范的存储器装置)但具有不同兼容性的半导体装置,可能需要制造完全新的半导体装置。因此,一些封装解决方案可能产生设计低效率且抑制跨越顾客的装置兼容性。
为了克服这些缺陷等,本文公开的技术描述了包含封装半导体装置的半导体装置组合件,所述封装半导体装置具有耦合到封装级衬底的一或多个半导体裸片。所述封装级衬底具有第一表面,在所述第一表面处以第一配置安置第一接触衬垫。封装半导体装置与额外封装级衬底耦合,所述额外封装级衬底包含具有以第一配置安置的第二接触衬垫的第二表面和具有以不同于第一配置的第二配置安置的第三接触衬垫的第三表面。所述额外封装级衬底包含电路系统,所述电路系统耦合第二接触衬垫与第三接触衬垫以在第三接触衬垫处提供连接性。在这样做时,可组装自适应地兼容的半导体装置。
本文中所公开的技术涉及半导体装置、具有半导体装置的系统,以及用于制造半导体装置的相关方法。术语“半导体装置”一般指包含一或多种半导体材料的固态装置。半导体装置的实例包含逻辑装置、存储器装置及二极管等等。此外,术语“半导体装置”可以指成品装置或在变为成品装置之前的各个处理阶段处的组合件或其它结构。取决于其使用的情境,术语“衬底”可以指支撑电子组件(例如,裸片)的结构,例如印刷电路板(PCB)或晶片级衬底、裸片级衬底、或用于裸片堆叠或3DI应用的另一裸片。
虽然可能相对于裸片或晶片示出或描述一些实例,但本文公开的技术可应用于裸片或晶片。此外,除非情境另有指示,否则可使用常规的半导体制造技术来形成本文中所公开的结构。举例来说,材料可使用化学气相沉积、物理气相沉积、原子层沉积、旋涂和/或其它合适的技术来沉积。类似地,举例来说,可使用等离子蚀刻、湿式蚀刻、化学-机械平坦化或其它合适的技术去除材料。
本文中所论述的包含存储器装置的装置可形成在半导体衬底或裸片,例如硅、锗、硅锗合金、砷化镓、氮化镓等上。在一些情况下,衬底为半导体晶片。在其它情况下,衬底可为绝缘体上硅(silicon-on-insulator,SOI)衬底,例如玻璃上硅(silicon-on-glass,SOG)或蓝宝石上硅(silicon-on-sapphire,SOP),或另一衬底上的半导体材料的外延层。可通过使用包含但不限于磷、硼或砷的各种化学物质的掺杂来控制衬底或衬底的子区的导电性。可在衬底的初始形成或生长期间,通过离子植入或通过任何其它掺杂方法执行掺杂。
如本文中所使用,鉴于图中所示的定向,术语“竖直”、“横向”、“上部”及“下部”可以指半导体裸片组合件中的特征的相对方向或位置。举例来说,“上部”或“最上部”可指比另一特征更接近页面的顶部定位的特征。然而,这些术语应广泛地理解为包含具有其它定向的半导体装置,所述定向例如倒置或倾斜定向,其中顶部/底部、上面/下面、上方/下方、向上/向下,及左侧/右侧可取决于定向而互换。
图2示出根据本发明技术的实施例的半导体装置组合件200的简化示意横截面视图。半导体装置组合件200包含多个电路组件,例如存储器裸片202、逻辑裸片204和电容器206。所述多个电路组件可在耦合表面处与封装级衬底208耦合。封装级衬底208可为PCB或任何其它衬底,例如半导体裸片或由半导体材料制成的衬底。电路组件可通过任何数目的技术附接,例如线接合、焊料凸块、铜柱等。封装级衬底208的上部表面可包含接触衬垫(未示出),电路组件可电耦合在所述接触衬垫处以实现电路组件与封装级衬底208之间的通信。上部表面处的接触衬垫可连接到封装级衬底208处的电路系统(例如,迹线、线、通孔、电线等),所述电路系统连接上部表面处的接触衬垫与封装级衬底208的下部表面处的接触衬垫212。接触衬垫212可使得所述多个电路组件能够与外部电路部件电耦合以对所述多个电路组件提供各种功能性(例如,电力、接地、I/O信号等)。所述多个电路组件和封装级衬底208可至少部分地由囊封物210囊封以保护电路组件免受干扰(例如,湿气、微粒、静电和物理冲击)。
在一些实施方案中,与封装级衬底208耦合且由囊封物210囊封的多个电路组件可称为“封装半导体装置”。封装半导体装置可为任何适当半导体装置。举例来说,封装半导体装置可为存储器装置,例如动态随机存取存储器(DRAM)装置、“与非”(NAND)存储器装置、“或非”(NOR)存储器装置、磁性随机存取存储器(MRAM)装置、相变存储器(PCM)装置、铁电随机存取存储器(FeRAM)装置、静态随机存取存储器(SRAM)装置,或类似者。在其中多个裸片提供于单个组合件中的实施例中,半导体装置可以包含相同种类的存储器裸片(例如,两个NAND、两个DRAM等)或不同种类的存储器裸片(例如,一个DRAM和一个NAND等)。根据本公开的另一方面,封装半导体装置可为逻辑装置(例如,控制器裸片、处理器裸片等),或具有逻辑和存储器裸片的混合(例如,存储器控制器裸片和由此控制的存储器裸片)的装置。
举例来说,基于顾客所请求的规范,封装半导体装置可与任何数目的其它电路组件兼容。可在封装半导体装置的外部暴露的接触衬垫212可以特定配置安置于封装级衬底208处以对封装半导体装置提供某一兼容性。举例来说,接触衬垫212可根据当前、传统或未来一代的通用快闪存储(UFS)标准(例如,UFS1.X、UFS2.X、UFS 3.X、UFS 4.X、UFS 5.X等,其中“X”是任何子版本编号,例如0、1、2等)或任何其它标准(例如,嵌入式多媒体卡(eMMC)、固态硬盘(SSD)、交越快闪存储器(XFM)等)来布置以提供与类似配置的主机装置的兼容性。一旦封装好,封装级衬底且因此接触衬垫212的配置就不可改变。因此,在多个顾客要求相同功能规范(例如,多个电路组件的配置是相同的)但兼容性规范不同的情况下,每一顾客可能需要单独的半导体装置。
然而,如图2的半导体装置组合件200中所示,额外封装级衬底214可与封装级衬底208或封装半导体装置耦合以更改封装半导体装置的兼容性。额外封装级衬底214可包含任何适当衬底,例如PCB或硅衬底(例如,插入件)。额外封装级衬底214可包含上部表面,接触衬垫216以对应于封装级衬底214处的接触衬垫212的配置的配置安置于所述接触衬垫处。以此方式,封装半导体装置可通过封装级衬底208处的接触衬垫212和额外封装级衬底214处的接触衬垫216耦合到额外封装级衬底214。接触衬垫212和接触衬垫216可通过任何适当互连件电耦合。举例来说,焊料接头218可由安置于接触衬垫212处的焊料球形成。可使额外封装级衬底214在接触衬垫216处与焊料球接触,且可加热焊料球以回流焊料材料且在封装半导体装置与额外封装级衬底214之间形成焊料接头218。底部填充材料220(例如,模制底部填充物、毛细底部填充物等)可安置于封装级衬底208与额外封装级衬底214之间以隔绝互连件或机械地支撑封装级衬底208和额外封装级衬底214的耦合。
额外封装级衬底214可另外包含在下部表面处的接触衬垫222。下部表面处的接触衬垫222可以不同于上部表面处的接触衬垫216的配置安装,所述配置例如不同代的UFS标准或任何其它标准。额外封装级衬底214可包含电路系统(例如,迹线、通孔和其它导电结构),所述电路系统连接上部表面处的接触衬垫216与下部表面处的接触衬垫222(图2中示意性地示出)。所述电路系统可将接触衬垫216路由到下部表面处的用于相同目的(例如,电力、接地、I/O信令)的接触衬垫222。在一些实施方案中,额外封装级衬底214可为具有路由电路系统(例如,通孔或其它连接结构)的两层衬底,所述电路系统连接具有接触衬垫216的第一层和具有接触衬垫222的第二层。在其它实施方案中,额外封装级衬底214可包含额外层,所述额外层可包含在额外封装级衬底214处实施的逻辑电路系统的层。焊料球或任何其它连接元件可安置于额外封装级衬底214的接触衬垫222处以使得额外封装级衬底且因此封装半导体装置能够耦合到与额外封装级衬底214的接触衬垫222的配置兼容的外部电路部件(例如,主机装置处的PCB)。因此,额外封装级衬底214可提供调适封装半导体装置的兼容性的机制,进而实现封装后半导体装置的交叉兼容性且减少生产具有各种兼容性的具有类似能力的半导体装置所需要的设计时间。
图3示出包含封装半导体装置302的半导体装置组合件300的简化示意横截面视图。与图2所示的封装半导体装置相比,封装半导体装置302可包含安装在封装级衬底306上且与其电耦合的堆叠半导体裸片304。然而,应注意,封装半导体装置可包含以任何特定配置布置的任何数目的电路组件或半导体裸片。堆叠半导体裸片304和封装级衬底306可至少部分地由囊封物308囊封以保护堆叠半导体裸片304或封装级衬底306免受干扰。类似于相对于图2描述的封装半导体装置,封装半导体装置302可包含具有安置于下部表面处且在封装半导体装置302的外部暴露的接触衬垫的封装级衬底306。封装半导体装置302可与更改封装半导体装置302的兼容性的额外封装级衬底310耦合。封装半导体装置302和封装级衬底310可通过互连件耦合。举例来说,安置于封装半导体装置302与封装级衬底310之间的接触衬垫处的焊膏312。封装级衬底310可包含电路系统(在图3中示意性地示出),所述电路系统耦合其上实施焊膏312的接触衬垫与下部表面处的以不同配置安置的接触衬垫。因此,半导体装置组合件300可与具有对应于额外封装级衬底310的下部表面处的接触衬垫的配置的配置的额外电路组件兼容。
图4示出包含耦合到额外封装级衬底404的封装半导体装置402的半导体装置组合件400的简化示意横截面视图。封装半导体装置402可类似于或不同于图2或3所示的封装半导体装置中的任一个。与图2和3中示出的封装半导体装置相比,封装半导体装置402可通过导电柱406(例如,由铜、金、银、锡、铝或这些材料的合金构成)与额外封装级衬底404耦合。导电柱406可实施于封装半导体装置402处的接触衬垫与额外封装级衬底404处的以相同配置安置的接触衬垫之间。额外封装级衬底404可包含电路系统(图4中示意性地示出),所述电路系统耦合与导电柱406耦合的接触衬垫与下部表面处的以不同配置安置的接触衬垫。焊料球或其它连接元件可在下部表面处的接触衬垫处实施以使得封装半导体装置402能够耦合到具有对应于焊料球的接触衬垫的额外电路组件(例如,通过额外封装级衬底404)。
本公开现在转到图5和6,其示出根据多代UFS标准的在封装半导体装置处的接触衬垫的实例配置,然而应了解,可根据其它代的UFS标准或其它标准安置接触衬垫。实例配置可对应于封装半导体装置的暴露耦合表面(例如,如图2至4中所示的下部表面)或额外封装级衬底的表面的示意性部分平面图。举例来说,封装半导体装置和额外封装级衬底的第一表面可具有根据UFS 3.X标准安置的接触衬垫,且额外封装级衬底的第二表面可具有根据UFS 4.X标准安置的接触衬垫,反之亦然。在一些实例中,封装半导体装置和额外封装级衬底的第一表面可根据更复杂的布线(例如,根据UFS 4.X标准)设计,且额外封装级衬底可将第一表面处的接触衬垫路由到第二表面处的根据较不复杂的布线(例如,根据UFS 3.x标准)设计的接触衬垫。
图5示出包含封装级衬底502的半导体装置组合件500的示意性部分平面图,所述封装级衬底具有耦合表面,所述耦合表面具有根据UFS 3.0标准安置的接触衬垫504。焊料球可在接触衬垫中的每一个处实施以根据UFS 3.0标准产生球栅阵列。接触衬垫504的配置可指定每一接触衬垫的位置和使用。举例来说,封装级衬底502处的接触衬垫504以特定图案安置,且指定每一接触衬垫的使用。如所说明,接触衬垫504中的每一个的使用由标签指定。接触衬垫504可用于不同类型的通信,例如供应信号(例如,电压、接地等)、输入信号(例如,复位信号、数据输入、时钟信号等),或输出信号(例如,数据输出)。其它接触衬垫504可连接到接地或保持浮动,例如经预留用于未来使用或测试。配置可指定用于与半导体装置通信的特定数目的接触衬垫。如所说明,封装级衬底502包含153个接触衬垫。
图6示出包含封装级衬底602的半导体装置组合件600的示意性部分平面图,所述封装级衬底具有耦合表面,所述耦合表面具有根据UFS 4.0标准安置的接触衬垫604。焊料球可在接触衬垫中的每一个处实施以根据UFS 4.0标准产生球栅阵列。类似于相对于图5描述的封装级衬底,封装级衬底602处的接触衬垫604以特定图案安置,且基于UFS 4.0标准指定每一接触衬垫的使用。接触衬垫604可用于与相对于图5描述的接触衬垫类似的通信。举例来说,接触衬垫604可促进供应信号(例如,电压、接地等)、输入信号(例如,复位信号、数据输入、时钟信号等)或输出信号(例如,数据输出)的通信。其它接触衬垫604可连接到接地或保持浮动,例如经预留用于未来使用或测试。与相对于图5描述且根据UFS 3.0标准安置的接触衬垫相比,接触衬垫604包含237个接触衬垫。
在一些实施方案中,图5和6中分别示出的封装级衬底502或封装级衬底602可为封装半导体装置的封装级衬底(例如,图2所示的封装级衬底208)的暴露耦合表面。封装级衬底可在与示出的表面相对的耦合表面处耦合到封装半导体装置内的各种电路组件。封装级衬底可包含内部电路系统,所述内部电路系统将封装级衬底与电路组件之间的连接耦合到图5或6中示出的接触衬垫中的适当接触衬垫(例如,基于使用)。在这样做时,封装半导体装置可与使用接触衬垫的类似配置(例如,UFS 3.0、UFS 4.0等)的额外电路组件(例如,主机装置处的PCB)兼容。
在一些实施方案中,图5和6中分别示出的封装级衬底502和封装级衬底602可为与封装半导体装置耦合以更改封装半导体装置的兼容性的额外封装级衬底(例如,图2所示的封装级衬底208)。图5和6中的示意性部分平面图可示出具有接触衬垫的不同配置的额外封装级衬底的相对表面。额外封装级衬底可包含将一个表面处的接触衬垫耦合到在相对表面处的接触衬垫的内部电路系统。第一表面处的接触衬垫可耦合到在相对表面处的具有相同使用的接触衬垫。以此方式,可更改耦合表面处的接触衬垫的配置而不需要重新配置封装半导体装置处的接触衬垫的使用。在一些实施方案中,额外封装衬底的第一表面与相对表面相比可具有不同数目的接触衬垫(例如,一个表面具有以UFS 3.X配置安置的接触衬垫,且另一表面具有以UFS 4.X配置安置的接触衬垫)。因此,额外封装层级衬底处的电路系统可不在每一表面上的接触衬垫之间一对一地路由。在此情况下,一些接触衬垫可以不在相对表面处连接,或者一个表面处的多个接触衬垫可与相对表面处的相同接触衬垫耦合。
图7和8示出根据本发明技术的实施例的半导体装置组合件的一系列制造步骤的简化示意性横截面视图。如图7中所示,方法可包含用于提供半导体装置702的阶段700。半导体装置702可包含耦合到封装级衬底706的堆叠半导体裸片704。封装级衬底706可包含接触件(例如,衬垫),半导体裸片704耦合于所述接触件处,且所述接触件连接到在封装半导体装置的外部暴露的接触衬垫708。举例来说,基于顾客所请求的使封装半导体装置702能够在主机装置内实施的规范,接触衬垫708可以特定配置安置以实现与外部装置的兼容性。在一些实例中,此配置可不同于使封装半导体装置702与由不同顾客使用的外部组件兼容所需要的配置。因此,封装半导体装置702无法按原样安装于一些顾客的装置内。
如图8中所示,方法可包含用于选择额外封装级衬底802以更改封装半导体装置702的兼容性以使得封装半导体装置702能够安装于主机装置的PCB(例如,母板)或其它电路组件上的阶段800。额外封装级衬底802可选自多个封装级衬底,其各自具有带有以各种配置安置的接触衬垫的相应第一表面和第二表面。额外封装级衬底802可具有第一表面,所述第一表面具有接触衬垫804,所述接触衬垫以对应于封装半导体装置702处的接触衬垫708的配置的配置安置以使得互连件806能够电耦合接触衬垫708和接触衬垫804。额外封装级衬底802可进一步包含第二表面,所述第二表面具有接触衬垫808,所述接触衬垫以与其中将实施封装半导体裸片702的主机装置的PCB或其它组件处的接触衬垫的配置相同的配置安置。
一旦选定,封装半导体裸片702就可通过接触衬垫708和接触衬垫804处的互连件806电耦合到额外封装级衬底802。因此,接触衬垫808可提供与封装半导体装置702耦合的暴露连接,以使得封装半导体装置702能够通过额外封装级衬底802与主机装置的PCB或其它组件耦合。底部填充材料810可安置于封装半导体装置702与额外封装级衬底802之间,或囊封物可至少部分地囊封封装半导体装置702和额外封装级衬底802。
图9到11示出根据本发明技术的实施例的半导体装置组合件的一系列制造步骤的简化示意性横截面视图。与图7和8中示出的一系列制造步骤相比,图9到11所示的制造步骤可将多个半导体装置组合件制造到额外封装级衬底上。可随后将额外封装级衬底分离以产生多个半导体装置。
如图9中所示,方法可包含用于提供包含封装半导体装置902和封装半导体装置904的多个封装半导体装置的阶段900。所述多个封装半导体装置可包含相同的一组电路组件以实施相同功能或可包含不同电路组件以实施不同功能。虽然裸片的功能组件可不同,但在封装半导体装置的外部的接触衬垫的配置可相同。封装半导体装置可为初始被设计成满足第一兼容性要求的成品半导体装置;然而,现在可改变封装半导体装置的兼容性以使得装置能够与不同主机装置兼容。
如图10中所示,方法可包含用于电耦合封装半导体装置902和封装半导体装置904与额外封装级衬底1002的阶段1000。额外封装级衬底1002可包含在第一表面处以对应于封装半导体装置处的接触衬垫的配置安置的接触衬垫,以及在第二表面处以不同配置安置的接触衬垫。封装半导体装置可在额外封装级衬底1002上安装于不同的横向位置。在一些实例中,当安装在额外封装级衬底1002上时封装半导体装置中的每一个之间可能存在间隙。额外封装级衬底1002可被设计成支持封装半导体装置的任何数目的配置。
如图11中所示,方法可包含用于分离额外封装级衬底1002以分离封装半导体装置902和封装半导体装置904的阶段1100。额外封装级衬底1002可沿着封装半导体装置902与封装半导体装置904之间的切割线1102分离。额外封装级衬底1002可通过任何适当技术(例如,锯切、蚀刻等)分离以分离额外封装级衬底1002。在分离之前或之后,可在封装半导体装置902或封装半导体装置904与额外封装级衬底1002之间分配底部填充材料。
如图12中所示,方法可包含用于提供封装半导体装置1202和封装半导体装置1204的阶段1200,这些封装半导体装置可分别包含封装半导体装置902和额外封装级衬底1206以及封装半导体装置904和额外封装级衬底1208。由于额外封装级衬底1206和额外封装级衬底1208,封装半导体装置1202和封装半导体装置1204可具有与封装半导体装置902和封装半导体装置904不同的兼容性。在额外封装级衬底在封装半导体装置之间分离的条件下,额外封装级衬底1206和额外封装级衬底1208可分别具有比封装半导体装置902(例如,封装级衬底处)和封装半导体装置904(例如,封装级衬底处)的表面积更大的表面积(例如,耦合表面处)。一旦分离,封装半导体装置1202和封装半导体装置1204就可分别由囊封物1210和囊封物1212囊封。以此方式,可更改封装半导体装置902和封装半导体装置904的兼容性以产生封装半导体装置1202和封装半导体装置1204。
虽然前述实例半导体装置组合件已经示出且描述为包含特定数目的半导体裸片,但在其它实施例中,组件可具备更多或更少的半导体裸片。举例来说,图2至12中示出的半导体装置可以被具有任何其它数目的半导体裸片的半导体装置代替,加以必要的修改。
上文参考图2到12所描述的半导体装置和半导体装置组合件中的任一个可并入到大量更大和/或更复杂的系统中的任一个中,所述系统的代表性实例为图13中示意性地示出的系统1300。系统1300可包含半导体装置组合件1302(例如,或离散半导体装置)、电力源1304、驱动器1306、处理器1308和/或其它子系统或组件1310。半导体装置组合件1302可包含大体上与上文参考图2到12所描述的半导体装置的特征类似的特征。所得系统1300可执行广泛多种功能中的任一种,例如存储器存储、数据处理和/或其它合适的功能。因此,代表性系统1300可包含但不限于手持式装置(例如,移动电话、平板计算机、数字阅读器和数字音频播放器)、计算机、车辆、电器和其它产品。系统1300的组件可容纳于单个单元中或分布在多个互连的单元上(例如,通过通信网络)。系统1300的组件还可包含远程装置和多种计算机可读媒体中的任一种。
图14示出根据本发明技术的实施例的用于制造半导体装置组合件的实例方法。出于说明性目的,方法1400可相对于图2到13的特征、组件或元件描述。虽然在特定配置中示出,但方法1400的一或多个操作可省略、重复或重新组织。另外,方法1400可包含在图14中未示出的其它操作,举例来说,在本文所描述的一或多个其它方法中详细说明的操作。
在1402,提供封装半导体装置702。封装半导体装置702可包含具有以第一配置安置的第一接触衬垫708的第一耦合表面。在一些实施方案中,可提供额外封装半导体装置,其包含具有以第一配置安置的接触衬垫的耦合表面。额外封装半导体装置可以是与封装半导体装置702相同或不同的封装半导体装置。
在1404,从具有带有以各种配置安置的接触衬垫的相应第二和第三耦合表面的多个封装级衬底选择额外封装级衬底802。可选择额外封装级衬底802以使得第二耦合表面具有以第一配置安置的接触衬垫804且第三耦合表面具有以不同于第一配置的第二配置安置的接触衬垫808。第二配置可对应于封装半导体装置702将与其耦合的电路组件(例如,PCB)上的接触衬垫的配置。额外封装级衬底802可包含将接触衬垫804耦合到接触衬垫808的电路系统。在其中提供多个封装半导体装置的实施方案中,额外封装级衬底802可包含第二耦合表面处的以第一配置安置的额外接触衬垫和第三耦合表面处的以第二配置安置的额外接触衬垫。电路系统可耦合额外接触衬垫。
在1406,封装半导体装置702和额外封装级衬底802可通过电耦合接触衬垫804和接触衬垫808的互连件806耦合。可在封装半导体装置702与额外封装级衬底802之间分配底部填充材料220。在其中提供额外封装半导体装置的实施方案中,额外封装半导体装置和额外封装级衬底802可通过额外互连件耦合。额外封装级衬底802可在封装半导体装置之间分离以分离封装半导体装置。因此,执行方法1400可使用额外衬底调整封装半导体装置的兼容性以产生具有不同兼容性的封装半导体装置。
本文中所描述的功能可以硬件、由处理器执行的软件、固件或其任何组合实施。其它实例和实施在本公开和所附权利要求书的范围内。实施功能的特征还可物理上位于各种位置处,包含经分布以使得功能的部分在不同物理位置处实施。
如本文中所使用,包含在权利要求书中,如在项列表(例如,后加例如“中的至少一个”或“中的一或多个”的短语的项列表)中所使用的“或”指示包含端点的列表,使得例如A、B或C中的至少一个的列表意指A或B或C或AB或AC或BC或ABC(即,A和B和C)。另外,如本文所用,短语“基于”不应理解为提及封闭条件集。举例来说,在不脱离本公开的范围的情况下,描述为“基于条件A”的示范性步骤可基于条件A和条件B两者。换句话说,如本文所用,短语“基于”应同样地解释为短语“至少部分地基于”。
从上文中将了解,本文中已经出于说明的目的描述了本发明的具体实施例,但是可以在不偏离本发明的范围的情况下进行各种修改。相反,在以上描述中,论述了众多具体细节以提供对本发明技术的实施例的透彻及启发性描述。然而,相关领域的技术人员将认识到,可在并无具体细节中的一或多个的情况下实践本公开。在其它情况下,未展示或未详细地描述通常与存储器系统及装置相关联的众所周知的结构或操作,以避免混淆技术的其它方面。一般来说,应理解,除了本文中所公开的那些具体实施例之外的各种其它装置、系统和方法可在本发明技术的范围内。
Claims (20)
1.一种半导体装置组合件,其包括:
一或多个半导体裸片;
第一封装级衬底,其包含:
第一耦合表面,其具有第一接触衬垫;
第二耦合表面,其具有以第一配置安置的第二接触衬垫;以及
第一电路系统,其电耦合所述第一接触衬垫和所述第二接触衬垫;
第一互连件,其在所述第一接触衬垫处电耦合所述一或多个半导体裸片和所述第一封装级衬底;
第二封装级衬底,其包含:
第三耦合表面,其具有以所述第一配置安置的第三接触衬垫;
第四耦合表面,其具有以不同于所述第一配置的第二配置安置的第四接触衬垫;以及
第二电路系统,其电耦合所述第三接触衬垫和所述第四接触衬垫;以及
第二互连件,其在所述第二接触衬垫和所述第三接触衬垫处电耦合所述第一封装级衬底和所述第二封装级衬底。
2.根据权利要求1所述的半导体装置组合件,其中所述第二互连件包括焊料接头。
3.根据权利要求1所述的半导体装置组合件,其中所述第二互连件包括导电柱。
4.根据权利要求1所述的半导体装置组合件,其中:
所述第一封装级衬底包括第一印刷电路板;且
所述第二封装级衬底包括第二印刷电路板。
5.根据权利要求4所述的半导体装置组合件,其中所述第二印刷电路板是两层印刷电路板。
6.根据权利要求1所述的半导体装置组合件,其中所述一或多个半导体裸片和所述第一封装级衬底至少部分地由囊封物囊封。
7.根据权利要求1所述的半导体装置组合件,其中所述第三接触衬垫包含与所述第四接触衬垫不同数目的接触衬垫。
8.根据权利要求1所述的半导体装置组合件,其中:
所述第一配置包括通用快闪存储4.X配置;且
所述第二配置包括通用快闪存储3.X配置。
9.根据权利要求1所述的半导体装置组合件,其中:
所述第一配置包括通用快闪存储3.X配置;且
所述第二配置包括通用快闪存储4.X配置。
10.根据权利要求1所述的半导体装置组合件,其进一步包括分配于所述第一封装级衬底与所述第二封装级衬底之间的底部填充材料。
11.根据权利要求1所述的半导体装置组合件,其中所述第二封装级衬底具有比所述第一封装级衬底更大的表面积。
12.一种制造半导体装置的方法,其包括:
提供封装半导体装置,所述封装半导体装置具有第一耦合表面,所述第一耦合表面具有以第一配置安置的第一接触衬垫;
从具有带有以各种配置安置的相应第二接触衬垫和第三接触衬垫的相应第二耦合表面和第三耦合表面的多个封装级衬底选择封装级衬底,所述封装级衬底具有:
第二耦合表面,其具有以所述第一配置安置的第二接触衬垫;
第三耦合表面,其具有以不同于所述第一配置的第二配置安置的第三接触衬垫,所述第二配置对应于所述封装半导体装置将耦合到的印刷电路板上的第四接触衬垫的配置;以及
电路系统,其耦合所述第二接触衬垫和所述第三接触衬垫;以及
通过电耦合所述第一接触衬垫和所述第二接触衬垫的互连件而耦合所述封装半导体装置和所述封装级衬底。
13.根据权利要求12所述的方法,其中:
所述封装级衬底进一步具有:
第五接触衬垫,其在所述第二耦合表面处以所述第一配置安置;
第六接触衬垫,其在所述第三耦合表面处以所述第二配置安置;且
所述方法进一步包括:
提供额外封装半导体装置,所述额外封装半导体装置具有第四耦合表面,所述第四耦合表面具有以所述第一配置安置的第七接触衬垫;以及
通过电耦合所述第七接触衬垫和所述第五接触衬垫的额外互连件而耦合所述额外封装半导体装置和所述封装级衬底。
14.根据权利要求13所述的方法,其进一步包括在所述封装半导体装置与所述额外封装半导体装置之间分离所述封装级衬底以分离所述封装半导体裸片和所述额外封装半导体裸片。
15.根据权利要求12所述的方法,其进一步包括在所述封装半导体装置与所述封装级衬底之间分配底部填充材料。
16.一种半导体装置组合件,其包括:
封装半导体装置,其具有第一耦合表面,所述第一耦合表面具有以第一配置安置的第一接触衬垫;
印刷电路板,其包含:
第二耦合表面,其具有以所述第一配置安置的第二接触衬垫;
第三耦合表面,其具有以不同于所述第一配置的第二配置安置的第三接触衬垫;以及
电路系统,其电耦合所述第二接触衬垫和所述第三接触衬垫;以及
互连件,其电耦合所述第一接触衬垫和所述第二接触衬垫。
17.根据权利要求16所述的半导体装置组合件,其中所述第二接触衬垫包含与所述第三接触衬垫不同数目的接触衬垫。
18.根据权利要求16所述的半导体装置组合件,其中:
所述第一配置包括通用快闪存储4.X配置;且
所述第二配置包括通用快闪存储3.X配置。
19.根据权利要求16所述的半导体装置组合件,其中:
所述第一配置包括通用快闪存储3.X配置;且
所述第二配置包括通用快闪存储4.X配置。
20.根据权利要求16所述的半导体装置组合件,其中所述封装半导体装置包括由包含所述第一耦合表面的另一印刷电路板承载的存储器装置。
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