CN115224012A - 具有多个衬底和裸片堆叠的半导体装置 - Google Patents

具有多个衬底和裸片堆叠的半导体装置 Download PDF

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Publication number
CN115224012A
CN115224012A CN202210386732.3A CN202210386732A CN115224012A CN 115224012 A CN115224012 A CN 115224012A CN 202210386732 A CN202210386732 A CN 202210386732A CN 115224012 A CN115224012 A CN 115224012A
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China
Prior art keywords
die
substrate
die stack
stack
dies
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CN202210386732.3A
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Inventor
张振辉
黄宏远
赫姆·P·塔克亚尔
倪胜锦
陈奕武
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Micron Technology Inc
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Micron Technology Inc
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Publication of CN115224012A publication Critical patent/CN115224012A/zh
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Abstract

本文中公开了具有多个衬底和裸片堆叠的半导体装置，以及相关联系统和方法。在一些实施例中，一种半导体装置包含封装衬底，以及安装在所述封装衬底上且包含多个第一存储器裸片的第一裸片堆叠。所述装置可包含安装在所述第一裸片堆叠上的衬底，所述衬底包含多个路由元件。所述装置还可包含安装在所述衬底上的第二裸片堆叠，所述第二裸片堆叠包含多个第二存储器裸片。所述装置可进一步包含安装在所述衬底上的控制器裸片。所述控制器裸片可被配置成经由所述衬底的所述路由元件与所述第二裸片堆叠通信。所述装置可包含包封所述第一裸片堆叠、所述第二裸片堆叠、所述衬底和所述控制器裸片的模制材料。

Description

具有多个衬底和裸片堆叠的半导体装置
技术领域
本发明技术大体上涉及半导体装置，且更确切地说，涉及具有用于相应裸片堆叠的信号路由的多个衬底的半导体装置。
背景技术
包含存储器芯片、微处理器芯片和成像器芯片的经封装半导体裸片通常包含安装在衬底上且包覆在保护性覆盖物中的半导体裸片。半导体裸片可包含功能特征，例如存储器单元、处理器电路和成像器装置，以及电连接到功能特征的接合垫。接合垫可电连接到保护性覆盖物外部的端子，以允许半导体裸片连接到更高层级电路系统。
市场压力不断地驱使半导体制造商减小裸片封装的大小以适配在电子装置的空间限制内，同时也驱使半导体制造商增加每一封装的功能容量以满足操作参数。一种用于增加半导体封装的处理能力而不大体上增加由封装覆盖的表面积(即，封装的“覆盖面积”)的方法是在单个封装中将多个半导体裸片竖直堆叠在彼此的顶部上。此类竖直堆叠式封装中的裸片可经由电线、互连件或其它导电结构彼此电耦合和/或电耦合到衬底。然而，用于将信号路由到竖直堆叠式半导体裸片和从竖直堆叠式半导体裸片路由信号的常规技术可依赖于单个封装衬底内的复杂的多层路由结构，这可导致减少的信号完整性，较大封装大小以及增加的制造成本。
发明内容
根据本申请的方面，提供一种半导体装置。所述半导体装置包括：封装衬底；第一裸片堆叠，其安装在封装衬底上，第一裸片堆叠包含多个第一存储器裸片；中间衬底，其安装在第一裸片堆叠上，中间衬底包含多个路由元件；第二裸片堆叠，其安装在衬底上，第二裸片堆叠包含多个第二存储器裸片；控制器裸片，其安装在衬底上，其中控制器裸片被配置成经由中间衬底的路由元件与第二裸片堆叠通信；以及模制材料，其包封第一裸片堆叠、第二裸片堆叠、中间衬底和控制器裸片。
根据本申请的另一方面，提供一种半导体装置。所述半导体装置包括：封装衬底；第一裸片堆叠，其安装在封装衬底上，第一裸片堆叠包含耦合到封装衬底的多个DRAM裸片；中间衬底，其直接安装在第一裸片堆叠上，中间衬底包含多个路由元件，其中中间衬底经由一或多个焊线电耦合到封装衬底；第二裸片堆叠，其安装在中间衬底上，第二裸片堆叠包含耦合到中间衬底的多个NAND裸片；控制器裸片，其安装在中间衬底上，其中控制器裸片被配置成经由中间衬底的路由元件与第二裸片堆叠通信；以及模制材料，其包封第一裸片堆叠、第二裸片堆叠、中间衬底和控制器裸片。
根据本申请的又一方面，提供一种用于制造半导体装置的方法。所述方法包括：通过将多个第一存储器裸片安装在第一衬底上来形成第一组合件；通过将多个第二存储器裸片和控制器裸片安装在第二衬底上来形成第二组合件，其中第二存储器裸片经由第二衬底中的路由元件电耦合到控制器裸片；将第二组合件安装在第一组合件上；以及在将第二组合件安装在第一组合件上之后，用模制材料包封第一组合件和第二组合件。
附图说明
参考以下图式可更好地理解本发明技术的许多方面。图式中的组件不一定按比例绘制。实际上，重点是清楚地说明本发明技术的原理。
图1A为根据本发明技术的实施例配置的半导体装置的部分示意性侧横截面视图。
图1B为图1A的半导体装置的第一衬底的部分示意性侧横截面视图。
图1C为图1A的半导体装置的第二衬底的部分示意性侧横截面视图。
图2为根据本发明技术的实施例配置的另一半导体装置的部分示意性横截面视图。
图3为根据本发明技术的实施例配置的另一半导体装置的部分示意性横截面视图。
图4为根据本发明技术的实施例的说明用于制造半导体装置的方法的流程图。
图5为包含根据本发明技术的实施例配置的半导体装置或封装的系统的示意图。
具体实施方式
下文描述半导体装置的若干实施例以及相关联系统和方法的具体细节。在一些实施例中，例如，一种半导体装置包含：第一裸片堆叠，其包含多个第一存储器裸片(例如，DRAM裸片)；第二裸片堆叠，其包含多个第二存储器裸片(例如，NAND裸片)；以及用于第二裸片堆叠的控制器和/或逻辑裸片(例如，NAND控制器裸片)。第一裸片堆叠可安装在封装衬底上。半导体装置还可包含安装在第一裸片堆叠上的中间衬底，并且第二裸片堆叠和控制器裸片可安装在中间衬底上。半导体装置可进一步包含模制材料，其包封第一裸片堆叠、第二裸片堆叠、中间衬底和控制器裸片，以形成单个整体封装。
在一些实施例中，用于第二裸片堆叠的信号路由与用于第一裸片堆叠的信号路由物理地分离和/或电隔离。举例来说，第二裸片堆叠可经由中间衬底中的路由元件与控制器裸片通信，而第一裸片堆叠可经由封装衬底中的路由元件与外部装置(例如，主机装置)通信。因此，例如，相较于通过封装衬底路由所有信号的常规装置，封装衬底中的信号路由可减少和/或简化。因此，可使用较薄和较不复杂的封装衬底，这可减小总体封装高度。此方法还可通过减少或消除在通过单个衬底路由所有裸片堆叠信号的情况下可能产生的串扰而改进信号完整性。另外，可独立于封装衬底中的信号路由而修改中间衬底中的信号路由，这可减少制造成本且提供装置设计的较大灵活性。
所属领域的技术人员将认识到，本文中所描述的方法的适合阶段可在晶片级或在裸片级执行。因此，取决于其使用情境，术语“衬底”可指晶片级衬底或单分的裸片级衬底。此外，除非上下文另有指示，否则可使用半导体制造技术来形成本文中所公开的结构。可例如使用化学气相沉积、物理气相沉积、原子层沉积、镀覆、无电镀覆、旋涂和/或其它适合的技术来沉积材料。类似地，可例如使用等离子蚀刻、湿式蚀刻、化学机械平坦化或其它适合的技术来去除材料。
本文中公开许多具体细节以提供本发明技术的实施例的详尽且有用的描述。然而，所属领域的技术人员应理解，所述技术可具有额外实施例，并且所述技术可在没有下文参考图1A-5所描述的实施例的若干细节的情况下实践。举例来说，已省略所属领域中众所周知的半导体装置和/或封装的一些细节，以免使本发明技术模糊不清。一般来说，应理解，除了本文中所公开的那些具体实施例之外的各种其它装置和系统可在本发明技术的范围内。
如本文中所使用，术语“竖直”、“横向”、“上部”、“下部”、“上方”以及“下方”可鉴于图中所展示的定向而指半导体装置中的特征的相对方向或位置。举例来说，“上部”或“最上部”可指比另一特征更接近页的顶部定位的特征。然而，这些术语应广泛地理解为包含具有其它定向的半导体装置，所述定向例如倒置或倾斜定向，其中顶部/底部、之上/之下、上方/下方、向上/向下，以及左侧/右侧可取决于定向而互换。
图1A为根据本发明技术的实施例配置的半导体装置100(“装置100”)的部分示意性侧横截面视图。装置100包含：第一裸片堆叠102，其包含多个第一裸片104；以及第二裸片堆叠106，其包含多个第二裸片108。装置100还包含支撑第一裸片堆叠102的第一衬底110(例如，封装衬底)，以及支撑第二裸片堆叠106的第二衬底112(例如，中间衬底)。第一裸片堆叠102可安装在第一衬底110上，第二衬底112可安装在第一裸片堆叠102上，并且第二裸片堆叠106可安装在第二衬底112上。装置100还可包含安装在第二衬底112上的第三裸片114。第三裸片114可为被配置成控制第二裸片堆叠106的操作的控制器和/或逻辑裸片(例如，微控制器)，如下文更详细地论述。
第一裸片104、第二裸片108和第三裸片114中的每一个可包含半导体衬底(例如，硅衬底、砷化镓衬底、有机层压衬底等)。在一些实施例中，第一裸片104、第二裸片108和第三裸片114各自包含具有各种类型的半导体组件的前表面和/或有源表面。举例来说，第一裸片104、第二裸片108或第三裸片114中的任一个可包含存储器电路(例如，动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、快闪存储器(例如，NAND、NOR)，或其它类型的存储器电路)、控制器电路(例如，DRAM控制器电路)、逻辑电路、处理电路、电路元件(例如，电线、迹线、互连件、晶体管等)、成像组件，和/或其它半导体特征。任选地，第一裸片104或第二裸片108中的一或多个可为“空白”衬底，其不包含半导体组件，并且由例如结晶、半结晶和/或陶瓷衬底材料形成，这些材料例如硅、多晶硅、氧化铝(Al2O3)、蓝宝石和/或其它适合的材料。
在此类实施例中，装置100为存储器装置，并且第一裸片104和第二裸片108中的一些或全部为存储器裸片(例如，NAND裸片、DRAM裸片、SRAM裸片等)。第一裸片104和第二裸片108可各自为相同类型的存储器裸片。替代地，装置100可为混合存储器装置，其中第一裸片104中的一些或全部为与第二裸片108中的一些或全部不同的存储器裸片类型。举例来说，第一裸片104可各自为第一存储器裸片类型(例如，DRAM)，并且第二裸片108可各自为第二存储器裸片类型(例如，NAND)。任选地，第三裸片114可为用于第二裸片108的存储器控制器(例如，NAND存储器控制器)。然而，在其它实施例中，第一裸片104、第二裸片108和/或第三裸片114可包含其它类型的半导体裸片。
在所说明实施例中，第一裸片堆叠102的第一裸片104和第二裸片堆叠106的第二裸片108各自布置在叠瓦或阶梯式配置中，其中每一裸片从下方的裸片水平地偏移以允许电互连，如下文更详细地论述。虽然图1A将第一裸片堆叠102描绘为包含四个第一裸片104，并且将第二裸片堆叠106描绘为包含八个第二裸片108，但在其它实施例中，第一裸片堆叠102和/或第二裸片堆叠106可各自独立地具有更少或更多裸片(例如，一个、两个、四个、五个、六个、七个、八个、九个、十个或更多裸片)。第一裸片104和/或第二裸片108可以“面朝上”配置堆叠，其中其前表面向上且远离封装衬底110和中间衬底112定向。第三裸片114可以“面朝下”配置定向，其中其前表面向下且朝向中间衬底112定向。然而，在其它实施例中，第一裸片104和/或第二裸片108中的一或多个可呈面朝下配置，和/或第三裸片114可呈面朝上配置。
第一衬底110可为或包含适合于支撑第一裸片堆叠102的任何组件，例如中介层、印刷电路板、堆积再分布层(RDL)、电介质间隔件、另一半导体裸片(例如，逻辑裸片)或另一适合的封装衬底。在一些实施例中，第一衬底110包含额外半导体组件(例如，经掺杂硅晶片或砷化镓晶片)、不导电组件(例如，各种陶瓷衬底，例如氧化铝(Al2O3)等)、氮化铝，和/或导电部分(例如，互连电路系统、TSV等)。第一衬底110可耦合到导电元件或接触件116(例如，焊球、导电凸块、导电支柱、导电环氧树脂和/或其它适合的导电元件)，所述导电元件或接触件被配置成将装置100电耦合到外部装置(未展示)，例如如下文中进一步论述的主机装置。
图1B为第一衬底110的部分示意性侧横截面视图。第一衬底110可包含多个离散层。在所说明实施例中，例如，第一衬底110包含三个功能和/或金属层：第一信号路由层132、电源和/或接地屏蔽层134，以及第二信号路由层136。电源和/或接地屏蔽层134可定位在第一信号路由层132与第二信号路由层136之间。另外，第一衬底110可包含功能和/或金属层之间的额外绝缘材料层，例如第一信号路由层132与电源和/或接地屏蔽层134之间的第一绝缘层133，以及电源和/或接地屏蔽层134与第二信号路由层136之间的第二绝缘层135。然而，在其它实施例中，可按需要改变第一衬底110中的层的数目和/或布置。第一衬底110的层132-136中的一些或全部可包含用于将信号发射到装置100的各种组件(例如，第一裸片堆叠102)和/或从所述各种组件发射信号的路由元件(例如，为了简单起见而省略的导电组件，例如迹线、接合垫、通孔等)，如下文更详细地描述。
再次参考图1A，第一裸片堆叠102可经由多个第一电连接器118电耦合到第一衬底110。在所说明实施例中，第一电连接器118被描绘为将个别第一裸片104连接到彼此和/或连接到第一衬底110的多个焊线。替代地或组合地，第一电连接器118可包含其它类型的连接元件，例如硅通孔(TSV)、互连结构(例如，凸块、微凸块、支柱、柱、立柱等)，和/或所属领域的技术人员已知的任何其它裸片到裸片或裸片到衬底互连元件。
在一些实施例中，第一裸片堆叠102经由通过第一电连接器118、第一衬底110和导电元件116路由的信号与外部装置(例如，图1A中未展示的主机装置)通信。第一衬底110可包含一或多个路由元件(例如，信号迹线、接合垫、通孔等，如先前参考图1B所描述)，以将信号从第一裸片堆叠102和第一电连接器118发射到导电元件116，且反之亦然。举例来说，第一电连接器118中的至少一些可连接到第一衬底110上的接合垫(未展示)，并且第一衬底110的路由元件可将每一接合垫连接到对应导电元件116。第一衬底110、导电元件116和电连接器118还可将电力从外部电源发射到第一裸片堆叠102。
第二衬底112可经由裸片附接膜和/或所属领域的技术人员已知的其它适合的技术耦合到第一裸片堆叠102(例如，耦合到第一裸片堆叠102中的最上部第一裸片104)。第二衬底112可直接安装到第一裸片堆叠102上，而无任何介入间隔件、中介层、裸片或其它支撑结构。第二衬底112可为适合于支撑第二裸片堆叠106的任何组件，例如中介层、印刷电路板、电介质间隔件、堆积RDL、另一半导体裸片(例如，逻辑裸片)，或另一适合的有机或无机衬底。第二衬底112可由与第一衬底110相同或类似的材料制成，或可由不同材料制成。任选地，第二衬底112的材料可经选择以减少或最小化与第一衬底110的热膨胀系数(CTE)失配，例如，在制造和/或操作期间减少装置100上的热机械应力。
图1C为第二衬底112的部分示意性侧横截面视图。第二衬底112可包含多个离散层。在所说明实施例中，例如，第二衬底112包含两个功能和/或金属层：信号路由层142和电源和/或接地屏蔽层144。电源和/或接地屏蔽层144可定位在信号路由层142下方。第二衬底112可进一步包含信号路由层142与电源和/或接地屏蔽层144之间的绝缘层143。然而，在其它实施例中，可按需要改变第二衬底112中的层的数目和/或布置。第二衬底112的层142-144中的一些或全部可包含用于将信号发射到装置100的各种组件(例如，所述第二裸片堆叠106和/或第三裸片114)和/或从所述各种组件发射信号的路由元件(例如，为了简单起见而省略的迹线、通孔、接合垫等)，如下文更详细地描述。
再次参考图1A，第二裸片堆叠106可经由多个第二电连接器120电耦合到第二衬底112。第二电连接器120可与第一电连接器118相同或大体上类似。在所说明实施例中，例如，第二电连接器120包含将个别第二裸片108连接到彼此和/或连接到第二衬底112的多个焊线。然而，在其它实施例中，可使用其它类型的裸片到裸片或裸片到衬底互连技术。
第三裸片114可通过多个互连结构122(例如，凸块、微凸块、支柱、柱、立柱等)安装在第二衬底112上。在一些实施例中，第三裸片114以面朝下配置附接到第二衬底112，其中互连结构122将第三裸片114的有源表面电耦合到第二衬底112。互连结构122可任选地由底部填充材料(为了简单起见在图1A中省略)包围。例如，相较于其中第三裸片114位于与第一裸片堆叠102相同的衬底上的装置，第二衬底112上的第三裸片114的位置可提供用于在制造过程期间在互连结构122周围引入底部填充材料的更多容限。然而，在其它实施例中，第三裸片114可以面朝上配置安装(例如，使用裸片附接膜)，并且可经由焊线或其它电连接器电耦合到第二衬底112。如图1A中所展示，装置100可不包含第三裸片114与第二衬底112之间的任何介入间隔件、支撑、其它裸片等。
第二衬底112可包含一或多个路由元件(例如，信号迹线、接合垫、通孔等，如先前参考图1C所描述)，以在第二裸片堆叠106与第三裸片114之间传达信号。举例来说，第二电连接器120和互连结构122中的至少一些可连接到第二衬底112上相应接合垫(未展示)，并且第二衬底112的路由元件可将个别接合垫连接到彼此。因此，第三裸片114可经由第二衬底112与第二裸片堆叠106通信，例如，以控制第二裸片108的操作。
第二衬底112可通过至少一个第三电连接器124(例如，一或多个焊线)电耦合到第一衬底110。第三电连接器124可将信号从第二裸片堆叠106和/或第三裸片114路由到第一衬底110，所述第一衬底继而可将信号路由到外部装置(例如，经由第一衬底110的路由元件以及导电元件116)。相反地，来自外部装置的信号可经由导电元件116、第一衬底110、第三电连接器124和第二衬底112发射到第二裸片堆叠106和/或第三裸片114。导电元件116、第一衬底110、第三电连接器124和第二衬底112还可将电力从外部电源发射到第二裸片堆叠106和/或第三裸片114。任选地，第一裸片堆叠102可经由路由通过第一衬底110、第三电连接器124和第二衬底112的信号与第二裸片堆叠106和/或第三裸片114通信。
在一些实施例中，第二衬底112包含大部分或全部用于第二裸片堆叠106与第三裸片114之间的通信的信号路由路径，和/或第一衬底110包含很少或不包含用于第二裸片堆叠106与第三裸片114之间的通信的信号路由路径。类似地，在一些实施例中，第一衬底110包含大部分或全部用于第一裸片堆叠102与外部装置之间的通信的信号路由路径，和/或第二衬底112包含很少或不包含用于第一裸片堆叠102与外部装置之间的通信的信号路由路径。因此，第一裸片堆叠102和第二裸片堆叠106可彼此电隔离，因为其相应信号路由路径彼此解耦并跨越不同衬底分布。
任选地，第一衬底110和/或第二衬底112可包含用于外部装置与第三裸片114之间的通信和/或外部装置与第二裸片堆叠106之间的通信的信号路由路径。这些信号路由路径可与用于外部装置与第一裸片堆叠102之间的通信的信号路由路径不同和/或分开(例如，与所述信号路由路径电隔离)。举例来说，第一衬底110可包含用于与外部装置通信的多个外部接触件(例如，其可为或包含导电元件116)，第一裸片堆叠102可电耦合到外部接触件的第一子集，并且第二裸片堆叠106和/或第三裸片114可电耦合到外部接触件的第二不同子集。在一些实施例中，第三裸片114电插入第二裸片堆叠106与第二衬底112和/或外部装置之间。在此类实施例中，第二裸片堆叠106不与第二衬底112和/或外部装置直接通信，而是经由路由通过第三裸片114的信号与第二衬底112和/或外部装置间接通信。
第一裸片堆叠102与第二裸片堆叠106之间的电隔离可提供各种优点。举例来说，电隔离可减少在用于第一裸片堆叠102和第二裸片堆叠106的信号路由路径位于同一衬底中的情况下原本可能发生的串扰和/或其它干扰。另外，通过跨越两个不同衬底分离信号路由路径，可减少每一衬底中的路由的量和/或复杂性。举例来说，可减少每一衬底内的路由层的数目，这可减小装置100的整体大小(例如，高度)。在一些实施例中，第一衬底110和/或第二衬底112各自独立地具有不超过六个层、五个层、四个层、三个层或两个层。
此外，因为用于第一裸片堆叠102和第二裸片堆叠106的信号路由路径位于不同衬底中，所以可独立地修改每一衬底中的路由(例如，基于对应裸片堆叠的所要布置和/或功能性)而对另一衬底中的路由几乎无影响或无影响。因此，第一衬底110和第一裸片堆叠102的相同或类似配置可与第二衬底112、第二裸片堆叠106和第三裸片114的许多不同配置一起使用；且反之亦然。此模块化方法可改进设计和制造灵活性，并且减少成本。
如图1A中所展示，装置100可进一步包含模制材料126，其包封第一衬底110、第一裸片堆叠102、第二衬底112、第二裸片堆叠106和/或第三裸片114。模制材料140可为树脂、环氧树脂、基于硅酮的材料、聚酰亚胺或适合于保护装置100的各种组件免于污染物和/或物理损坏的任何其它材料。在一些实施例中，例如，相比于其中装置组件单独地包封且接着组装到单个封装中的封装层叠(POP)配置，第一衬底110、第一裸片堆叠102、第二衬底112、第二裸片堆叠106和/或第三裸片114全部由连续体积的模制材料140包封。
任选地，装置100可包含表面安装组件(图1A中未展示)，例如电容器、电阻器、电感器和/或其它电路元件。表面安装组件可在第一衬底110、第二衬底112或其组合上。多个衬底的使用可提供用于定位表面安装组件的较大空间和灵活性。在一些实施例中，半导体装置100包含例如外部散热器、套管(例如，导热套管)、电磁干扰(EMI)屏蔽组件等其它组件。
如上文所描述，在一些实施例中，装置100为存储器装置且被配置成连接到主机装置，所述主机装置利用存储器以用于信息或其组件的临时或永久性存储。主机装置可为计算装置，例如台式或便携式计算机、服务器、手持式装置(例如，移动电话、平板计算机、数字读取器、数字媒体播放器)，或其某一组件(例如，中央处理单元、协处理器、专用存储器控制器等)。主机装置可为联网装置(例如，交换器、路由器等)、数字图像、音频和/或视频的记录器、交通工具、电器、玩具，或若干其它产品中的任一个。在一些实施例中，主机装置可直接连接到装置100，但在其它实施例中，主机装置可间接连接到装置100(例如，经由联网连接或通过中间装置)。
图2和3说明根据本发明技术的实施例的具有各种裸片堆叠配置的半导体装置。图2和3中所展示的装置可大体上类似于关于图1A-1C所描述的装置100。因此，相似编号用于识别类似或相同组件，并且图2和3中所展示的装置的描述将限于不同于图1A-1C的装置100的那些特征。
图2为根据本发明技术的实施例配置的半导体装置200(“装置200”)的部分示意性横截面视图。装置200可大体上类似于图1A-1C的装置100，不同之处在于装置200包含安装在第二衬底212上的多个裸片堆叠(例如，第二裸片堆叠206a和第三裸片堆叠206b)。虽然所说明实施例展示第二衬底212上的两个裸片堆叠206a-b，但在其它实施例中，装置200可包含第二衬底212上的较大数目个裸片堆叠，例如三个、四个、五个或更多个裸片堆叠。装置200的配置可有利于减少总体封装高度，同时容纳更多裸片。
第二裸片堆叠206a可包含第二裸片208a的集合，并且第三裸片堆叠206b可包含第三裸片208b的集合。第二裸片208a可全部为与第三裸片208b相同的裸片类型，或第二裸片208a中的一些或全部可为与第三裸片208b中的一些或全部不同的裸片类型。在一些实施例中，第二裸片和第三裸片208a-b可为存储器裸片(例如，NAND裸片)。第二裸片堆叠206a可包含与第三裸片堆叠206b相同数目个裸片，或第二裸片堆叠206a可包含与第三裸片堆叠206b不同数目个裸片。虽然图2将第二裸片堆叠和第三裸片堆叠206a-b说明为各自具有四个裸片，但在其它实施例中，第二裸片堆叠和第三裸片堆叠206a-b可各自独立地具有不同数目个裸片(例如，一个、两个、三个、五个、六个、七个、八个或更多个裸片)。
装置200可进一步包含第四裸片214，其可与图1A的第三裸片114相同或类似。举例来说，第四裸片214可为被配置成控制第二裸片堆叠206a和/或第三裸片堆叠206b的操作的控制器和/或逻辑裸片(例如，存储器控制器裸片)。在所说明实施例中，第四裸片214定位在第二裸片堆叠206a与第三裸片堆叠206b之间的第二衬底212上。然而，在其它实施例中，第四裸片214可在第二衬底212上的不同位置处(例如，到与第二和/或第三裸片堆叠206a-b横向间隔开的位置)。
第二裸片堆叠和第三裸片堆叠206a-b可分别经由第二电连接器220a(例如，第二焊线)和第三电连接器220b(例如，第三焊线)电耦合到第二衬底212。因此，第四裸片214可经由第二衬底212中的路由元件与第二裸片堆叠和第三裸片堆叠206a-b通信。任选地，第二裸片堆叠和第三裸片堆叠206a-b还可经由第二衬底212的路由元件彼此通信。在一些实施例中，第二衬底212包含大部分或全部用于第二裸片堆叠和第三裸片堆叠206a-b和/或第四裸片214之间的通信的信号路由路径，和/或第一衬底210包含很少或不包含用于第二裸片堆叠和第三裸片堆叠206a-b和/或第四裸片214之间的通信的信号路由路径。
第二衬底212可通过至少一个第四电连接器224(例如，一或多个第四焊线)电耦合到第一衬底210。第四电连接器224可将信号从第二裸片堆叠206a、第三裸片堆叠206b和/或第四裸片214路由到第一衬底210，所述第一衬底继而可将信号路由到外部装置(例如，经由第一衬底210的路由元件以及导电元件216)。相反地，来自外部装置的信号可经由导电元件216、第一衬底210、第四电连接器224和第二衬底212发射到第二裸片堆叠206a、第三裸片堆叠206b和/或第四裸片214。导电元件216、第一衬底210、第四电连接器224和第二衬底212还可将电力从外部电源发射到第二裸片堆叠206a、第三裸片堆叠206b和/或第四裸片214。任选地，第一裸片堆叠202可经由路由通过第一衬底210、第四电连接器224和第二衬底212的信号与第二裸片堆叠206a、第三裸片堆叠206b和/或第四裸片214通信。
图3为根据本发明技术的实施例配置的半导体装置300(“装置300”)的部分示意性横截面视图。装置300可大体上类似于图1A-1C的装置100，不同之处在于装置300包含安装在第一衬底310上的多个裸片堆叠(例如，第一裸片堆叠302a和第三裸片堆叠302b)。虽然所说明实施例展示第一衬底310上的两个裸片堆叠302a-b，但在其它实施例中，装置300可包含第一衬底310上的较大数目个裸片堆叠，例如三个、四个、五个或更多个裸片堆叠。装置300的配置可有利于减少总体封装高度，同时容纳更多裸片。
第一裸片堆叠302a可包含第一裸片304a的集合，并且第三裸片堆叠302b可包含第三裸片304b的集合。第一裸片304a可为与第三裸片304b相同的裸片类型，或第一裸片304a中的一些或全部可为与第三裸片304b中的一些或全部不同的裸片类型。在一些实施例中，第一裸片和第三裸片304a-b中的一些或全部为存储器裸片(例如，DRAM裸片)。第一裸片堆叠302a可包含与第三裸片堆叠302b相同数目个裸片，或第一裸片堆叠302a可包含与第三裸片堆叠302b不同数目个裸片。虽然图3将第一裸片堆叠和第三裸片堆叠302a-b说明为各自具有四个裸片，但在其它实施例中，第一裸片堆叠和第三裸片堆叠302a-b可各自独立地具有不同数目个裸片(例如，一个、两个、三个、五个、六个、七个、八个或更多个裸片)。
在所说明实施例中，第二衬底312安装在第一裸片堆叠和第三裸片堆叠302a-b两者上且跨越其延伸。然而，在其它实施例中，第二衬底312可安装在仅第一裸片堆叠302a或仅第三裸片堆叠302b上。如先前参考图1A-1C所描述，第二衬底312可支撑第二裸片堆叠306和/或第四裸片314(其可与图1A的第三裸片114相同或类似)。
第一裸片堆叠和第三裸片堆叠302a-b可分别经由第一电连接器318a(例如，第一焊线)和第三电连接器318b(例如，第三焊线)电耦合到第一衬底310。因此，第一裸片堆叠和第三裸片堆叠302a-b可经由第一衬底310中的路由元件彼此通信。任选地，第一裸片堆叠和第三裸片堆叠302a-b可经由第一衬底310中的路由元件以及导电元件316与外部装置通信。第一衬底310和导电元件316还可将电力从外部电源发射到第一裸片堆叠和第三裸片堆叠302a-b。在一些实施例中，第一衬底310包含大部分或全部用于第一裸片堆叠和第三裸片堆叠302a-b之间的通信的信号路由路径，和/或第二衬底312包含很少或不包含用于第一裸片堆叠和第三裸片堆叠302a-b之间的通信的信号路由路径。类似地，在一些实施例中，第一衬底310包含大部分或全部用于第一裸片堆叠和第三裸片堆叠302a-b与外部装置之间的通信的信号路由路径，和/或第二衬底312包含很少或不包含用于第一裸片堆叠和第三裸片堆叠302a-b与外部装置之间的通信的信号路由路径。
图4为根据本发明技术的实施例的说明用于制造半导体装置的方法400的流程图。方法400可用于制造本文中所描述的半导体装置中的任一个，例如图1A-3的装置100-300中的任一个。
方法400开始于步骤410，其中通过将多个第一裸片安装在第一衬底上来形成第一组合件。第一裸片(例如，图1A的第一裸片104)可安装在第一衬底(例如，图1A的第一衬底110)上，以便根据所属领域的技术人员已知的技术形成第一裸片堆叠(例如，第一裸片堆叠102)。在一些实施例中，第一组合件包含布置在封装衬底上的竖直堆叠中的多个第一存储器裸片(例如，DRAM裸片)。任选地，第一裸片可组装到第一衬底上的多个裸片堆叠中，例如，如先前参考图3所描述。步骤410还可包含经由焊线或其它电连接器将第一裸片电耦合到第一衬底。在其它实施例中，第一裸片可在方法400的后续步骤中(例如，在下文所描述的步骤430期间或之后)电耦合到第一衬底。
在步骤420处，方法400继续通过将多个第二裸片和第三裸片安装在第二衬底上来形成第二组合件。第二裸片(例如，图1A的第二裸片108)可安装在第二衬底(例如，图1A的第二衬底112)上，以便根据所属领域的技术人员已知的技术形成第二裸片堆叠(例如，第二裸片堆叠106)。任选地，第二裸片可组装到第二衬底上的多个裸片堆叠中，例如，如先前参考图2所描述。第三裸片(例如，图1A的第三裸片114)可在将第二裸片安装在第二衬底上之前、期间或之后安装在第二衬底上。在一些实施例中，第二组合件包含布置在中间衬底上的竖直堆叠中的多个第二存储器裸片(例如，NAND裸片)，以及用于中间衬底上的第二存储器裸片的控制器和/或逻辑裸片。
任选地，步骤410还可将第二裸片电耦合到第二衬底(例如，经由焊线和/或其它电连接器)，和/或将第三裸片电耦合到第二衬底(例如，经由互连结构)。第三裸片可在将第二裸片电耦合到第二衬底之前、期间或之后电耦合到第二衬底。在其它实施例中，第二裸片和/或第三裸片可在方法400的后续步骤中(例如，下文所描述的步骤430期间或之后)电耦合到第二衬底。
在步骤430处，方法400包含将第二组合件安装在第一组合件上。第二组合件可使用所属领域的技术人员已知的任何技术，例如裸片附接膜或其它适合的粘附材料来耦合到第一组合件。任选地，步骤430可进一步包含将第二组合件电耦合到第一组合件，例如，使用桥接第一衬底和第二衬底的焊线和/或其它电连接器。
在步骤440处，方法400包含根据所属领域的技术人员已知的技术用模制材料(例如，图1A的模制材料126)包封第一组合件和第二组合件。第一组合件和第二组合件可在单个过程步骤中包封，使得最终装置为具有包围第一组合件和第二组合件两者的相同模制材料的整体封装。
相较于常规制造过程，方法400可提供各种优点。举例来说，因为第一组合件和第二组合件在单独的过程步骤中制造，所以可在组装最终装置之前独立地测试第一组合件和第二组合件。因此，如果组合件中的一个发生故障或以其它方式不适合使用，则可丢弃且替换个别组合件，而非丢弃整个装置。此方法可减少制造成本和浪费的部分。
具有上文参考图1A-4所描述的特征的半导体装置和/或封装中的任一个可并入到无数更大和/或更复杂的系统中的任一个中，所述系统的代表性实例为图5中示意性地展示的系统500。系统500可包含处理器502、存储器504(例如，SRAM、DRAM、快闪和/或其它存储器装置)、输入/输出装置506，和/或其它子系统或组件508。上文参考图1A-4所描述的半导体裸片和/或封装可包含在图5中所展示的元件中的任一个中。所得系统500可被配置成执行广泛多种适合的计算、处理、存储、感测、成像和/或其它功能中的任一个。因此，系统500的代表性实例包含但不限于，计算机和/或其它数据处理器，例如台式计算机、膝上型计算机、网络家电、手持式装置(例如，掌上型计算机、可穿戴式计算机、蜂窝或移动电话、个人数字助理、音乐播放器等)、平板计算机、多处理器系统、基于处理器的或可编程的消费型电子装置、网络计算机和微型计算机。系统500的额外代表性实例包含灯、相机、交通工具等。关于这些和其它实例，系统500可容纳在单个单元中或例如经由通信网络分布在多个互连单元之上。因此，系统500的组件可包含本地和/或远程存储器储存装置以及广泛多种适合的计算机可读媒体中的任一个。
综上所述，应了解，本文中已经出于说明的目的描述了本技术的具体实施例，但可在不偏离本公开的情况下进行各种修改。因此，本发明不受除所附权利要求书之外的限制。此外，特定实施例的上下文中所描述的新技术的某些方面还可在其它实施例中组合或去除。此外，虽然已在那些实施例的上下文中描述了与新技术的某些实施例相关联的优点，但其它实施例也可展现此类优点，并且并非所有实施例都要呈现此类优点以落入本技术的范围内。因此，本公开和相关联的技术可涵盖未明确地在本文中展示或描述的其它实施例。

Claims (20)

1.一种半导体装置，其包括：
封装衬底；
第一裸片堆叠，其安装在所述封装衬底上，所述第一裸片堆叠包含多个第一存储器裸片；
中间衬底，其安装在所述第一裸片堆叠上，所述中间衬底包含多个路由元件；
第二裸片堆叠，其安装在所述衬底上，所述第二裸片堆叠包含多个第二存储器裸片；
控制器裸片，其安装在所述衬底上，其中所述控制器裸片被配置成经由所述中间衬底的所述路由元件与所述第二裸片堆叠通信；以及
模制材料，其包封所述第一裸片堆叠、所述第二裸片堆叠、所述中间衬底和所述控制器裸片。
2.根据权利要求1所述的半导体装置，其中所述第一存储器裸片中的至少一些为与所述第二存储器裸片中的至少一些不同的存储器裸片类型。
3.根据权利要求2所述的半导体装置，其中所述第一存储器裸片包含多个DRAM裸片，并且所述第二存储器裸片包含多个NAND裸片。
4.根据权利要求1所述的半导体装置，其中所述中间衬底直接耦合到所述第一裸片堆叠中的最上部第一存储器裸片。
5.根据权利要求4所述的半导体装置，其中所述中间衬底经由裸片附接膜耦合到所述最上部第一存储器裸片。
6.根据权利要求1所述的半导体装置，其中：
所述封装衬底包含多个外部封装接触件，
所述第一裸片堆叠电耦合到所述外部封装接触件的第一子集，并且
所述第二裸片堆叠和所述控制器裸片电耦合到所述外部封装接触件的第二子集。
7.根据权利要求1所述的半导体装置，其中所述第一裸片堆叠经由多个第一焊线电耦合到所述封装衬底，并且所述第二裸片堆叠经由多个第二焊线电耦合到所述中间衬底。
8.根据权利要求7所述的半导体装置，其进一步包括将所述中间衬底耦合到所述封装衬底的至少一个焊线。
9.根据权利要求7所述的半导体装置，其中所述封装衬底包含不超过三个功能层。
10.根据权利要求1所述的半导体装置，其进一步包括安装在所述中间衬底上的第三裸片堆叠，所述第三裸片堆叠包含多个第三存储器裸片，其中所述控制器被配置成经由所述衬底的所述路由元件与所述第三裸片堆叠通信。
11.根据权利要求1所述的半导体装置，其进一步包括安装在所述封装衬底上的第三裸片堆叠，其中所述第三裸片堆叠包含多个第三存储器裸片，并且其中所述中间衬底安装在所述第一裸片堆叠和所述第三裸片堆叠两者上。
12.根据权利要求1所述的半导体装置，其中所述控制器裸片电插入在所述第二裸片堆叠与所述封装衬底之间。
13.一种半导体装置，其包括：
封装衬底；
第一裸片堆叠，其安装在所述封装衬底上，所述第一裸片堆叠包含耦合到所述封装衬底的多个DRAM裸片；
中间衬底，其直接安装在所述第一裸片堆叠上，所述中间衬底包含多个路由元件，其中所述中间衬底经由一或多个焊线电耦合到所述封装衬底；
第二裸片堆叠，其安装在所述中间衬底上，所述第二裸片堆叠包含耦合到所述中间衬底的多个NAND裸片；
控制器裸片，其安装在所述中间衬底上，其中所述控制器裸片被配置成经由所述中间衬底的所述路由元件与所述第二裸片堆叠通信；以及
模制材料，其包封所述第一裸片堆叠、所述第二裸片堆叠、所述中间衬底和所述控制器裸片。
14.根据权利要求13所述的半导体装置，其进一步包括：
多个第一焊线，其将所述第一裸片堆叠电耦合到所述封装衬底；以及
多个第二焊线，其将所述第二裸片堆叠电耦合到所述中间衬底。
15.根据权利要求13所述的半导体装置，其中：
所述封装衬底包含多个外部封装接触件，
所述第一裸片堆叠电耦合到所述外部封装接触件的第一子集，并且
所述第二裸片堆叠和所述控制器裸片电耦合到所述外部封装接触件的第二子集。
16.根据权利要求13所述的半导体装置，其中所述封装衬底包含不超过三个功能层，并且所述中间衬底包含不超过两个功能层。
17.根据权利要求13所述的半导体装置，其中所述控制器裸片电插入在所述第二裸片堆叠与所述封装衬底之间。
18.一种用于制造半导体装置的方法，其包括：
通过将多个第一存储器裸片安装在第一衬底上来形成第一组合件；
通过将多个第二存储器裸片和控制器裸片安装在第二衬底上来形成第二组合件，其中所述第二存储器裸片经由所述第二衬底中的路由元件电耦合到所述控制器裸片；
将所述第二组合件安装在所述第一组合件上；以及
在将所述第二组合件安装在所述第一组合件上之后，用模制材料包封所述第一组合件和所述第二组合件。
19.根据权利要求18所述的方法，其进一步包括：
经由多个第一焊线将所述第一存储器裸片电耦合到所述第一衬底；
经由多个第二焊线将所述第二存储器裸片电耦合到所述第二衬底；以及
经由一或多个第三焊线将所述第二衬底电耦合到所述第一衬底。
20.根据权利要求18所述的方法，其中所述第一存储器裸片包含多个DRAM裸片，并且所述第二存储器裸片包含多个NAND裸片。
CN202210386732.3A 2021-04-16 2022-04-13 具有多个衬底和裸片堆叠的半导体装置 Pending CN115224012A (zh)

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