CN104576546B - 半导体封装件及其制造方法 - Google Patents

半导体封装件及其制造方法 Download PDF

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CN104576546B
CN104576546B CN201410566487.XA CN201410566487A CN104576546B CN 104576546 B CN104576546 B CN 104576546B CN 201410566487 A CN201410566487 A CN 201410566487A CN 104576546 B CN104576546 B CN 104576546B
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semiconductor chip
semiconductor
hole
package substrate
package
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CN104576546A (zh
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洪民基
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明提供了一种半导体封装件及其制造方法，在该半导体封装件中，单元阵列区和外围电路区分别形成为不同的半导体芯片。包括存储器单元的第一半导体芯片与仅包括由第一半导体芯片共用的外围电路的第二半导体芯片彼此电连接。因此，半导体封装件的负载电容可减小。结果，半导体封装件的RC延迟可减小，从而提高了半导体封装件的操作速度。

Description

半导体封装件及其制造方法
相关申请的交叉引用
本申请要求于2013年10月22日提交的韩国专利申请No.10-2013-0126140的优先权，该申请的全文以引用方式并入本文中。
背景技术
随着电子工业的发展，对更高性能、更快速度和更小尺寸(紧凑)的电子元件的需求增加。随着这种趋势，当前的半导体封装技术之一是将多个存储器芯片叠堆(例如，安装)在单个封装件衬底上。然而，如果叠堆存储器芯片，则包括叠堆的存储器芯片的所得半导体封装件的输入电容增大，从而导致速度减小。另外，对各个存储器芯片连续重复的裸晶接合工艺和引线接合工艺趋于使得整体工艺复杂。
发明内容
至少一些示例实施例提供了半导体封装件和/或其制造方法。
一种根据示例实施例的半导体封装件包括：封装件衬底；第一半导体芯片，其位于封装件衬底的中心区，第一半导体芯片包括具有外围电路的外围电路区；以及第二半导体芯片，其在封装件衬底上并且叠堆在第一半导体芯片的两侧，第二半导体芯片的每一个包括其中设置有存储器单元的单元阵列区，第一半导体芯片中的外围电路被配置为驱动第二半导体芯片中的存储器单元。
在一些示例实施例中，外围电路区还可包括连接区和位线感测放大器区中的至少一个。
在一些示例实施例中，封装件衬底可包括形成在其中心区中的孔。第一半导体芯片可与孔重叠，并可安装在封装件衬底的底表面上。第二半导体芯片可位于封装件衬底的顶表面上。第一半导体芯片和第二半导体芯片可通过被设置为穿过孔的导线彼此电连接。
在一些示例实施例中，半导体封装件还可包括覆盖第一半导体芯片和第二半导体芯片并填充孔的模制层。
在一些示例实施例中，孔的一部分可通过第一半导体芯片暴露出来。第一半导体芯片的一个侧表面与孔的一个侧表面之间的距离可为约500μm或更大。
在一些示例实施例中，封装件衬底可包括设置在封装件衬底的顶表面上并邻近孔的衬底导电图案。第二半导体芯片可包括位于各个第二半导体芯片的端部的布线导电图案。布线导电图案中的一些可通过导线连接至衬底导电图案。在一些示例实施例中，可将地/电源电压施加至衬底导电图案。
在一些示例实施例中，第二半导体芯片可彼此相同，第一半导体芯片包括第一侧和与第一侧相对的第二侧，并且设置在第一半导体芯片的第一侧的第一组第二半导体芯片和设置在第一半导体芯片的第二侧的第二组第二半导体芯片彼此对称地设置。
在一些示例实施例中，第二半导体芯片可彼此相同，并且设置在第一半导体芯片的第一侧的第二半导体芯片的数量可与设置在第一半导体芯片的与第一侧相对的第二侧的第二半导体芯片的数量不同。
在一些示例实施例中，封装件衬底可以包括位于其中心区的上凹陷部分，并且第一半导体芯片可设置在上凹陷部分中。在这种情况下，封装件衬底还可包括设置在上凹陷部分的底部上的衬底导电图案，并且第一半导体芯片可包括第一芯片导电图案和第二芯片导电图案，第一芯片导电图案和第二芯片导电图案位于第一半导体芯片的顶表面上，第一芯片导电图案可电连接至第二半导体芯片，并且第二芯片导电图案可电连接至衬底导电图案。
在一些示例实施例中，第一半导体芯片可嵌入在封装件衬底中。封装件衬底可包括衬底导电图案和衬底内部互连部分。衬底导电图案可设置在封装件衬底的顶表面上。衬底内部互连部分可设置在封装件衬底中并连接至衬底导电图案。第一半导体芯片和第二半导体芯片可通过衬底导电图案和衬底内部互连部分彼此电连接。
在一些示例实施例中，封装件衬底可包括位于其中心区的下凹陷部分。第一半导体芯片可设置在下凹陷部分中。第一半导体芯片可包括位于其底表面上的芯片导电图案，并且封装件衬底可包括位于其顶表面上的第一衬底导电图案、位于其中的衬底内部互连部分和位于其底表面上的第二衬底导电图案。第二衬底导电图案将衬底内部互连部分与芯片导电图案彼此连接。第一半导体芯片和第二半导体芯片可通过导线、第一衬底导电图案、衬底内部互连部分和第二衬底导电图案彼此电连接。
一种根据另一示例实施例的半导体封装件，包括：封装件衬底；第一半导体芯片，其安装在封装件衬底上，并包括其中设置有外围电路的外围电路区；以及至少一个第二半导体芯片，其安装在封装件衬底上，并包括其中设置有存储器单元的单元阵列区。外围电路可被配置为驱动存储器单元。
一种根据示例实施例的制造半导体封装件的方法，包括步骤：将第一半导体芯片叠堆在封装件衬底上，第一半导体芯片的每一个包括其中设置有存储器单元的单元阵列区；将第二半导体芯片安装在封装件衬底上，第二半导体芯片包括具有外围电路的外围电路区，外围电路用于驱动存储器单元；以及形成导线以将第一半导体芯片与第二半导体芯片彼此电连接。
一种根据另一示例实施例的半导体封装件，包括：封装件衬底；多个第一半导体芯片，每一个第一半导体芯片包括存储器单元；以及第二半导体芯片，其包括被第一半导体芯片共用的外围电路。外围电路被配置为将包括在两个或更多个第一半导体芯片中的存储器单元一起驱动。第一半导体芯片的每一个都不包括被配置为驱动存储器单元的外围电路，并且第二半导体芯片不包括存储器单元。
封装件衬底可包括顶表面、底表面和限定在一个位置处的孔，第一半导体芯片可设置在顶表面上，第二半导体芯片可设置在底表面上并与孔重叠。
第二半导体芯片可设置为不完全覆盖孔。
封装件衬底可包括位于封装件衬底的一个表面上的凹陷部分，并且第二半导体芯片可位于凹陷部分中。
附图说明
通过附图和随后的具体实施方式，本发明的构思将变得更加清楚。以举例而非限制的方式提供图中描绘的示例实施例，其中相同的标号指代相同或相似的元件。附图不一定按照比例绘制，而是重点在于示出本发明构思的各方面。
图1是根据示例实施例的半导体封装件的布局；
图2是沿着图1中的线I-I'截取的剖视图；
图3是通常半导体存储器芯片中的电路区的布局图；
图4示出了指示DRAM器件的单元阵列区中的各种电路块的布局；
图5是图1中的第一半导体芯片的框图；
图6是图1中的第二半导体芯片的框图；
图7示出了如图5所示的多个第一半导体芯片与如图6所示的一个公共的第二半导体芯片之间的关系；
图8至图12是示出制造图2中的半导体封装件的方法的剖视图；
图13示出了根据另一示例实施例的半导体封装件的布局图；
图14是沿着图13中的线II-II'截取的剖视图；
图15至图19是根据其它示例实施例的半导体封装件的剖视图；
图20是示出包括根据示例实施例的半导体封装件的封装模块的示例的框图；
图21是示出包括根据示例实施例的半导体封装件的电子系统的示例的框图；
图22是示出包括根据示例实施例的半导体封装件的存储器系统的示例的框图。
具体实施方式
将参照附图更加详细地描述的以下示例实施例，从中本发明的构思的优点和特征以及实现它们的方法将变得清楚。然而，应该理解，本发明的构思不限于以下示例实施例，而是可按照多种形式实现。因此，提供这些示例实施例仅是为了使得本公开将是彻底和完整的，并且将把示例实施例的范围完全传递给本领域技术人员。
应该理解，当元件或层被称作“位于”另一元件或层“上”、“连接至”或“耦合至”另一元件或层时，其可直接位于另一元件或层上、直接连接至或结合至另一元件或层，或者可存在中间元件或层。相反，当元件被称作“直接位于”另一元件或层“上”、“直接连接至”或“直接耦合至”另一元件或层时，不存在中间元件或层。如本文所用，术语“和/或”包括相关所列项之一或多个的任何和所有组合。在附图中，为了清楚起见，夸大了元件的厚度。
以下将参照作为理想示例实施例(和中间结构)的示意图的剖视图描述本发明的示例实施例。可通过制造技术和/或公差来修改示例附图。因此，示例实施例不应被解释为限于图中示出的特定构造，而是包括例如由制造方法导致的形状的修改。例如，示为直角的蚀刻区可按照圆角形成，或形成为具有期望(或替代性地，预定)的曲率。因此，附图中示出的区具有示意性特征。另外，附图中示出的区的形状是元件中的区的形状的特定示例，并且不限于此。虽然，使用像第一、第二和第三的术语在各个示例实施例中描述各个元件，但是所述元件不由这些术语限制。这些术语仅用于将一个元件与另一元件区分开。本文描述的示例实施例包括其补充实施例。
说明书中使用的术语仅是为了描述特定示例实施例而非旨在限制示例实施例。如说明书中所用，除非本文中清楚指明不是这样，否则单数形式“一个”、“一”和“该”也旨在包括复数形式。还应该理解，术语“包括”和/或“包括……的”当用于本说明书中时，指明存在所列特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或它们的组。
为了方便描述，本文中可使用诸如“在……下方”、“在……之下”、“下”、“在……之上”、“上”等的空间相对术语，以描述附图中所示的一个元件或特征与其它元件或特征的关系。应该理解，除图中所示的取向之外，空间相对术语还旨在涵盖使用或操作中的装置的不同取向。例如，如果图中的装置颠倒，则被描述为“在其它元件之下”或“在其它元件下方”的元件将因此被取向为“在其它元件或特征之上”。这样，示例术语“在……之下”可涵盖在……之上和在……之下这两个取向。装置可按照其它方式取向(旋转90度或位于其它取向)，并且本文所用的空间相对描述语将相应地解释。
除非另外限定，否则本文中使用的所有术语(包括技术和科学术语)具有与本发明所属领域的普通技术人员之一通常理解的含义相同的含义。还应该理解，除非本文中明确这样定义，否则诸如在通用词典中定义的那些的术语应该被解释为具有与它们在相关技术的上下文中的含义一致的含义，而不应该理想化地或过于正式地解释它们。
虽然未示出一些剖视图的对应的平面图和/或透视图，但是本文示出的器件结构的剖视图针对沿着平面图中将示出的两个不同方向和/或沿着透视图中将示出的三个不同方向延伸的多个器件结构提供了支持。所述两个不同方向可以或可以不彼此正交。所述三个不同方向可包括可以与所述两个不同方向正交的第三方向。所述多个器件结构可集成在相同电子装置中。例如，当在剖视图中示出一个器件结构(例如，存储器单元结构或晶体管结构)时，电子装置可包括多个所述器件结构(例如，存储器单元结构或晶体管结构)，如将通过电子装置的平面图示出的那样。所述多个器件结构可按照阵列和/或按照二维图案排列。
下文中，现在将参照附图更加完全地描述一些示例实施例。
图1是根据示例实施例的半导体封装件100的布局，图2是沿着图1中的线I-I'截取的剖视图。在半导体封装件100中，封装件衬底1具有形成在其中心的孔3。孔3可为沿一个方向延伸的条状形式。第一衬底导电图案5a和第二衬底导电图案5b设置在封装件衬底1的底表面上。封装件衬底1可为单层或多层印刷电路板(PCB)。第一半导体芯片10按顺序叠堆在封装件衬底1上，以与孔3相邻。粘合剂层7设置在第一半导体芯片10之间以及最下面的第一半导体芯片10与半导体衬底1之间。第一半导体芯片10的边缘形成台阶形状。第一布线导电图案至第三布线导电图案12a、12b和12c分别设置在第一半导体芯片10的端部。
第二半导体芯片20安装在封装件衬底1的底表面上。安装第二半导体芯片20以与孔3重叠。孔3的一部分可被暴露出来，而不被第二半导体芯片20覆盖。半导体芯片20的一个侧表面与孔3的一个侧表面(在该侧表面处，孔3不被第二半导体芯片20覆盖)之间的距离D1可为500微米或更大。
第一芯片导电图案至第四芯片导电图案22a、22b、22c和22p设置在第二半导体芯片20的一个表面上。第四芯片导电图案22p电连接至第二衬底导电图案5b。虽然未示出，但是可在第四芯片导电图案22p与第二衬底导电图案5b之间设置焊料球。第二半导体芯片20可按照倒装芯片接合法安装在封装件衬底1的底表面上。第一芯片导电图案至第三芯片导电图案22a、22b和22c可通过孔3暴露出来。外部焊料球34可附着至第一衬底导电图案5a。
第一布线导电图案12a和第一芯片导电图案22a可设置在第一区“A”中。设置在一列上的第一布线导电图案12a和第一芯片导电图案22a可通过单根导线30连接。第一布线导电图案12a和第一芯片导电图案22a可各自对应于接地引脚或电源引脚。
第二布线导电图案12b和第二芯片导电图案22b可设置在第二区“B”中。设置在一列上的第二布线导电图案12b和第二芯片导电图案22b可通过单根导线30连接。第二布线导电图案12b和第二芯片导电图案22b可各自对应于数据引脚、地址引脚或命令引脚。
第三布线导电图案12c和第三芯片导电图案22c可设置在第三区“C”中。第三布线导电图案12c的每一个和第三芯片导电图案22c的每一个可通过单根导线30连接。第三布线导电图案12c和第三芯片导电图案22c可各自对应于芯片启用(enable)引脚。
例如，设置在第二半导体芯片20的一侧的一组第一半导体芯片10和设置在第二半导体芯片20的另一侧(与第一侧相对)的另一组第一半导体芯片10关于穿过封装件衬底1的中心的竖直轴线彼此对称地设置。第一半导体芯片10可各自对应于包括相同或相似的存储器单元的存储器单元芯片。第二半导体芯片20可对应于包括用于驱动存储器单元的外围电路的外围电路芯片。现在，以下将详细描述这一点。
图3是典型半导体存储器芯片的电路区的布局图。
参照图3，存储器芯片150可包括单元阵列区CA和外围电路区PERI。多个存储器单元可设置在单元阵列区CA中。外围电路区PERI可包括各种电路，例如解码器电路和驱动器电路，以驱动存储器单元。存储器芯片150可为例如相变随机存取存储器(PRAM)、电阻式RAM(RRAM)、磁性RAM(MRAM)、动态RAM(DRAM)或闪速存储器装置。根据存储器芯片150的类型，存储器单元可包括电阻器、电容器或电荷俘获层。
图4示出了指示DRAM器件的单元阵列区中的各种电路块的布局。
参照图4，在存储器芯片150是DRAM的情况下，单元阵列区CA包括多个存储块BLK，每个存储块BLK包括：多个存储器单元；位线感测放大器区BLSA，其设置在存储块BLK的一侧；子字线驱动器区SWD，其设置在存储块BLK的不与存储块BLK的所述一侧相对的另一侧；和连接区CJ，其位于存储块BLK的角落，例如位线感测放大器区BLSA与子字线驱动器区SWD之间。
位线感测放大器区BLSA是其中设置了位线感测放大器的区，并且位线感测放大器用于感测和放大存储在存储器单元中的数据并将所述数据的值传输至外部实体。子字线驱动器可设置在子字线驱动器区SWD中以控制施加至存储器单元的字线的电压。连接区CJ是其中子字线驱动器区SWD与位线感测放大器区BLSA彼此交叉的区。例如，可适当地将内部电压驱动器(未示出)、位线均衡器(未示出)和/或字线驱动电路(未示出)设置在连接区CJ中。内部电压驱动器对用作位线感测放大器的电压源的内部电压的供应进行控制。
存储器芯片150包括单元阵列区CA和外围电路区PERI二者，如图3所示。
根据示例实施例，单元阵列区CA和外围电路区PERI相对于各个芯片分离。例如，第一半导体芯片10包括单元阵列区CA而不包括外围电路区PERI(见图5)，而第二半导体芯片20包括外围电路区PERI而不包括单元阵列区CA(见图6)。在第一半导体芯片10包括DRAM的存储器单元的情况下，第二半导体芯片20还可包括连接区CJ和位线感测放大器区BLSA中的至少一个，其被包括在典型DRAM芯片的单元阵列区CA中(见图4)。
图7示出了如图5所示的多个第一半导体芯片与如图6所示的一个公共的第二半导体芯片之间的关系。
参照图1、图2和图7，可通过包括公共外围电路区PERI的第二半导体芯片20将电信号发送至八个第一半导体芯片10的单元阵列区CA中的存储器单元。因此，电信号通过一个(对应于第二半导体芯片20的)公共接口，以访问八个第一半导体芯片10的存储器单元。因此，除半导体封装件100的输入电容之外，包括第一半导体芯片10和第二半导体芯片20的半导体封装件100还经受与单个半导体芯片(例如，第二半导体芯片20)关联的电容。结果，半导体封装件的输入电容可减小。因此，可减小RC延迟，从而实现更高的速度。
不同的是，在如图3所示的典型半导体存储器芯片150竖直叠堆(并且并联地连接)在封装件衬底1上的情况下，信号经过包括在对应的存储器芯片150中的外围电路区PERI，以被发送至包括在对应的存储器芯片150中的存储器单元。因此，除封装件衬底的输入电容以外，半导体封装件的输入电容还包括对应的存储器芯片150的电容。因此，如果八个相同的存储器芯片150竖直地叠堆并安装在单个半导体封装件中，则单个半导体封装件的输入电容等于封装件衬底的输入电容与对应的八个存储器芯片160的电容之和。因此，半导体封装件的输入电容值会增大。因此，会增大RC延迟，从而难以实现更高的速度。
通过提供各自包括相同或相似的单元阵列区CA的第一半导体芯片10和包括外围电路区PERI的第二半导体芯片20，不管包括存储器单元的第一半导体芯片20的数量是否增加，都可提高半导体封装件100的信号传输速度。
另外，包括在根据示例实施例的半导体封装件100中的半导体芯片10和20不具有硅通孔。因此，不需要执行形成再分布线的处理，从而减小了工艺成本。
图8至图12是示出制造图2中的半导体封装件的方法的剖视图。
参照图8，所述方法始于其中形成有孔3的封装件衬底1的制备。第一衬底导电图案5a和第二衬底图案5b设置在封装件衬底1的底表面上。
参照图9，利用粘合剂层7将第一半导体芯片10按顺序附着至封装件衬底1上。半导体芯片10的边缘可按照台阶式叠堆。第一布线导电图案至第三布线导电图案12a、12b和12c可在第一半导体芯片10的端部上暴露出来。例如，第一半导体芯片10可为包括其中设置有存储器单元的单元阵列区CA的存储器芯片。
参照图10，第二半导体芯片20安装在封装件衬底1的底表面上。第二半导体芯片20可包括设置在半导体芯片20的一个表面上的第一芯片导电图案至第四芯片导电图案22a、22b、22c和22p。可通过倒装芯片接合安装第二半导体芯片20。例如，第二半导体芯片20可对应于包括外围电路区PERI的外围电路芯片。第二半导体芯片20可至少部分地与孔3重叠。因此，孔3可不被半导体芯片20完全覆盖。如参照图1的描述，半导体芯片20的一个侧表面与孔3的一个侧表面(在该侧表面处，孔3不被第二半导体芯片20覆盖)之间的距离D1可为50微米或更多。
参照图11，通过执行引线接合工艺，分别将布线导电图案12a、12b和12c通过导线30连接至芯片导电图案22a、22b和22c。根据示例实施例，可以在第一半导体芯片10全部附着之后，一次地执行引线接合工艺。因此，可简化制造半导体封装件的方法。在制造其中叠堆有典型存储器芯片的半导体封装件的典型方法中，可关于各个存储器芯片(例如按照叠堆的存储器芯片的数量)重复执行附着工艺和引线接合工艺。
参照图12，通过执行模制处理形成模制层32以覆盖第一半导体芯片10、封装件衬底1和第二半导体芯片20。如果半导体芯片20的一个侧表面与孔3的一个侧表面(在该侧表面处，孔3不被第二半导体芯片20覆盖)之间的距离D1为500微米或更大，则用于形成模制层的树脂溶液可通过孔3平稳地流至第二半导体芯片20的侧表面和底表面。如果距离D1小于500微米，则用于形成模制层的树脂溶液流可能不平稳，因此可能在模制层32中形成空隙等。
返回参照图2，外部焊料球34附着至第一衬底导电图案5a。可执行切分工艺以将半导体封装件分为单独的半导体封装件。
图13示出了根据另一示例实施例的半导体封装件101的布局图，并且图14是沿着图13中的线II-II'截取的剖视图。在半导体封装件101中，可在封装件衬底1的顶表面上设置第三衬底导电图案5c。第三衬底导电图案5c可以设置为与第一区“A”重叠。最下面的第一半导体芯片10的侧表面可与孔3的侧表面分离开，以暴露出第三衬底导电图案5c。各自对应于接地引脚或电源引脚的第一布线导电图案12a中的一些可不连接至第二半导体芯片20的第一芯片导电图案22a，而是可通过导线30连接至第三衬底导电图案5c。因此，除第二半导体芯片20之外，外部地/电源电压可通过第一衬底内部互连部分24a和第三衬底导电图案5c施加至第一布线导电图案12a中的一些。其它组件可与参照图1和图2说明的那些相同/相似。
图15是根据另一示例实施例的半导体封装件102的剖视图。在半导体封装件102中，叠堆在第二半导体芯片20的两侧上的第一半导体封装件10的数量可彼此不同。其它组件可与参照图1和图2说明的那些相同/相似。
图16是根据另一示例实施例的半导体封装件103的剖视图。在半导体封装件103中，可在封装件衬底1上设置上凹陷部分3a(替代孔)。第二衬底导电图案5b可设置在上凹陷部分3a的底部上。另外，第二半导体芯片20可设置在上凹陷部分3a中，并可通过介于它们之间的粘合剂层7附着至上凹陷部分3a的底部上。第二半导体芯片20的第四芯片导电图案22p通过导线30连接至第二衬底导电图案5b。模制层32覆盖封装件衬底1、第一半导体芯片10和第二半导体芯片20，并填充上凹陷部分3a。其它组件可与参照图2说明的那些相同/相似。
图17是根据另一示例实施例的半导体封装件104的剖视图。在半导体封装件104中，第二半导体芯片20嵌入在封装件衬底1中。第一衬底导电图案5a设置在封装件衬底1的底表面上，并且外部焊料球34附着至第一衬底导电图案5a。第二衬底导电图案5b设置在封装件衬底1的中心顶表面上。第一半导体芯片10的第一布线导电图案至第三布线导电图案12a、12b和12c通过导线30连接至第二衬底导电图案5b。第一半导体芯片10通过第二衬底导电图案5b和第一衬底内部互连部分24a电连接至第二半导体芯片20。第二半导体芯片20通过第二衬底内部互连部分24p电连接至外部焊料球34。其它组件可与参照图2说明的那些相同/相似。
图18是根据另一示例实施例的半导体封装件105的剖视图。在半导体封装件105中，封装件衬底1包括下凹陷部分3b，并且第二半导体芯片20插入于下凹陷部分3b中。封装件衬底1具有其上设置有第一衬底导电图案5a和第二衬底导电图案5b的底表面以及其上设置有第三衬底导电图案5c的顶表面。第一导电芯片10的第一布线导电图案至第三布线导电图案12a、12b和12c通过导线30连接至第三衬底导电图案5c。第三衬底导电图案5c通过第一衬底内部互连部分24a、第二衬底导电图案5b和第一芯片导电图案22a电连接至第二半导体芯片20。其它组件可与参照图2说明的那些相同/相似。
图19是根据另一示例实施例的半导体封装件106的剖视图。在半导体封装件106中，封装件衬底1不包括孔或凹陷部分。第一衬底导电图案5a设置在封装件衬底1的底表面上，并且外部焊料球34附着至第一衬底导电图案5a。第二衬底导电图案5b设置在封装件衬底1的顶表面上。第二半导体芯片20附着至封装件衬底1上，并且半导体芯片10以台阶方式叠堆在第二半导体芯片20上。第一芯片导电图案至第三芯片导电图案22a、22b和22c设置在第二半导体芯片20的端部，并且第一布线导电图案至第三布线导电图案12a、12b和12c设置在第一半导体芯片10的端部。第一布线导电图案至第三布线导电图案12a、12b和12c、第一芯片导电图案至第三芯片导电图案22a、22b和22c以及第二衬底导电图案5b分别通过导线30连接。其它组件可与参照图2说明的那些相同/相似。
图20是示出包括根据示例实施例的半导体封装件的封装模块的示例的框图。如图所示，封装模块1200可包括半导体集成电路芯片1220和以方形扁平封装(QFP)所封装的半导体集成电路芯片1230，其中的一些应用了根据示例实施例的半导体封装技术。可通过将半导体元件1220和1230安装在衬底1210上形成封装模块1200。封装模块1200可通过设置在衬底1210的一侧的外部连接端子1240连接至外部电子装置。
根据示例实施例的半导体封装技术可应用于电子系统。图21是示出包括根据示例实施例的半导体封装件的电子系统的示例的框图。如图所示，电子系统1300可包括控制器1310、输入/输出(I/O)装置1320和存储器装置1330。控制器1310、I/O装置1320和存储器装置1330可通过总线1350连接。总线1350可为数据通过其传输的路径。例如，控制器1310可包括例如至少一个微处理器、数字信号处理器、微控制器或执行相似功能的至少一个逻辑器件。控制器1310和存储器装置1330可包括根据示例实施例的半导体封装件。I/O装置1320可包括例如键区、键盘和/或显示装置。存储器装置1330可包括例如易失性存储器装置和/或非易失性存储器装置。例如，存储器装置1330可由闪速存储器装置形成。例如，包括闪速存储器装置并根据示例实施例形成的半导体封装件可安装在例如移动装置或台式计算机的数据处理系统上。包括在半导体封装件中的闪速存储器装置可被配置为形成固态盘(SSD)。在这种情况下，电子系统1300可在闪速存储器中稳定地存储大量数据。电子系统1300还可包括用于将数据发送至通信网络/从通信网络接收数据的接口1340。接口1340可为有线/无线接口。例如，接口1340可包括例如天线或有线/无线收发器。虽然未示出，但是本领域技术人员应该清楚，在电子系统1300中还可设置例如应用芯片集、相机图像处理器(CIS)和/或I/O装置。
电子系统1300可被例如移动系统、个人计算机、工业计算机或执行各种功能的逻辑系统采用。例如，所述移动系统可包括个人数字助理(PDA)、便携式计算机、网络平板、移动电话、无线电话、笔记本计算机、存储卡、数字音乐系统和信息发送/接收系统中的任一个。当电子系统1300是可无线通信的设备时，电子系统1300可用于第三代通信系统的通信接口协议中，所述第三代通信系统的通信接口协议例如码分多址(CDMA)、全球移动通信系统(GSM)、北美数字蜂窝网(NADC)、扩展时分多址(E-TDMA)、宽带码分多址(WCDMA)或CDMA2000。
根据示例实施例的半导体封装件可按照存储卡的形式提供。图22是示出包括根据示例实施例的半导体封装件的存储器系统的示例的框图。如图所示，存储卡1400可包括非易失性存储器装置1410和存储器控制器1420。非易失性存储器装置1410和存储器控制器1420可在其中存储数据或读取存储的数据。非易失性存储器装置1410可包括嵌入在根据示例实施例的半导体封装件中的两个或更多个非易失性存储器芯片。存储器控制器1410可响应于主机的读/写请求来控制非易失性存储器装置1410读取存储的数据或存储数据。
如前所述，在根据示例实施例的半导体封装件中，单元阵列区和外围电路区分离以分别形成为不同的半导体芯片。包括单元阵列区的多个第一半导体芯片和包括外围电路区的单个第二半导体芯片彼此电连接。因此，半导体封装件的输入电容包括关于第二半导体芯片的负载电容，但不经受关于对应的第一半导体芯片的负载电容，从而使得单负载成为可能。结果，半导体封装件的输入电容可减小。因此，RC延迟可减小，从而实现更高的速度。另外，在制造根据示例实施例的半导体封装件的方法中，可仅执行一次引线接合工艺，从而实现工艺简化。
虽然已经参照上面描述的一些示例实施例具体示出和描述了示例实施例，但是本领域普通技术人员应该清楚，在不脱离由权利要求限定的示例实施例的精神和范围的情况下，可在其中作出形式和细节上的各种修改。

Claims (12)

1.一种半导体封装件，包括：
封装件衬底；
第一半导体芯片，其位于所述封装件衬底的中心区，所述第一半导体芯片包括具有外围电路的外围电路区；以及
多个第二半导体芯片，其位于所述封装件衬底上并位于所述封装件衬底的第一区和第二区上，所述多个第二半导体芯片的每一个包括其中设置有存储器单元的单元阵列区，所述第一半导体芯片中的所述外围电路被配置为驱动所述多个第二半导体芯片中的所述存储器单元，
其中，
所述封装件衬底包括形成在其中心区的孔，
所述第一半导体芯片与所述孔重叠，
其中，所述孔设置在所述封装件衬底的所述第一区和所述第二区之间，
所述多个第二半导体芯片位于所述封装件衬底的顶表面上，所述孔为沿一个方向延伸的条状，并且
所述孔的垂直于所述顶表面并且垂直于所述一个方向的一个侧表面与所述第一半导体芯片的靠近所述孔的所述一个侧表面的垂直于所述顶表面并且垂直于所述一个方向的一个侧表面之间的距离,使得所述第一半导体芯片不完全覆盖所述孔，
所述第一半导体芯片安装在所述封装件衬底的底表面上，
所述孔贯穿所述顶表面和所述底表面。
2.根据权利要求1所述的半导体封装件，其中，所述外围电路区还包括连接区和位线感测放大器区中的至少一个。
3.根据权利要求1所述的半导体封装件，其中，
所述第一半导体芯片和所述第二半导体芯片通过被设置为穿过所述孔的导线彼此电连接。
4.根据权利要求3所述的半导体封装件，还包括：
模制层，其覆盖所述第一半导体芯片和所述第二半导体芯片，并填充所述孔。
5.根据权利要求3所述的半导体封装件，其中，
所述孔的一部分被所述第一半导体芯片暴露出来，并且
所述第一半导体芯片的所述一个侧表面与所述孔的所述一个侧表面之间的距离为500㎛或更大。
6.根据权利要求3所述的半导体封装件，其中，
所述封装件衬底包括位于所述封装件衬底的顶表面上并邻近所述孔的衬底导电图案，
所述第二半导体芯片包括位于各个第二半导体芯片的端部的布线导电图案，并且
所述布线导电图案中的一些通过导线连接至所述衬底导电图案。
7.根据权利要求6所述的半导体封装件，其中，将地/电源电压施加至所述衬底导电图案。
8.根据权利要求1所述的半导体封装件，其中，
所述第二半导体芯片彼此相同，
所述第一半导体芯片包括第一侧和与所述第一侧相对的第二侧，并且
位于所述第一半导体芯片的第一侧的第一组第二半导体芯片和位于所述第一半导体芯片的第二侧的第二组第二半导体芯片关于穿过所述封装件衬底的中心的竖直轴线彼此对称地设置。
9.根据权利要求1所述的半导体封装件，其中，
所述第二半导体芯片彼此相同，并且
位于所述第一半导体芯片的第一侧的第二半导体芯片的数量与位于所述第一半导体芯片的第二侧的第二半导体芯片的数量不同，所述第一半导体芯片的第二侧与所述第一半导体芯片的第一侧相对。
10.一种半导体封装件，包括：
封装件衬底；
第一半导体芯片，其位于所述封装件衬底上，所述第一半导体芯片包括具有外围电路的外围电路区；以及
多个第二半导体芯片，其位于所述封装件衬底上，所述多个第二半导体芯片中的每一个包括具有存储器单元的单元阵列区，并且所述外围电路被配置为驱动所述多个第二半导体芯片中的存储器单元，
其中，
所述封装件衬底包括形成在其上的孔，
所述第一半导体芯片与所述孔重叠，
所述多个第二半导体芯片位于所述封装件衬底的顶表面上，所述孔在平面图中沿一个方向延伸，并且
所述孔的一个侧表面与所述第一半导体芯片的一个侧表面之间的距离,使得所述第一半导体芯片不完全覆盖所述孔，
其中，所述孔的所述一个侧表面垂直于所述封装件衬底的所述顶表面并且垂直于所述一个方向，
其中，所述第一半导体芯片的所述一个侧表面垂直于所述封装件衬底的所述顶表面并且垂直于所述一个方向，
其中，所述第一半导体芯片的所述一个侧表面靠近所述孔的所述一个侧表面，
其中，所述孔的端部被所述第一半导体芯片暴露，
其中，所述第一半导体芯片安装在所述封装件衬底的底表面上，
其中，所述孔贯穿所述顶表面和所述底表面。
11.一种制造半导体封装件的方法，包括步骤：
将多个第一半导体芯片叠堆在封装件衬底上，所述多个第一半导体芯片的每一个包括其中设置有存储器单元的单元阵列区；
将第二半导体芯片安装在所述封装件衬底上，所述第二半导体芯片包括具有外围电路的外围电路区，所述外围电路用于驱动所述多个第一半导体芯片中的存储器单元；以及
形成导线以将所述多个第一半导体芯片与所述第二半导体芯片彼此电连接
其中，
所述封装件衬底包括形成在其上的孔，
所述第二半导体芯片与所述孔重叠，
所述多个第一半导体芯片位于所述封装件衬底的顶表面上，所述孔为沿一个方向延伸的条状，并且
所述孔的垂直于所述顶表面并且垂直于所述一个方向的一个侧表面与所述第二半导体芯片的靠近所述孔的所述一个侧表面的垂直于所述顶表面并且垂直于所述一个方向的一个侧表面之间的距离,使得所述第二半导体芯片不完全覆盖所述孔，
所述第二半导体芯片安装在所述封装件衬底的底表面上，
所述孔贯穿所述顶表面和所述底表面。
12.一种半导体封装件，包括：
封装件衬底；
多个第一半导体芯片，每一个第一半导体芯片包括存储器单元；以及
第二半导体芯片，其包括被所述第一半导体芯片共用的外围电路，所述外围电路被配置为将两个或更多个第一半导体芯片中的所述存储器单元一起驱动，
其中所述第一半导体芯片的每一个都不包括被配置为驱动所述存储器单元的外围电路，并且所述第二半导体芯片不包括存储器单元,
所述封装件衬底包括顶表面、底表面和限定在一个位置处的孔，所述多个第一半导体芯片位于所述顶表面上，并且所述第二半导体芯片位于所述底表面上并与所述孔重叠，并且
所述孔为沿一个方向延伸的条状，
所述孔的一个侧表面与所述第二半导体芯片的一个侧表面之间的距离使得所述第二半导体芯片不完全覆盖所述孔，
其中，所述孔的所述一个侧表面垂直于所述封装件衬底的所述顶表面并且垂直于所述一个方向，
其中，所述第二半导体芯片的所述一个侧表面垂直于所述封装件衬底的所述顶表面并且垂直于所述一个方向，并且
其中，所述第二半导体芯片的所述一个侧表面靠近所述孔的所述一个侧表面，
其中，所述孔贯穿所述顶表面和所述底表面。
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