CN111668180B - 包括混合布线接合结构的层叠封装件 - Google Patents

包括混合布线接合结构的层叠封装件 Download PDF

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CN111668180B
CN111668180B CN201910971817.6A CN201910971817A CN111668180B CN 111668180 B CN111668180 B CN 111668180B CN 201910971817 A CN201910971817 A CN 201910971817A CN 111668180 B CN111668180 B CN 111668180B
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chip
package
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discrete
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CN111668180A (zh
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李南宰
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SK Hynix Inc
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SK Hynix Inc
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Abstract

包括混合布线接合结构的层叠封装件。一种层叠封装件包括层叠在封装基板上的第一子芯片层叠物和第二子芯片层叠物以及接合布线。第一子芯片层叠物包括第一子芯片和第二子芯片。第一子芯片具有其上设置有第一公共焊盘的第一表面。第二子芯片具有其上设置有第二公共焊盘的第三表面。第三表面接合至第一表面，以使得第二公共焊盘接合至第一公共焊盘。第二子芯片包括与第二公共焊盘相对的第四表面以及从第四表面延伸以使第二公共焊盘露出的通孔。接合布线经由通孔连接至第二公共焊盘并且将第一公共焊盘和第二公共焊盘二者电连接至封装基板。

Description

包括混合布线接合结构的层叠封装件
技术领域
本公开总体上涉及半导体封装技术，并且更具体地，涉及包括混合布线接合结构的层叠封装件。
背景技术
随着小型电子装置的发展，对移动系统的需求日益增加，已经不断地开发出高性能和大容量的半导体封装件。例如，已经开发出具有高密度和多通道特性的存储器半导体封装件。也就是说，已将大量精力集中在增加单个半导体封装件中所嵌入的半导体芯片的数量上。
为了增加嵌入在单个半导体封装件中的半导体芯片的数量，已经提出了用于在封装基板上垂直层叠多个半导体芯片的技术来提供层叠封装件。在这种情况下，已经使用布线接合技术或硅通孔(TSV)技术将多个层叠的半导体芯片电连接到封装基板。近来，已经开发了各种先进技术来改善用于将多个层叠的半导体芯片电连接到封装基板的互连结构。
发明内容
根据一个实施方式，一种层叠封装件可以包括第一子芯片层叠物、第二子芯片层叠物和接合布线。第一子芯片层叠物可以设置在封装基板上，并且第二子芯片层叠物可以层叠在第一子芯片层叠物上以相对于第一子芯片层叠物横向偏移。接合布线可以将第一子芯片层叠物电连接到封装基板。第一子芯片层叠物可以包括第一子芯片和第二子芯片。第一子芯片可以具有其上设置有第一分立焊盘和第一公共焊盘的第一表面。第二子芯片可以具有接合到第一表面的第三表面。第二子芯片可以包括第二分立焊盘、第二公共焊盘和通孔。第二分立焊盘和第二公共焊盘可以设置在第三表面上，并且通孔可以从第二子芯片的与第一子芯片相对的第四表面延伸以使第一分立焊盘、第二分立焊盘和第二公共焊盘露出。第二公共焊盘可以接合到第一公共焊盘。接合布线可以经由通孔接合到第一分立焊盘、第二分立焊盘和第二公共焊盘中的相应焊盘。
根据另一实施方式，一种层叠封装件可以包括第一子芯片层叠物和接合布线。第一子芯片层叠物设置在封装基板上，并且接合布线可以将第一子芯片层叠物电连接到封装基板。第一子芯片层叠物可以包括第一子芯片和第二子芯片。第一子芯片可以具有其上设置有第一公共焊盘的第一表面。第二子芯片可以具有其上设置有第二公共焊盘的第三表面，并且第三表面可以接合到第一表面，使得第二公共焊盘接合到第一公共焊盘。第二子芯片可以包括第四表面和通孔。第二子芯片的第四表面可以与第二公共焊盘相对，并且通孔可以从第四表面延伸以使第二公共焊盘露出。接合布线可以经由通孔连接到第二公共焊盘，并且可以被配置为将第一公共焊盘和第二公共焊盘两者电连接到封装基板。
附图说明
图1是例示了根据一个实施方式的层叠封装件的立体图。
图2是沿着图1的线A-A’截取的截面图。
图3是沿着图1的线B-B’截取的截面图。
图4是沿着图1的线C-C’截取的截面图。
图5是沿着图1的线D-D’截取的截面图。
图6是沿着图1的线E-E’截取的截面图。
图7至图10是例示了根据一个实施方式的制造子芯片层叠物的方法的截面图。
图11是例示了根据一个实施方式的子芯片层叠物的截面图。
图12是例示了根据一个实施方式的采用包括层叠封装件的存储卡的电子系统的框图。
图13是例示了根据一个实施方式的包括层叠封装件的另一电子系统的框图。
具体实施方式
这里使用的术语可以对应于考虑到实施方式中的功能而选择的词，并且术语的含义可以根据实施方式所属领域的普通技术人员而不同地解释。如果进行了详细定义，则可以根据定义来解释术语。除非另有定义，否则本文中使用的术语(包括技术术语和科学术语)具有与实施方式所属领域的普通技术人员通常所理解的含义相同的含义。
将理解的是，尽管在本文中可以使用术语“第一”、“第二”、“第三”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一个元件区分开，而不用于仅定义元件本身或者表示特定顺序。
还应理解，当元件或层被称为“在”另一元件或层“上”、“上方”、“下”、“下方”或“外部”时，该元件或层可以直接接触另一个元件或层，或者可以存在中间元件或层。应该以类似的方式来解释用于描述元件或层之间的关系的其它词语(例如，“在…之间”与“直接在…之间”或“相邻”与“直接相邻”)。
诸如“在…下面”、“在…下方”、“下面的”、“在…上方”、“上面的”、“顶部”、“底部”之类的空间相对术语可以用于描述例如在附图中所示的元件和/或特征与其它元件和/或特征的关系。将理解的是，除了附图中描绘的方位之外，空间相对术语旨在涵盖装置在使用和/或操作中的不同方位。例如，当附图中的装置被翻转时，被描述为在其它元件或特征之下和/或下方的元件将被定向在其它元件或特征上方。装置可以以其它方式定向(旋转90度或在其它方位)，并相应解释本文使用的空间相对描述语。
层叠封装件可以包括诸如半导体芯片或半导体晶片之类的电子装置。半导体芯片或半导体晶片可以通过使用晶片切割工艺将诸如晶圆之类的半导体基板分离成多片而获得。半导体芯片可以对应于存储器芯片、逻辑芯片(包括专用集成电路(ASIC)芯片)或片上系统(SoC)。存储器芯片可以包括集成在半导体基板上的动态随机存取存储器(DRAM)电路、静态随机存取存储器(SRAM)电路、NAND型闪存电路、NOR型闪存电路、磁性随机存取存储器(MRAM)电路、电阻式随机存取存储器(ReRAM)电路、铁电随机存取存储器(FeRAM)电路或相变随机存取存储器(PcRAM)电路。逻辑芯片可以包括集成在半导体基板上的逻辑电路。在诸如移动电话之类的通信系统、与生物技术或医疗保健相关的电子系统或可穿戴电子系统中可以采用半导体封装件。
在整个说明书中，相同的附图标记指代相同的元件。即使参照一个附图未提及或描述附图标记，也可以参照另一附图提及或描述该附图标记。另外，即使在一个附图中未示出附图标记，也可以参照另一附图来提及或描述该附图标记。
图1是例示了根据一个实施方式的层叠封装件10的立体图。
参照图1，层叠封装件10可以被配置为包括封装基板100、第一子芯片层叠物200、第二子芯片层叠物300和接合布线400。尽管在附图中未示出，但是可以在第二子芯片层叠物300上层叠更多附加子芯片层叠物中的一个。
可以使用第一粘合层510将第一子芯片层叠物200附接到封装基板100的顶表面。第一粘合层510可以将第一子芯片层叠物200固定到封装基板100。封装基板100可以用作将第一子芯片层叠物200和第二子芯片层叠物300电连接到外部装置(未示出)的互连构件。封装基板100可以是包括电路互连结构的基板，例如，印刷电路板(PCB)。封装基板100可以是中介层，或者可以包括其中设置有重分配线(RDL)的介电层。
封装基板100可以包括接合指110，接合布线400接合到接合指110的表面。接合指110可以对应于设置在封装基板100中或封装基板100上的电路互连结构(未示出)的一部分。接合指110可以设置在封装基板100的一部分上以与第一子芯片层叠物200和第二子芯片层叠物300间隔开。第一子芯片层叠物200和第二子芯片层叠物300可以设置在封装基板100上以露出接合指110。这是因为接合布线400中的一些的第一端应该被接合到接合指110。
第二子芯片层叠物300可以层叠在第一子芯片层叠物200上，以相对于第一子芯片层叠物200横向偏移。第二子芯片层叠物300可以相对于第一子芯片层叠物200横向偏移以露出第一子芯片层叠物200的边缘部分201。因此，第二子芯片层叠物300的边缘部分可以从第一子芯片层叠物200的侧表面横向突出，以用作对应于悬突体的突出部分303。第二子芯片层叠物300的突出部分303可以邻近第一子芯片层叠物200的与第一子芯片层叠物200的边缘部分201相对的侧表面。结果，第二子芯片层叠物300可以相对于第一子芯片层叠物200横向偏移以提供阶梯结构。第二子芯片层叠物300可以使用第二粘合层530附接到第一子芯片层叠物200。
图2是沿着图1的穿过层叠封装件10中所包括的第一子芯片层叠物200的线A-A’截取的截面图。
参照图1和图2，第一子芯片层叠物200可以被配置为包括彼此接合的第一子芯片210和第二子芯片250。第一子芯片210和第二子芯片250可以是具有不同功能的半导体芯片。然而，在一些其它实施方式中，第一子芯片210和第二子芯片250可以是具有相同功能的半导体芯片。第一子芯片210和第二子芯片250可以是诸如NAND芯片或DRAM芯片之类的存储器半导体芯片。
第一子芯片210和第二子芯片250可以彼此完全交叠并且可以彼此接合。第二子芯片250可以与第一子芯片210完全交叠，使得第二子芯片250的侧表面与第一子芯片210的侧表面垂直对齐。
可以使用晶圆接合技术将第一子芯片210和第二子芯片250彼此接合以构成第一子芯片层叠物200。例如，可以使用直接接合互连(DBI)技术将第一子芯片210和第二子芯片250彼此接合以构成第一子芯片层叠物200。在第一子芯片210和第二子芯片250之间的界面处可以不提供有机粘合材料或有机粘合层。
第二子芯片250的第三表面251可以面对第一子芯片210的第一表面211，并且第二子芯片250的第三表面251可以接合到第一子芯片250的第一表面211。第一子芯片210的与第二子芯片250相对的第二表面(图1的213)可以面对封装基板100，并且第一子芯片210的第二表面(图1的213)可以使用第一粘合层510附接到封装基板100的表面。集成电路(未示出)可以设置在第一子芯片210中以与第一子芯片210的第一表面211相邻，并且另一集成电路(未示出)可以设置在第二子芯片250中，以与第二子芯片250的第三表面251相邻。第一表面211和第三表面251可以对应于与第一子芯片210和第二子芯片250的集成电路相邻的有源表面。
第一分立焊盘215和第一公共焊盘217可以设置在第一子芯片210的第一表面211上。尽管图2例示了第一分立焊盘215的数量为一个的示例，但是第一分立焊盘215的数量根据实施方式可以为两个或更多个。第一分立焊盘215和第一公共焊盘217可以用作将第一子芯片210电连接到接合布线400的连接端子。
第二分立焊盘255和第二公共焊盘257可以设置在第二子芯片250的第三表面251上。尽管图2例示了第二分立焊盘255的数量为一个的示例，但是第二分立焊盘255的数量根据实施方式可以为两个或更多个。第二分立焊盘255和第二公共焊盘257可以用作将第二子芯片250电连接到接合布线400的连接端子。
第一子芯片210的第一分立焊盘215可以设置为与第一公共焊盘217间隔开并且与其有所区别。第一分立焊盘215可以设置在第一公共焊盘217所设置的区域的外部区域处。第二子芯片250的第二分立焊盘255可以设置为与第二公共焊盘257间隔开并且与其有所区别。第二分立焊盘255可以设置在第二公共焊盘257所设置的区域的外部区域。
第一子芯片210的第一公共焊盘217可以设置为与第二子芯片250的第二公共焊盘257交叠。第二子芯片250可以接合到第一子芯片210，使得第二子芯片250的第二公共焊盘257与第一子芯片210的第一公共焊盘217中的相应焊盘交叠。在实施方式中，第二子芯片250的第二公共焊盘257可以与第一子芯片210的第一公共焊盘217以一对一的方式交叠，从而单个第二公共焊盘257与单个第一公共焊盘217交叠。与第一公共焊盘217中的一个相对应的第一公共焊盘217A可以接合到与第二公共焊盘257中的一个相对应的第二公共焊盘257A，并且第一公共焊盘217A和第二公共焊盘257A可以彼此电连接以提供一个信号路径。第一子芯片210的第一公共焊盘217可以是第一子芯片210的数据输入/输出(I/O)端子。第二子芯片250的第二公共焊盘257可以是第二子芯片250的数据输入/输出(I/O)端子。
第一子芯片210的第一分立焊盘215可以独立于第二子芯片250的第二分立焊盘255的位置来设置。第一子芯片210的第一分立焊盘215和第二子芯片250的第二分立焊盘255可以设置为在平面图中彼此间隔开而没有交叠。例如，第一子芯片210的第一分立焊盘215和第二子芯片250的第二分立焊盘255可以设置为彼此间隔开，以防止第一分立焊盘215和第二分立焊盘255彼此垂直交叠。第一子芯片210的第一分立焊盘215在平面图中可以位于包括第一公共焊盘217(或第二公共焊盘257)的区域的与第二子芯片250的第二分立焊盘255相对的一侧。因此，第一子芯片210的第一分立焊盘215和第二子芯片250的第二分立焊盘255彼此不接合，以彼此电断开。
第一子芯片210的第一分立焊盘215和第二子芯片250的第二分立焊盘255可以是彼此电独立的连接端子。第一分立焊盘215可以仅电连接至第一子芯片210，并且可以与第二子芯片250电断开。类似地，第二分立焊盘255可以仅电连接至第二子芯片250，并且可以与第一子芯片210电断开。
第一分立焊盘215可以是用于选择第一子芯片210和第二子芯片250中的第一子芯片210的连接端子。例如，第一分立焊盘215可以是被施加用于选择性地驱动第一子芯片210的芯片使能信号的第一芯片使能焊盘。类似地，第二分立焊盘255可以是被施加用于选择性地驱动第二子芯片250的芯片使能信号的第二芯片使能焊盘。
图3是沿着图1的穿过层叠封装件10中所包括的第二子芯片层叠物300的线B-B’截取的截面图。
参照图1和图3，第二子芯片层叠物300可以具有与第一子芯片层叠物200基本相同的形状。第二子芯片层叠物300可以被配置为包括彼此接合的第三子芯片310和第四子芯片350。第三子芯片310和第四子芯片350可以彼此完全交叠并且可以彼此接合。第四子芯片350可以与第三子芯片310完全交叠，使得第四子芯片350的侧表面与第三子芯片310的侧表面垂直对齐。
第三子芯片310和第四子芯片350可以使用晶圆接合技术彼此接合以构成第二子芯片层叠物300。例如，第三子芯片310和第四子芯片350可以使用直接接合互连(DBI)技术彼此接合以构成第二子芯片层叠物300。在第三子芯片310和第四子芯片350之间的界面处可以不提供有机粘合材料或有机粘合层。
第四子芯片350的第七表面351可以面对第三子芯片310的第五表面311，并且第四子芯片350的第七表面351可以接合到第三子芯片310的第五表面311。第三子芯片310的与第四子芯片350相对的第六表面(图1的313)可以面对第二子芯片250的第四表面253，并且第三子芯片310的第六表面(图3的313)可以使用第二粘合层530附接到第二子芯片250的第四表面253。
第三分立焊盘315和第三公共焊盘317可以设置在第三子芯片310的第五表面311上。第三分立焊盘315和第三公共焊盘317可以用作将第三子芯片310电连接到接合布线400的连接端子。第四分立焊盘355和第四公共焊盘357可以设置在第四子芯片350的第七表面351上。第四分立焊盘355和第四公共焊盘357可以用作将第四子芯片350电连接到接合布线400的连接端子。
第三子芯片310的第三分立焊盘315可以设置为与第三公共焊盘317间隔开并且与其有所区别。第三分立焊盘315可以设置在第三公共焊盘317所设置的区域的外部区域。第四子芯片350的第四分立焊盘355可以设置为与第四公共焊盘357间隔开并且与其有所区别。第四分立焊盘355可以设置在第四公共焊盘357所设置的区域的外部区域。
第三子芯片310的第三公共焊盘317可以设置为与第四子芯片350的第四公共焊盘357交叠。第四子芯片350可以接合到第三子芯片310，使得第四子芯片350的第四公共焊盘357与第三子芯片310的第三公共焊盘317中的相应焊盘交叠。在实施方式中，第四子芯片350的第四公共焊盘357可以与第三子芯片310的第三公共焊盘317以一对一的方式交叠，从而单个第四公共焊盘357与单个第三公共焊盘317交叠。第三公共焊盘317可以接合到第四公共焊盘357，并且第三公共焊盘317和第四公共焊盘357可以彼此电连接以提供信号路径。第三子芯片310的第三公共焊盘317可以是第三子芯片310的数据输入/输出(I/O)端子。第四子芯片350的第四公共焊盘357可以是第四子芯片350的数据输入/输出(I/O)端子。
第三子芯片310的第三分立焊盘315可以独立于第四子芯片350的第四分立焊盘355的位置来设置。第三子芯片310的第三分立焊盘315和第四子芯片350的第四分立焊盘355可以设置为在平面图中彼此间隔开而没有交叠。例如，第三子芯片310的第三分立焊盘315和第四子芯片350的第四分立焊盘355可以设置为彼此间隔开，以防止第三分立焊盘315和第四分立焊盘355彼此垂直交叠。第三子芯片310的第三分立焊盘315在平面图中可以位于包括第三公共焊盘317(或第四公共焊盘357)的区域的与第四子芯片350的第四分立焊盘355相对的一侧。第三分立焊盘315可以是被施加用于选择性地驱动第三子芯片310的芯片使能信号的第三芯片使能焊盘。类似地，第四分立焊盘355可以是被施加用于选择性地驱动第四子芯片350的芯片使能信号的第四芯片使能焊盘。
图4是沿着图1的线C-C’截取的截面图。
参照图1和图4，第一子芯片层叠物200的第二子芯片250可以包括使第一子芯片210的第一分立焊盘215露出的第一通孔610。第一通孔610可以设置为贯穿第二子芯片250的第四表面253。第一通孔610可以是从第二子芯片250的第四表面253延伸到第二子芯片250的第三表面251的通孔。第一通孔610可以形成为在垂直方向上完全贯穿第二子芯片250。
第一子芯片210的第一分立焊盘215的表面215S可以通过第一通孔610露出并暴露。接合布线400中所包括的第一接合布线410的一端可以接合到第一分立焊盘215的表面215S。第一接合布线410的另一端可以接合到封装基板100的接合指110中所包括的第一接合指111。第一接合布线410可以经由第一通孔610将第一子芯片210的第一分立焊盘215直接连接至第一接合指111。
图5是沿着图1的线D-D’截取的截面图。
参照图1和图5，第一子芯片层叠物200的第二子芯片250可以包括使第二子芯片250的第二分立焊盘255露出的第二通孔620。第二通孔620可以设置为贯穿第二子芯片250的第四表面253。第二通孔620可以是从第二子芯片250的第四表面253延伸至第二分立焊盘255的表面255S的通孔。也就是说，第二子芯片250的第二分立焊盘255的表面255S可以通过第二通孔620露出并暴露。通过第二通孔620露出的第二分立焊盘255的表面255S可以对应于第二分立焊盘255的与第一子芯片210相对的背表面。第二通孔620可以基本上贯穿第二子芯片250，以暴露第二分立焊盘255的背表面255S。
接合布线400中所包括的第二接合布线420的一端可以接合至第二分立焊盘255的表面255S。第二接合布线420的另一端可以接合至封装基板100的接合指110中所包括的第二接合指112。第二接合布线420可以经由第二通孔620将第二子芯片250的第二分立焊盘255直接连接到第二接合指112。
图6是沿着图1的线E-E’截取的截面图。
参照图1和图6，第一子芯片层叠物200的第二子芯片250可以包括使第二子芯片250的第二公共焊盘257露出的第三通孔630。第三通孔630可以设置为贯穿第二子芯片250的第四表面253。第三通孔630可以是从第二子芯片250的第四表面253延伸至第二公共焊盘257的表面257S的通孔。也就是说，第二子芯片250的第二公共焊盘257的表面257S可以通过第三通孔630中的相应通孔露出并暴露。通过第三通孔630露出的第二公共焊盘257的表面257S可以对应于第二公共焊盘257的与第一公共焊盘217相对的背表面。第一公共焊盘217和第二公共焊盘257之间的接合表面257B可以对应于第二公共焊盘257的前侧表面。第三通孔630可以基本上贯穿第二子芯片250以暴露第二公共焊盘257的背表面257S中的相应背表面。
接合布线400中所包括的第三接合布线430的第一端可以接合至第二公共焊盘257的表面257S。第三接合布线430的与第一端相对的第二端可以接合至封装基板100的接合指110所包括的第三接合指113。第三接合布线430可以经由第三通孔630将第二子芯片250的第二公共焊盘257直接连接到第三接合指113。
因为第一公共焊盘217接合到第二公共焊盘257，所以第一公共焊盘217可以通过第二公共焊盘257电连接到第三接合布线430。第一子芯片210可以通过第一公共焊盘217、第二公共焊盘257和第三接合布线430电连接到封装基板100的第三接合指113。第二子芯片250可以通过第二公共焊盘257和第三接合布线430电连接到封装基板100的第三接合指113。
第一公共焊盘217和第二公共焊盘257可以通过第三接合布线430电连接到第三接合指113。也就是说，第一子芯片210和第二子芯片250二者可以通过第一公共焊盘217、第二公共焊盘257和第三接合布线430电连接到第三接合指113。然而，如图4所示，如果将芯片使能信号施加到第一接合布线410和第一分立焊盘215，则可以选择第一子芯片210，并且可以选择性地使能第一子芯片210。另外，如图5所示，如果将芯片使能信号施加到第二接合布线420和第二分立焊盘255，则可以选择第二子芯片250，并且可以选择性地使能第二子芯片250。因此，可以选择第一子芯片210和第二子芯片250中的一个并通过第三接合指113、第三接合布线430、第一公共焊盘217和第二公共焊盘257将数据或信号施加到所选子芯片。
参照图2和图6，第二子芯片250的第一通孔610的深度D1可以大于第三通孔630的深度D3。而第一分立焊盘215的通过第一通孔610露出的顶表面位于与第一子芯片210的第一表面211相同的水平处，并且通过第三通孔630露出的第二公共焊盘257位于第一公共焊盘217上。因为第一分立焊盘215和第一公共焊盘217位于相同的水平，所以第二公共焊盘257可以位于比第一分立焊盘215高的水平处。因此，第一通孔610的深度D1可以比第三通孔630的深度D3大第二公共焊盘257的厚度。第二通孔620的深度D2可以基本上等于第三通孔630的深度D3。
再次参照图1和图2，第一通孔610至第三通孔630可以以行或列排列并且可以形成在第二子芯片250中。然而，在一些其它实施方式中，可以在第二子芯片250中形成单个沟槽状通孔，而不是第一通孔610至第三通孔630。在这种情况下，可以形成单个沟槽状通孔以使第一分立焊盘215、第二公共焊盘257和第二分立焊盘255全部露出。
参照图1、图3和图4，第二子芯片层叠物300的第四子芯片350可以包括使第三子芯片310的第三分立焊盘315露出的第四通孔640。第四通孔640可以设置为贯穿第四子芯片350的与第三子芯片310相对的第八表面353。第四通孔640可以是从第四子芯片350的第八表面353延伸至第四子芯片350的第七表面351的通孔。
参照图1、图3和图5，第二子芯片层叠物300的第四子芯片350还可以包括使第四子芯片350的第四分立焊盘355露出的第四通孔640。参照图1、图3和图6，第二子芯片层叠物300的第四子芯片350还可以包括使第四子芯片350的第四公共焊盘357露出的其它第四通孔640。如图3所示，所有的第四通孔640可以基本上贯穿第四子芯片350，以分别使第三分立焊盘315、第四分立焊盘355和第四公共焊盘357露出。
再次参照图1、图3和图6，接合布线400中所包括的第四接合布线440可以设置为将通过第四通孔640露出的第四公共焊盘357电连接到第二公共焊盘257。第四接合布线440的第一端可以接合到第四公共焊盘357中的相应焊盘，并且第四接合布线440的与第一端相对的第二端可以接合至第二公共焊盘257中的相应焊盘。因此，第四接合布线440可以通过第二公共焊盘257电连接到第三接合布线430。这样，第四接合布线440可以形成为将第二子芯片层叠物300电连接到第三接合布线430。第四接合布线440可以是将第二子芯片层叠物300电连接到第一子芯片层叠物200的接合布线。
再次参照图1、图3和图4，接合布线400中所包括的第五接合布线450可以电连接到由第四通孔640中的一个露出的第三分立焊盘315。第五接合布线450可以经由第四通孔640将第三子芯片310的第三分立焊盘315直接连接到封装基板100的接合指110中所包括的第五接合指115。可以通过第五接合指115、第五接合布线450和第三分立焊盘315将用于选择第三子芯片310的芯片使能信号施加到第三子芯片310。
再次参照图1、图3和图5，接合布线400中所包括的第六接合布线460可以电连接到通过第四通孔640中的一个露出的第四分立焊盘355。第六接合布线460可以经由第四通孔640将第四子芯片350中的第四分立焊盘355直接连接到封装基板100的接合指110中所包括的第六接合指116。可以通过第六接合指116、第六接合布线460和第四分立焊盘355将用于选择第四子芯片350的芯片使能信号施加到第四子芯片350。
第五接合布线450和第六接合布线460可以是将第二子芯片层叠物300直接连接到封装基板100的接合布线。
参照图1和图2，第一子芯片层叠物200的第一公共焊盘217可以接合到第一子芯片层叠物200的第二公共焊盘257并且可以电连接到第一子芯片层叠物200的第二公共焊盘257。因为第三接合布线430接合到第二公共焊盘257，所以第一公共焊盘217和第二公共焊盘257可以电连接到第三接合布线430。第一公共焊盘217和第二公共焊盘257可以通过第三接合布线430电连接到封装基板100。
如此，第一子芯片210和第二子芯片250可以通过第三接合布线430、第一公共焊盘217和第二公共焊盘257电连接到封装基板100。因此，第三接合布线430、第一公共焊盘217和第二公共焊盘257可以构成混合布线接合结构。混合布线接合结构可以将第一子芯片210和第二子芯片250电连接到封装基板100。因此，第一子芯片210和第二子芯片250可以通过晶圆接合技术彼此接合以构成第一子芯片层叠物200，并且第二子芯片层叠物300可以层叠在第一子芯片层叠物200上以提供层叠封装件10。
构成第一子芯片层叠物200的第一子芯片210和第二子芯片250可以在不使用硅通孔(TSV)的情况下彼此电连接。即使不使用TSV，混合布线接合结构也可以将第一子芯片210和第二子芯片250电连接到封装基板100。因此，根据实施方式，可以克服由于TSV引起的一些问题。例如，实施方式可以解决由于TSV而导致的低制造率，以提高层叠封装件的制造率。
构成第一子芯片层叠物200的第一子芯片210和第二子芯片250可以使用晶圆接合技术彼此直接接合。在这种情况下，因为不使用粘合层将第一子芯片210接合到第二子芯片250，所以可以减小第一子芯片层叠物200的厚度。因此，甚至在不增加层叠封装件10的总厚度的情况下，可以增加层叠封装件10中所层叠的子芯片的数量。
第一子芯片210和第二子芯片250二者可以电连接到第三接合布线430。即使第一子芯片210和第二子芯片250中的一个是故障芯片，第一子芯片210和第二子芯片250中的另一个也可以使用而没有任何连接故障。
第一子芯片210的第一分立焊盘215和第二子芯片250的第二分立焊盘255可以分别位于包括第一公共焊盘217和第二公共焊盘257的区域的相对两侧。因此，与第一子芯片210的第一分立焊盘215连接的第一接合布线410和与第二子芯片250的第二分立焊盘255连接的第二接合布线420可以位于包括第三接合布线430的区域的相对两侧。与第一接合布线和第二接合布线设置为彼此紧邻的情况相比，包括通过第三接合布线430彼此分离的第一接合布线410和第二接合布线420的接合布线400的设置灵活性可以相对增加。因此，根据实施方式，可以有效地抑制在设置接合布线400时接合布线变形而彼此接触的故障的发生。
图7至图10是例示了制造图1的层叠封装件10中所包括的第一子芯片层叠物200的方法的截面图。
图7例示了提供第一晶圆210W和第二晶圆250W的步骤。第一晶圆210W可以是包括第一子芯片区域210R的晶圆。第一晶圆210W可以包括第一表面211以及与第一表面211相邻设置的第一分立焊盘215和第一公共焊盘217。第二晶圆250W可以是包括第二子芯片区域250R的晶圆。第二晶圆250W可以包括第三表面251以及与第三表面251相邻设置的第二分立焊盘255和第二公共焊盘257。
图8例示了将第一晶圆210W和第二晶圆250W彼此接合的步骤。可以将第二晶圆250W与第一晶圆210W对齐，使得第二晶圆250W的第三表面251面对第一晶圆210W的第一表面211，并且可以使用晶圆接合技术将第二晶圆250W的第三表面251接合至第一晶圆210W的第一表面211。第一公共焊盘217可以接合到第二公共焊盘257中的相应焊盘，第一分立焊盘215可以接合到第二晶圆250W的第三表面251，并且第二分立焊盘255可以接合到第一晶圆210W的第一表面211。可以使用直接接合互连(DBI)技术来执行该晶圆接合步骤。
图9例示了对第一晶圆210W和第二晶圆250W进行背部研磨的步骤。第一背部研磨工艺G1可以施加到第一初始背侧表面213I以减小第一晶圆210W的厚度。在第一背部研磨工艺G1之后，可以暴露与本底(back-ground)第一晶圆的背侧表面相对应的第二表面213。第二背部研磨工艺G2可以施加到第二初始背侧表面253I以减小第二晶圆250W的厚度。在第二背部研磨工艺G2之后，可以暴露与本底第二晶圆的背侧表面相对应的第四表面253。第一背部研磨工艺G1和第二背部研磨工艺G2可以分别独立执行。通过第一背部研磨工艺G1去除的部分的量可以与通过第二背部研磨工艺G2去除的部分的量相等或不同。
图10例示了使多个第一子芯片层叠物200彼此分离的步骤。首先，可以在施加了第一背部研磨工艺G1和第二背部研磨工艺G2的第一晶圆210W和第二晶圆250W的接合结构中形成通孔600。通孔600可以形成为基本贯穿第二晶圆250W。接下来，可以对第一晶圆210W和第二晶圆250W的接合结构施加诸如切割工艺之类的分离工艺，以获得彼此分离的第一子芯片层叠物200。也可以使用与参照7至图10描述的工艺基本相同的工艺来获得第二子芯片层叠物(图1的300)。
图11是例示了根据另一实施方式制造的另一子芯片层叠物200T的截面图。
参照图11，构成子芯片层叠物200T的第一子芯片210T和第二子芯片250T可以具有不同的厚度。第一子芯片210T的厚度T1可以小于第二子芯片250T的厚度T2。相反，第一子芯片210T的厚度T1可以大于第二子芯片250T的厚度T2。图1中所示的实施方式可以是第一子芯片210和第二子芯片250具有相同厚度的示例。
因为第一子芯片210T和第二子芯片250T彼此接合，所以即使第二子芯片250T的厚度T2减小，也可以抑制或防止诸如子芯片层叠物200T翘曲之类的故障的发生。如果第二子芯片250T的厚度T2减小，则子芯片层叠物200T的总厚度也可以减小。因此，可以增加在具有有限高度的层叠封装件中采用的子芯片的数量。另外，根据实施方式，可以利用将多个半导体芯片电连接到封装基板的混合布线接合结构来提供高级层叠封装件。
图12是例示了包括采用根据实施方式的层叠封装件中的至少一个的存储卡7800的电子系统的框图。存储卡7800包括诸如非易失性存储器装置的存储器7810以及存储器控制器7820。存储器7810和存储器控制器7820可以存储数据或读出所存储的数据。存储器7810和/或存储器控制器7820可以包括根据实施方式的层叠封装件中的至少一个。
存储器7810可以包括应用了本公开的实施方式的技术的非易失性存储器装置。存储器控制器7820可以响应于来自主机7830的读/写请求而控制存储器7810，从而读出所存储的数据或者存储数据。
图13是例示了包括根据实施方式的层叠封装件中的至少一个的电子系统8710的框图。电子系统8710可以包括控制器8711、输入/输出装置8712和存储器8713。控制器8711、输入/输出装置8712和存储器8713可以通过提供数据移动所通过的路径的总线8715彼此联接。
在实施方式中，控制器8711可以包括一个或更多个微处理器、数字信号处理器、微控制器和/或能够执行与这些组件相同功能的逻辑器件。控制器8711或存储器8713可以包括根据本公开的实施方式的层叠封装件中的至少一个。输入/输出装置8712可以包括从小键盘、键盘、显示装置、触摸屏等中选择的至少一个。存储器8713是用于存储数据的装置。存储器8713可以存储数据和/或控制器8711要执行的命令等。
存储器8713可以包括诸如DRAM之类的易失性存储器装置和/或诸如闪存之类的非易失性存储器装置。例如，可以将闪存安装到诸如移动终端或台式计算机之类的信息处理系统。闪存可以构成固态盘(SSD)。在这种情况下，电子系统8710可以在闪存系统中稳定地存储大量数据。
电子系统8710可以还包括被配置为向通信网络发送数据和从通信网络接收数据的接口8714。接口8714可以是有线型或无线型。例如，接口8714可以包括天线或有线或无线收发器。
电子系统8710可以被实现为执行各种功能的移动系统、个人计算机、工业计算机或逻辑系统。例如，移动系统可以是个人数字助理(PDA)、便携式计算机、平板计算机、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐系统和信息发送/接收系统中的任何一种。
如果电子系统8710是能够执行无线通信的设备，则电子系统8710可以在使用CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强时分多址)、WCDAM(宽带码分多址)、CDMA2000、LTE(长期演进)或Wibro(无线宽带互联网)的技术的通信系统中使用。
已经出于例示的目的公开了本公开的实施方式。本领域技术人员将理解，在不脱离本公开和所附权利要求的范围和精神的情况下，可以做出各种变型、添加和替换。
相关申请的交叉引用
本申请要求于2019年3月6日提交的韩国专利申请No.10-2019-0025585的优先权，该韩国专利申请的全部内容通过引用合并于本文中。

Claims (20)

1.一种层叠封装件，该层叠封装件包括：
第一子芯片层叠物，该第一子芯片层叠物被设置在封装基板上；
第二子芯片层叠物，该第二子芯片层叠物层叠在所述第一子芯片层叠物上以相对于所述第一子芯片层叠物横向偏移；以及
接合布线，所述接合布线将所述第一子芯片层叠物电连接到所述封装基板，
其中，所述第一子芯片层叠物包括：
第一子芯片，该第一子芯片具有其上设置有第一分立焊盘和第一公共焊盘的第一表面；以及
第二子芯片，该第二子芯片具有接合到所述第一表面的第三表面，
其中，第二子芯片包括：
第二分立焊盘和第二公共焊盘，该第二分立焊盘和该第二公共焊盘被设置在所述第三表面上；以及
通孔，所述通孔从所述第二子芯片的与所述第一子芯片相对的第四表面延伸以使所述第一分立焊盘、所述第二分立焊盘和所述第二公共焊盘露出，
其中，所述第二公共焊盘接合到所述第一公共焊盘，并且
其中，所述接合布线经由所述通孔接合到所述第一分立焊盘、所述第二分立焊盘和所述第二公共焊盘中的各个焊盘。
2.根据权利要求1所述的层叠封装件，其中，所述第二子芯片与所述第一子芯片完全交叠并接合至所述第一子芯片。
3.根据权利要求1所述的层叠封装件，其中，所述第一分立焊盘被设置为与所述第二分立焊盘间隔开，以防止所述第一分立焊盘与所述第二分立焊盘垂直交叠。
4.根据权利要求1所述的层叠封装件，其中，所述第一分立焊盘和所述第二分立焊盘分别位于所述第一公共焊盘的相对两侧。
5.根据权利要求1所述的层叠封装件，其中，所述第一公共焊盘被设置为与所述第二公共焊盘交叠。
6.根据权利要求1所述的层叠封装件，
其中，所述通孔从所述第二子芯片的所述第四表面延伸至所述第二子芯片的所述第三表面；并且
其中，所述通孔包括：
第一通孔，该第一通孔使所述第一子芯片的所述第一分立焊盘露出；
第二通孔，该第二通孔贯穿所述第二子芯片以使所述第二分立焊盘露出；以及
第三通孔，该第三通孔贯穿所述第二子芯片以使所述第二公共焊盘的与所述第一公共焊盘相对的背侧表面露出。
7.根据权利要求6所述的层叠封装件，其中，所述第一通孔比所述第三通孔深。
8.根据权利要求6所述的层叠封装件，其中，所述接合布线包括：
第一接合布线，该第一接合布线被配置为经由所述第一通孔接合至所述第一分立焊盘，并且被配置为将所述第一分立焊盘电连接至所述封装基板的第一接合指；
第二接合布线，该第二接合布线被配置为经由所述第二通孔接合至所述第二分立焊盘，并且被配置为将所述第二分立焊盘电连接至所述封装基板的第二接合指；以及
第三接合布线，该第三接合布线被配置为经由所述第三通孔接合至所述第二公共焊盘，并且被配置为将所述第一公共焊盘和所述第二公共焊盘电连接至所述封装基板的第三接合指。
9.根据权利要求8所述的层叠封装件，该层叠封装件还包括：第四接合布线，该第四接合布线的一端接合至所述第二公共焊盘以电连接至所述第三接合布线，并且另一端电连接至所述第二子芯片层叠物。
10.根据权利要求1所述的层叠封装件，该层叠封装件还包括第五接合布线，该第五接合布线将所述第二子芯片层叠物直接连接到所述封装基板。
11.根据权利要求1所述的层叠封装件，其中，所述第一子芯片和所述第二子芯片具有不同的厚度。
12.根据权利要求1所述的层叠封装件，其中，所述第二子芯片的厚度小于所述第一子芯片的厚度。
13.根据权利要求1所述的层叠封装件，其中，所述第二子芯片层叠物具有与所述第一子芯片层叠物基本相同的形状。
14.根据权利要求1所述的层叠封装件，其中，所述第二子芯片层叠物包括：
第三子芯片，该第三子芯片具有其上设置有第三分立焊盘和第三公共焊盘的第五表面；以及
第四子芯片，该第四子芯片具有接合到所述第五表面的第七表面，
其中，所述第四子芯片包括：
第四分立焊盘和第四公共焊盘，该第四分立焊盘和该第四公共焊盘被设置在所述第七表面上；以及
第四通孔，所述第四通孔从所述第四子芯片的与所述第三子芯片相对的第八表面延伸，以使所述第三分立焊盘、所述第四分立焊盘和所述第四公共焊盘露出。
15.根据权利要求1所述的层叠封装件，该层叠封装件还包括粘合层，该粘合层将所述第二子芯片附接到所述第一子芯片。
16.一种层叠封装件，该层叠封装件包括：
第一子芯片层叠物，该第一子芯片层叠物被设置在封装基板上；以及
接合布线，该接合布线将所述第一子芯片层叠物电连接到所述封装基板，
其中，所述第一子芯片层叠物包括：
第一子芯片，该第一子芯片具有其上设置有第一公共焊盘的第一表面；以及
第二子芯片，该第二子芯片具有其上设置有第二公共焊盘的第三表面，其中，所述第三表面接合到所述第一表面，使得所述第二公共焊盘接合到所述第一公共焊盘，
其中，所述第二子芯片包括：
第四表面，该第四表面与所述第二公共焊盘相对；以及
通孔，该通孔从所述第四表面延伸以使所述第二公共焊盘露出，
其中，所述接合布线经由所述通孔连接到所述第二公共焊盘，并且被配置为将所述第一公共焊盘和所述第二公共焊盘两者电连接到所述封装基板。
17.根据权利要求16所述的层叠封装件，该层叠封装件还包括第二子芯片层叠物，该第二子芯片层叠物被设置在所述第一子芯片层叠物上并且相对于所述第一子芯片层叠物横向偏移。
18.根据权利要求17所述的层叠封装件，其中，所述第二子芯片层叠物具有与所述第一子芯片层叠物基本相同的形状。
19.根据权利要求17所述的层叠封装件，其中，所述第二子芯片层叠物包括：
第三子芯片，该第三子芯片具有其上设置有第三分立焊盘和第三公共焊盘的第五表面以及与所述第三分立焊盘相对的第六表面；以及
第四子芯片，该第四子芯片具有接合到所述第五表面的第七表面，
其中，所述第四子芯片包括：
第四公共焊盘，该第四公共焊盘被设置在所述第七表面上；以及
附加通孔，该附加通孔从所述第四子芯片的与所述第三子芯片相对的第八表面延伸，以使所述第四公共焊盘露出。
20.根据权利要求17所述的层叠封装件，其中，所述第一子芯片包括第一分立焊盘，该第一分立焊盘接收用于选择所述第一子芯片和所述第二子芯片中的所述第一子芯片的芯片使能信号。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220097725A (ko) * 2020-12-31 2022-07-08 삼성전자주식회사 반도체 패키지
US11532595B2 (en) 2021-03-02 2022-12-20 Micron Technology, Inc. Stacked semiconductor dies for semiconductor device assemblies

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001358285A (ja) * 2000-06-12 2001-12-26 Hitachi Ltd 樹脂封止型半導体装置
JP2002064206A (ja) * 2000-06-09 2002-02-28 Toshiba Corp 半導体装置及びその製造方法
JP2004095799A (ja) * 2002-08-30 2004-03-25 Toshiba Corp 半導体装置およびその製造方法
JP2007281510A (ja) * 2001-05-11 2007-10-25 Renesas Technology Corp 半導体装置の製造方法
KR20090013417A (ko) * 2007-08-01 2009-02-05 삼성전자주식회사 반도체 패키지, 이를 이용한 웨이퍼 스택 패키지 및 이의제조방법
KR20140028209A (ko) * 2012-08-27 2014-03-10 에스케이하이닉스 주식회사 반도체 칩, 이를 포함하는 반도체 패키지 및 반도체 패키지의 칩선택 방법
CN105347289A (zh) * 2015-10-09 2016-02-24 锐迪科微电子（上海）有限公司 适用于芯片级封装的密闭结构及其制造方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6661085B2 (en) * 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
JP4377269B2 (ja) * 2004-03-19 2009-12-02 Ｎｅｃエレクトロニクス株式会社 半導体装置
US20050253245A1 (en) * 2004-05-12 2005-11-17 Mark Lynch Package design and method for electrically connecting die to package
JP4528100B2 (ja) * 2004-11-25 2010-08-18 新光電気工業株式会社 半導体装置及びその製造方法
US7393770B2 (en) * 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
US7786572B2 (en) * 2005-09-13 2010-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. System in package (SIP) structure
JP4913640B2 (ja) * 2007-03-19 2012-04-11 ルネサスエレクトロニクス株式会社 半導体装置
KR20090043898A (ko) * 2007-10-30 2009-05-07 삼성전자주식회사 스택 패키지 및 그 제조 방법, 및 스택 패키지를 포함하는카드 및 시스템
US7872357B2 (en) * 2008-03-05 2011-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Protection for bonding pads and methods of formation
KR101660430B1 (ko) * 2009-08-14 2016-09-27 삼성전자 주식회사 반도체 패키지
JP4776675B2 (ja) * 2008-10-31 2011-09-21 株式会社東芝 半導体メモリカード
KR101676620B1 (ko) * 2010-02-05 2016-11-16 에스케이하이닉스 주식회사 적층 반도체 패키지
KR101766725B1 (ko) * 2010-10-06 2017-08-09 삼성전자 주식회사 칩 스택을 구비하는 반도체 장치, 반도체 시스템 및 그 제조 방법
US8637353B2 (en) * 2011-01-25 2014-01-28 International Business Machines Corporation Through silicon via repair
WO2013078538A1 (en) * 2011-11-29 2013-06-06 Mosaid Technologies Incorporated Interposer for stacked semiconductor devices
ITTO20120374A1 (it) * 2012-04-27 2013-10-28 St Microelectronics Srl Struttura a semiconduttore con regioni conduttive a bassa temperatura di fusione e metodo per riparare una struttura a semiconduttore
KR102033784B1 (ko) 2012-07-13 2019-10-17 에스케이하이닉스 주식회사 칩 스택 패키지 및 이를 포함하는 시스템 인 패키지와 그 동작방법
KR101984831B1 (ko) * 2013-01-31 2019-05-31 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
KR102110405B1 (ko) * 2013-11-01 2020-05-14 에스케이하이닉스 주식회사 반도체 패키지 및 그 제조방법
US20150221614A1 (en) * 2014-02-06 2015-08-06 Sehat Sutardja High-bandwidth dram using interposer and stacking
KR102320046B1 (ko) * 2014-09-19 2021-11-01 삼성전자주식회사 캐스케이드 칩 스택을 갖는 반도체 패키지
KR102360381B1 (ko) * 2014-12-01 2022-02-11 삼성전자주식회사 적층 구조를 갖는 반도체 소자 및 그 제조방법
KR20170034597A (ko) * 2015-09-21 2017-03-29 에스케이하이닉스 주식회사 복수의 칩들이 내장된 반도체 패키지
KR102576764B1 (ko) * 2016-10-28 2023-09-12 에스케이하이닉스 주식회사 비대칭 칩 스택들을 가지는 반도체 패키지
US10347605B2 (en) * 2017-11-28 2019-07-09 International Business Machines Corporation System and method for routing signals in complex quantum systems
KR20200022214A (ko) * 2018-08-22 2020-03-03 삼성전자주식회사 반도체 패키지 및 그의 제조 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002064206A (ja) * 2000-06-09 2002-02-28 Toshiba Corp 半導体装置及びその製造方法
JP2001358285A (ja) * 2000-06-12 2001-12-26 Hitachi Ltd 樹脂封止型半導体装置
JP2007281510A (ja) * 2001-05-11 2007-10-25 Renesas Technology Corp 半導体装置の製造方法
JP2004095799A (ja) * 2002-08-30 2004-03-25 Toshiba Corp 半導体装置およびその製造方法
KR20090013417A (ko) * 2007-08-01 2009-02-05 삼성전자주식회사 반도체 패키지, 이를 이용한 웨이퍼 스택 패키지 및 이의제조방법
KR20140028209A (ko) * 2012-08-27 2014-03-10 에스케이하이닉스 주식회사 반도체 칩, 이를 포함하는 반도체 패키지 및 반도체 패키지의 칩선택 방법
CN105347289A (zh) * 2015-10-09 2016-02-24 锐迪科微电子（上海）有限公司 适用于芯片级封装的密闭结构及其制造方法

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