CN111490029B - 包括桥接管芯的半导体封装 - Google Patents

包括桥接管芯的半导体封装 Download PDF

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Publication number
CN111490029B
CN111490029B CN201910909802.7A CN201910909802A CN111490029B CN 111490029 B CN111490029 B CN 111490029B CN 201910909802 A CN201910909802 A CN 201910909802A CN 111490029 B CN111490029 B CN 111490029B
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die
semiconductor die
semiconductor
bridge
package
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CN111490029A (zh
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金钟薰
金基范
崔福奎
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SK Hynix Inc
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SK Hynix Inc
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Abstract

包括桥接管芯的半导体封装。一种半导体封装包括设置在封装基板上的第一半导体管芯以及第二半导体管芯的层叠物。该半导体封装还包括：第一桥接管芯，其具有将第一半导体管芯电连接到封装基板的第一通孔；第二桥接管芯，其具有将第二半导体管芯的层叠物电连接到封装基板的第二通孔；以及第三半导体管芯，其被设置为与第一半导体管芯以及第二半导体管芯的层叠物交叠。此外，该半导体封装还包括将第三半导体管芯电连接到第二桥接管芯的再分配线。

Description

包括桥接管芯的半导体封装
技术领域
本公开涉及半导体封装技术，更具体地，涉及包括桥接管芯的半导体封装。
背景技术
近来，已进行了许多努力以将多个半导体管芯集成到单个半导体封装中。即，已尝试增加封装集成密度以实现利用多功能操作高速处理大量数据的高性能半导体封装。例如，系统封装(SiP)技术可被视为实现高性能半导体封装的有吸引力的候选。在半导体封装中可采用硅中介层(silicon interposer)以将多个半导体管芯彼此电连接。在SiP中，已使用硅中介层来将微处理器管芯电连接到存储器管芯。
发明内容
根据实施方式，一种半导体封装包括：第一半导体管芯，其设置在封装基板上；第二半导体管芯的层叠物，其设置在封装基板上以与第一半导体管芯间隔开；第一桥接管芯，其包括将第一半导体管芯电连接到封装基板的第一通孔；第二桥接管芯，其包括将第二半导体管芯的层叠物电连接到封装基板的第二通孔；第三半导体管芯，其被设置为与第一半导体管芯以及第二半导体管芯的层叠物交叠；第一内连接器，其将第一半导体管芯电连接到第三半导体管芯；第二内连接器，其将第二半导体管芯的层叠物电连接到第三半导体管芯；以及再分配线，其被设置为将第三半导体管芯电连接到第二桥接管芯。
根据另一实施方式，一种半导体封装包括：第一半导体管芯，其设置在封装基板上；第二半导体管芯的层叠物，其设置在封装基板上以与第一半导体管芯间隔开；第一桥接管芯，其包括将第一半导体管芯电连接到封装基板的第一通孔；第二桥接管芯，其包括将第二半导体管芯的层叠物电连接到封装基板的第二通孔；支撑管芯，其被设置为与第一半导体管芯以及第二半导体管芯的层叠物交叠；导电图案，其设置在支撑管芯的表面上；第一内连接器，其将第一半导体管芯电连接到导电图案；以及第二内连接器，其将第二半导体管芯的层叠物电连接到导电图案。
根据另一实施方式，一种半导体封装包括：第一半导体管芯，其设置在封装基板上；第二半导体管芯，其设置在封装基板上以与第一半导体管芯间隔开；第一桥接管芯，其包括将第一半导体管芯电连接到封装基板的第一通孔；第二桥接管芯，其包括将第二半导体管芯电连接到封装基板的第二通孔；第三半导体管芯，其被设置为与第一半导体管芯和第二半导体管芯交叠；第一内连接器，其将第一半导体管芯电连接到第三半导体管芯；第二内连接器，其将第二半导体管芯电连接到第三半导体管芯；以及再分配线，其被设置为将第三半导体管芯电连接到第二桥接管芯。
附图说明
图1是示出根据实施方式的半导体封装的横截面图。
图2是包括图1所示的半导体封装的第一半导体管芯的部分的放大图。
图3是包括图1所示的半导体封装的第二半导体管芯的层叠物的部分的放大图。
图4是示出根据另一实施方式的半导体封装的横截面图。
图5是示出根据另一实施方式的半导体封装的横截面图。
图6是示出采用包括根据实施方式的半导体封装的存储卡的电子系统的框图。
图7是示出包括根据实施方式的半导体封装的另一电子系统的框图。
具体实施方式
本文所使用的术语可对应于考虑其在实施方式中的功能而选择的词语，术语的含义可被解释为根据实施方式所属领域的普通技术人员而不同。如果详细定义，则可根据定义来解释术语。除非另外定义，否则本文所使用的术语(包括技术术语和科学术语)具有实施方式所属领域的普通技术人员通常理解的相同含义。
本文所公开的具体结构或功能描述仅是例示性的，用于描述根据本公开的概念的实施方式。根据本公开的概念的实施方式可按照各种形式实现，不能被解释为限于本文所阐述的实施方式。
根据本公开的概念的实施方式可按照各种方式修改并且具有各种形状。因此，实施方式示出于附图中并且旨在在本文中详细描述。然而，根据本公开的概念的实施方式不应被解释为限于指定的公开，而是包括没有脱离本公开的精神和技术范围的所有改变、等同或替代。
将理解，尽管本文中可使用术语“第一”、“第二”、“第三”等来描述各种元件，但是这些元件不应受这些术语限制。这些术语仅用于将一个元件与另一元件相区分，而非用于仅限定元件本身或者意指特定顺序。
还将理解，当元件或层被称为在另一元件或层“上”、“上方”、“下面”、“下方”或“外侧”时，该元件或层可与另一元件或层直接接触，或者可存在中间元件或层。用于描述元件或层之间的关系的其它词语应该以类似的方式解释(例如，“在...之间”与“直接在...之间”或者“相邻”与“直接相邻”之间)。
将理解，当元件被称为“连接”或“联接”到另一元件时，它可直接连接或联接到所述另一元件，或者也可存在中间元件。相比之下，当元件被称为“直接连接”或“直接联接”到另一元件时，不存在中间元件。
本申请中所使用的术语仅用于描述特定实施方式，而非旨在限制本公开。除非上下文清楚地另外指示，否则本公开中的单数形式旨在也包括复数形式。还将理解，诸如“包括”或“具有”等的术语旨在指示本说明书中所公开的特征、数量、操作、动作、部件、部分或其组合的存在，而非旨在排除可存在或可添加一个或更多个其它特征、数量、操作、动作、部件、部分或其组合的可能性。
诸如“在...之下”、“在...下面”、“下”、“上面”、“上”、“顶部”、“底部”等的空间相对术语可用于描述元件和/或特征与另一元件和/或特征的关系(例如，如图中所示)。将理解，除了附图中所描绘的取向之外，空间相对术语旨在涵盖装置在使用和/或操作中的不同取向。例如，当附图中的装置翻转时，被描述为在其它元件或特征下面和/或之下的元件将被取向为在其它元件或特征上面。装置可按照其它方式取向(旋转90度或处于其它取向)并且相应地解释本文中所使用的空间相对描述符。术语“柔性桥接管芯”或“柔性层叠封装”意指当外力(或外部应力)施加到桥接管芯或层叠封装时在没有任何裂缝的情况下翘曲或弯曲的桥接管芯或层叠封装。
层叠封装可对应于半导体封装。半导体封装可包括诸如半导体芯片或半导体管芯的电子器件。半导体芯片或半导体管芯可通过使用划片工艺将诸如晶圆的半导体基板分离成多片来获得。半导体芯片可对应于存储器芯片、逻辑芯片(包括专用集成电路(ASIC)芯片)或系统芯片(SoC)。存储器芯片可包括集成在半导体基板上的动态随机存取存储器(DRAM)电路、静态随机存取存储器(SRAM)电路、NAND型闪存电路、NOR型闪存电路、磁随机存取存储器(MRAM)电路、电阻式随机存取存储器(ReRAM)电路、铁电随机存取存储器(FeRAM)电路或相变随机存取存储器(PcRAM)电路。逻辑芯片可包括集成在半导体基板上的逻辑电路。半导体封装可用在诸如移动电话的通信系统、与生物技术或保健关联的电子系统或可穿戴电子系统中。
贯穿说明书，相同的标号表示相同的元件。即使标号未参照一幅图提及或描述，该标号也可参照另一幅图提及或描述。另外，即使标号未在一幅图中示出，其也可参照另一幅图提及或描述。
图1是示出根据实施方式的半导体封装10的横截面图。
参照图1，半导体封装10可被配置为包括封装基板100、第一半导体管芯200、第二半导体管芯301的层叠物300和管芯组件400。管芯组件400可被配置为包括第一桥接管芯500、第二桥接管芯600、第三半导体管芯700和模塑层800。
第一半导体管芯200可设置在封装基板100的第一表面101上。层叠物300可设置在封装基板100的第一表面101上。层叠物300可与第一半导体管芯200横向间隔开。管芯组件400可位于封装基板100和层叠物300之间。管芯组件400也可位于封装基板100和第一半导体管芯200之间。即，管芯组件400可设置在封装基板100的第一表面101上，并且第一半导体管芯200和层叠物300可在管芯组件400的接触封装基板100的侧面的相反侧并排设置在管芯组件400的表面上。
封装基板100可用作将半导体封装10电连接到外部装置或另一半导体模块的互连构件。在实施方式中，封装基板100可以是印刷电路板(PCB)。封装基板100可具有位于管芯组件400的相反侧的第二表面102。外连接器190可设置在封装基板100的第二表面102上以将半导体封装10电连接到外部装置或另一半导体模块。外连接器190可以是焊球。
图2是示出包括图1所示的半导体封装10的第一半导体管芯200的部分的放大横截面图。
参照图1和图2，管芯组件400的第一桥接管芯500可位于封装基板100和第一半导体管芯200之间。第一桥接管芯500可与第一半导体管芯200交叠。第一桥接管芯500可用作将第一半导体管芯200电连接到封装基板100的互连构件。第一桥接管芯500也可充当支撑第一半导体管芯200的部分的支撑件。
第一桥接管芯500可被配置为包括第一桥接管芯主体510和第一通孔520。第一通孔520可由垂直地穿透第一桥接管芯主体510的导电材料形成。
第一桥接管芯主体510可包括诸如硅材料的半导体材料。如果第一桥接管芯主体510包括硅材料，则第一通孔520可使用硅通孔(TSV)技术来形成。第一通孔520可使用硅处理技术来形成。因此，第一通孔520可形成为具有小尺寸(例如，小直径)的导电通孔。例如，第一通孔520可形成为具有大约0.5微米的直径。
第一桥接管芯主体510的宽度W2可小于第一半导体管芯200的宽度W1。然而，当需要增加第一通孔520的数量以便将第一半导体管芯200电连接到封装基板100时，可通过使用TSV技术形成第一通孔520来增加第一通孔520的数量。因此，第一桥接管芯500可提供足够量的第一通孔520，充当将第一半导体管芯200电连接到封装基板100的垂直电路径。
第一通孔520可由导电金属材料(例如，包括铜的金属材料)形成。
第一通孔520可通过第三内连接器930电连接到第一半导体管芯200。第一通孔520可通过第四内连接器940电连接到封装基板100。包括第三内连接器930、第一通孔520和第四内连接器940的连接结构可提供与将第一半导体管芯200直接电连接到封装基板100的垂直路径对应的第一电路径P1。第三内连接器930和第四内连接器940可以是凸块。
图3是示出包括图1所示的半导体封装10的层叠物300的部分的放大横截面图。
参照图3，管芯组件400的第二桥接管芯600可位于封装基板100和层叠物300之间。第二桥接管芯600可与层叠物300交叠。第二桥接管芯600可用作将层叠物300电连接到封装基板100的互连构件。第二桥接管芯600也可充当支撑层叠物300的部分的支撑件。
第二桥接管芯600可被配置为包括第二桥接管芯主体610、第二通孔630和第三通孔670。第二通孔630可由垂直地穿透第二桥接管芯主体610的导电材料形成。
第二桥接管芯主体610可包括诸如硅材料的半导体材料。如果第二桥接管芯主体610包括硅材料，则第二通孔630可使用硅通孔(TSV)技术来形成。因此，第二通孔630可形成为具有小尺寸(例如，小直径)的导电通孔。
第二桥接管芯主体610的宽度W4可小于层叠物300的宽度W3。然而，当需要增加第二通孔630的数量以便将第二半导体管芯301电连接到封装基板100时，可通过使用TSV技术形成第二通孔630来增加第二通孔630的数量。因此，第二桥接管芯600可提供足够量的第二通孔630，充当将层叠物300电连接到封装基板100的垂直电路径。
第二通孔630可通过第五内连接器950电连接到层叠物300。第二通孔630可通过第六内连接器960电连接到封装基板100。包括第五内连接器950、第二通孔630和第六内连接器960的连接结构可提供与将层叠物300直接电连接到封装基板100的垂直路径对应的第二电路径P2。第三内连接器930和第四内连接器940可以是凸块。
再参照图1，第三半导体管芯700可设置在第一桥接管芯500和第二桥接管芯600之间。第三半导体管芯700的一个部分可与层叠物300的部分交叠，第三半导体管芯700的另一部分可与第一半导体管芯200的部分交叠。即，第三半导体管芯700可包括与第一半导体管芯200交叠的部分701以及与层叠物300交叠的部分702。第三半导体管芯700可被设置为使得部分701位于第一半导体管芯200和封装基板100之间并且部分702位于层叠物300和封装基板100之间。
第三半导体管芯700可具有彼此相反的第一表面703和第二表面704。第三半导体管芯700可被设置为使得第一表面703面向第一半导体管芯200和层叠物300，并且第二表面704面向封装基板100。导电连接焊盘710可设置在第三半导体管芯700的第一表面703上。
第三半导体管芯700还可包括设置在部分701中的第二界面区域720，并且第二界面区域720可包括物理层PHY。第三半导体管芯700还可包括电路区域730，用于控制第二半导体管芯301的集成电路形成在该电路区域730中。第二半导体管芯301可对应于由第三半导体管芯700控制的从管芯，第三半导体管芯700可对应于主管芯。
层叠物300可通过垂直地层叠第二半导体管芯301来形成。第二半导体管芯301可以是诸如动态随机存取存储器(DRAM)器件的存储器半导体管芯。第二半导体管芯301可通过第七内连接器970彼此电连接。各个第二半导体管芯301可包括电连接到一些第七内连接器970的第四通孔320。第二半导体管芯301可通过第七内连接器970和第四通孔320彼此电连接。第四通孔320可使用TSV技术形成。
再参照图2，第三半导体管芯700可被设置为使得部分701与第一半导体管芯200交叠。第一半导体管芯200可包括与第三半导体管芯700交叠的第一界面区域220。第一界面区域220可包括用于与第三半导体管芯700连通的集成电路。即，用于与第三半导体管芯700连通的物理层PHY可设置在第一界面区域220中。第一半导体管芯200可被设置为使得第一界面区域220与第二界面区域720交叠。
第一半导体管芯200可通过第一内连接器910电连接到第三半导体管芯700。第一内连接器910可设置在第三半导体管芯700的与第一半导体管芯200交叠的部分701上。第一内连接器910可与第一界面区域220和第二界面区域720交叠。第一内连接器910可提供将第一半导体管芯200电连接到第三半导体管芯700的第三电路径P3。
由于第一内连接器910位于第一半导体管芯200和第三半导体管芯700之间，所以第三电路径P3的垂直长度可显著减小。因此，由于电路径的距离减小，第一界面区域220和第二界面区域720之间的数据传输速度可改进，以增强半导体封装10的性能。
再参照图3，第三半导体管芯700可被设置为使得部分702与层叠物300交叠。层叠物300可通过第二内连接器920电连接到第三半导体管芯700。第二内连接器920可位于第三半导体管芯700的与层叠物300交叠的部分702上。第二内连接器920可提供将第三半导体管芯700电连接到层叠物300的第四电路径P4。
由于第二内连接器920位于第三半导体管芯700和层叠物300之间，所以第四电路径P4的垂直长度可显著减小。因此，由于电路径的距离减小，第三半导体管芯700和层叠物300之间的数据传输速度可改进，以增强半导体封装10的性能。
再参照图1，模塑层800可将第一桥接管芯500和第二桥接管芯600以及第三半导体管芯700嵌入其中。模塑层800可围绕第一桥接管芯500和第二桥接管芯600以及第三半导体管芯700并将其固定就位，从而充当管芯组件400的部件。模塑层800可延伸以填充第一桥接管芯500和第三半导体管芯700之间的空间D1。模塑层800也可延伸以填充第二桥接管芯600和第三半导体管芯700之间的空间D2。模塑层800可充当将第一桥接管芯500和第二桥接管芯600以及第三半导体管芯700结合并固定就位的基层。模塑层800可由各种封装材料中的任一种形成。例如，模塑层800可由环氧模塑料(EMC)材料形成。模塑层800可延伸以覆盖第三半导体管芯700的第二表面704，同时露出第三半导体管芯700的第一表面703。
参照图3，管芯组件400还可包括将第二桥接管芯600电连接到第三半导体管芯700的再分配线850。再分配线850可以是第一端位于第三半导体管芯700上，第二端位于第二桥接管芯600上的导电线图案。因此，各条再分配线850可从第三半导体管芯700的部分延伸到第二桥接管芯600的部分。再分配线850可设置在模塑层800的填充第二桥接管芯600和第三半导体管芯700之间的空间D2的部分801上。
再分配线850可延伸，使得再分配线850的第一端连接到第三半导体管芯700的连接焊盘710并且再分配线850的第二端连接到第二桥接管芯600的第三通孔670。第二桥接管芯600的第三通孔670可电联接到再分配线850以将第三半导体管芯700电连接到封装基板100。第三通孔670可通过第八内连接器980电连接到封装基板100。第三通孔670可形成为具有与第二通孔630基本上相同的形状。第八内连接器980可以是具有与第六内连接器960基本上相同的形状的凸块。
再分配线850、第三通孔670和第八内连接器980可提供将第三半导体管芯700电连接到封装基板100的第五电路径P5。由于第五电路径P5的配置，第三半导体管芯700可电连接到封装基板100而无需任何额外的连接构件。例如，实施方式可能不需要穿透第三半导体管芯700的主体的硅通孔(TSV)。
第一介电层861和第二介电层862可依次形成在管芯组件400的表面401上。可形成第一介电层861和第二介电层862以保护再分配线850并将再分配线850彼此电绝缘。
管芯组件400可支撑第一半导体管芯200和层叠物300并且可将第一半导体管芯200和层叠物300电连接到封装基板100。可通过形成用于将第一桥接管芯500和第二桥接管芯600以及第三半导体管芯700结合并固定就位的模塑层800来提供管芯组件400。结果，可使用管芯组件400来提供半导体封装10，而无需使用诸如硅中介层的任何互连结构。
图4是示出根据另一实施方式的半导体封装20的横截面图。
参照图4，半导体封装20可被配置为包括封装基板2100、第一半导体管芯2200、第二半导体管芯2301的层叠物2300和管芯组件2400。管芯组件2400可被配置为包括第一桥接管芯2500、第二桥接管芯2600、支撑管芯2700和模塑层2800。
第一半导体管芯2200可设置在封装基板2100的第一表面2101上。第二半导体管芯2301的层叠物2300可设置在封装基板2100的第一表面2101上。层叠物2300可与第一半导体管芯2200横向间隔开。管芯组件2400可位于封装基板2100和层叠物2300之间。管芯组件2400也可位于封装基板2100和第一半导体管芯2200之间。即，管芯组件2400可设置在封装基板2100的第一表面2101上，并且第一半导体管芯2200和层叠物2300可并排设置在管芯组件2400的表面上，该表面与接触封装基板2100的表面相反。
外连接器2190可设置在封装基板2100的第二表面2102(该表面与接触管芯组件2400的表面相反)上，以将半导体封装20电连接到外部装置或另一半导体模块。
管芯组件2400的第一桥接管芯2500可位于封装基板2100和第一半导体管芯2200之间。第一桥接管芯2500可与第一半导体管芯2200交叠。第一桥接管芯2500可被配置为包括第一桥接管芯主体2510和第一通孔2520。第一通孔2520可由垂直地穿透第一桥接管芯主体2510的导电材料形成。第一桥接管芯主体2510可包括诸如硅材料的半导体材料。如果第一桥接管芯主体2510包括硅材料，则第一通孔2520可使用硅通孔(TSV)技术来形成。
第一通孔2520可通过第三内连接器2930电连接到第一半导体管芯2200。第一通孔2520可通过第四内连接器2940电连接到封装基板2100。包括第三内连接器2930、第一通孔2520和第四内连接器2940的连接结构可提供与将第一半导体管芯2200直接电连接到封装基板2100的垂直路径对应的第一电路径P21。
管芯组件2400的第二桥接管芯2600可位于封装基板2100和层叠物2300之间。第二桥接管芯2600可与层叠物2300交叠。第二桥接管芯2600可被配置为包括第二桥接管芯主体2610和第二通孔2630。第二通孔2630可由垂直地穿透第二桥接管芯主体2610的导电材料形成。第二桥接管芯主体2610可包括诸如硅材料的半导体材料。如果第二桥接管芯主体2610包括硅材料，则第二通孔2630可使用硅通孔(TSV)技术来形成。
第二通孔2630可通过第五内连接器2950电连接到层叠物2300。第二通孔2630可通过第六内连接器2960电连接到封装基板2100。包括第五内连接器2950、第二通孔2630和第六内连接器2960的连接结构可提供与将层叠物2300直接电连接到封装基板2100的垂直路径对应的第二电路径P22。
层叠物2300可通过垂直地层叠第二半导体管芯2301来形成。第二半导体管芯2301可以是诸如动态随机存取存储器(DRAM)器件的存储器半导体管芯。第二半导体管芯2301可通过第七内连接器2970彼此电连接。各个第二半导体管芯2301可包括电连接到一些第七内连接器2970的第三通孔2320。第二半导体管芯2301可通过第七内连接器2970和第三通孔2320彼此电连接。第三通孔2320可使用TSV技术来形成。
管芯组件2400的支撑管芯2700可设置在第一桥接管芯2500和第二桥接管芯2600之间。支撑管芯2700可与第一半导体管芯2200和层叠物2300交叠。支撑管芯2700的部分2701可与第一半导体管芯2200交叠，支撑管芯2700的另一部分2702可与层叠物2300交叠。支撑管芯2700可被设置为使得部分2701位于第一半导体管芯2200和封装基板2100之间并且部分2702位于层叠物2300和封装基板2100之间。
支撑管芯2700可具有彼此相反的第一表面2703和第二表面2704。支撑管芯2700可被设置为使得第一表面2703面向第一半导体管芯2200和层叠物2300并且第二表面2704面向封装基板2100。导电图案2710可设置在支撑管芯2700的第一表面2703上。导电图案2710可以是互连线。导电图案2710可以是金属图案(例如，铜图案)。
支撑管芯2700可支撑导电图案2710。支撑管芯2700可包括硅材料。支撑管芯2700可以是不存在集成电路的虚拟管芯。由于支撑管芯2700包括硅材料，所以导电图案2710可使用硅处理技术来形成。因此，导电图案2710可被实现为具有精细尺寸。
支撑管芯2700可被设置为使得部分2701与第一半导体管芯2200交叠。第一半导体管芯2200可通过第一内连接器2910电连接到导电图案2710。第一内连接器2910可设置在支撑管芯2700的与第一半导体管芯2200交叠的部分2701上。支撑管芯2700可被设置为使得部分2702与层叠物2300交叠。层叠物2300可通过第二内连接器2920电连接到导电图案2710。第二内连接器2920可设置在支撑管芯2700的与层叠物2300交叠的部分2702上。
导电图案2710可被设置为与第一内连接器2910交叠并且可延伸以与第二内连接器2920交叠。导电图案2710可以是将第一内连接器2910电连接到第二内连接器2920的互连线。第一内连接器2910、导电图案2710和第二内连接器2920可提供与将层叠物2300电连接到第一半导体管芯2200的水平路径对应的第三电路径P23。
第一介电层2761可设置在支撑管芯2700的第一表面2703上以将导电图案2710与支撑管芯2700的主体2709电绝缘。第二介电层2762可另外设置在第一介电层2761上以将导电图案2710彼此电绝缘。
模塑层2800可将第一桥接管芯2500和第二桥接管芯2600以及支撑管芯2700嵌入其中。模塑层2800可围绕并固定第一桥接管芯2500和第二桥接管芯2600以及支撑管芯2700，从而充当管芯组件2400的部件。
即使不使用诸如硅中介层的任何互连结构，也可通过采用管芯组件2400来提供半导体封装20。
图5是示出根据另一实施方式的半导体封装30的横截面图。
参照图5，半导体封装30可被配置为包括封装基板3100、第一半导体管芯3200、第二半导体管芯3300和管芯组件3400。管芯组件3400可被配置为包括第一桥接管芯3500、第二桥接管芯3600、第三半导体管芯3700和模塑层3800。
第一半导体管芯3200可设置在封装基板3100的第一表面3101上。第二半导体管芯3300可设置在封装基板3100的第一表面3101上。第二半导体管芯3300可与第一半导体管芯3200横向间隔开。管芯组件3400可位于封装基板3100和第二半导体管芯3300之间。管芯组件3400也可位于封装基板3100和第一半导体管芯3200之间。即，管芯组件3400可设置在封装基板3100的第一表面3101上，并且第一半导体管芯3200和第二半导体管芯3300可并排设置在管芯组件3400的表面上，该表面与接触封装基板3100的表面相反。外连接器3190可设置在封装基板3100的第二表面3102上，该表面与接触管芯组件3400的表面相反。
管芯组件3400的第一桥接管芯3500可与第一半导体管芯3200交叠。第一桥接管芯3500可用作将第一半导体管芯3200电连接到封装基板3100的互连构件。第一桥接管芯3500还可充当支撑第一半导体管芯3200的部分的支撑件。
第一桥接管芯3500可被配置为包括第一桥接管芯主体3510和第一通孔3520。第一通孔3520可由垂直地穿透第一桥接管芯主体3510的导电材料形成。第一通孔3520可通过第三内连接器3930电连接到第一半导体管芯3200。第一通孔3520可通过第四内连接器3940电连接到封装基板3100。
管芯组件3400的第二桥接管芯3600可位于封装基板3100和第二半导体管芯3300之间。第二桥接管芯3600可与第二半导体管芯3300交叠。第二桥接管芯3600可用作将第二半导体管芯3300电连接到封装基板3100的互连构件。第二桥接管芯3600还可充当支撑第二半导体管芯3300的部分的支撑件。
第二桥接管芯3600可被配置为包括第二桥接管芯主体3610和第二通孔3630。第二通孔3630可由垂直地穿透第二桥接管芯主体3610的导电材料形成。第二通孔3630可通过第五内连接器3950电连接到第二半导体管芯3300。第二通孔3630可通过第六内连接器3960电连接到封装基板3100。
管芯组件3400的第三半导体管芯3700可设置在第一桥接管芯3500和第二桥接管芯3600之间。第三半导体管芯3700可与第一半导体管芯3200和第二半导体管芯3300交叠。第三半导体管芯3700的部分3701可与第一半导体管芯3200交叠，并且第三半导体管芯3700的另一部分3702可与第二半导体管芯3300交叠。第三半导体管芯3700可被设置为使得部分3701位于第一半导体管芯3200和封装基板3100之间并且部分3702位于第二半导体管芯3300和封装基板3100之间。
第三半导体管芯3700可具有彼此相反的第一表面3703和第二表面3704。第三半导体管芯3700可被设置为使得第一表面3703面向第一半导体管芯3200和第二半导体管芯3300并且第二表面3704面向封装基板3100。导电连接焊盘3710可设置在第三半导体管芯3700的第一表面3703上。
第三半导体管芯3700还可包括设置在部分3701中的第二界面区域3720，并且该第二界面区域3720可包括物理层PHY。第三半导体管芯3700还可包括形成有用于控制第二半导体管芯3300的集成电路的电路区域3730。第二半导体管芯3300可对应于由第三半导体管芯3700控制的从管芯，第三半导体管芯3700可对应于主管芯。在这种情况下，在第二半导体管芯3300中没有设置TSV。
第三半导体管芯3700可被设置为使得第三半导体管芯3700的部分3701与第一半导体管芯3200交叠。第一半导体管芯3200可包括与第三半导体管芯3700交叠的第一界面区域3220。第一界面区域3220可包括用于与第三半导体管芯3700连通的集成电路。即，用于与第三半导体管芯3700连通的物理层PHY可设置在第一界面区域3220中。第一半导体管芯3200可被设置为使得第一界面区域3220与第二界面区域3720交叠。
第一半导体管芯3200可通过第一内连接器3910电连接到第三半导体管芯3700。第一内连接器3910可设置在第三半导体管芯3700的与第一半导体管芯3200交叠的部分3701上。第一内连接器3910可与第一界面区域3220和第二界面区域3720交叠。
第三半导体管芯3700可被设置为使得第三半导体管芯3700的部分3702与第二半导体管芯3300交叠。第二半导体管芯3300可通过第二内连接器3920电连接到第三半导体管芯3700。第二内连接器3920可位于第三半导体管芯3700的与第二半导体管芯3300交叠的部分3702上。
模塑层3800可将第一桥接管芯3500和第二桥接管芯3600以及第三半导体管芯3700嵌入其中。管芯组件3400还可包括将第二桥接管芯3600电连接到第三半导体管芯3700的再分配线3850。
再分配线3850可具有连接到第三半导体管芯3700的连接焊盘3710的第一端以及连接到第二桥接管芯3600的第三通孔3670的第二端。第二桥接管芯3600的第三通孔3670可电联接到再分配线3850以将第三半导体管芯3700电连接到封装基板3100。第二桥接管芯3600的第三通孔3670可通过第八内连接器3980电连接到封装基板3100。第二桥接管芯3600的第三通孔3670可形成为具有与第二通孔3630基本上相同的形状。第八内连接器3980可以是具有与第六内连接器3960基本上相同的形状的凸块。
第一介电层3861和第二介电层3862可依次形成在管芯组件3400的表面3401上。可形成第一介电层3861和第二介电层3862以保护再分配线3850并将再分配线3850彼此电绝缘。
图6是示出包括采用根据实施方式的半导体封装中的至少一个的存储卡7800的电子系统的框图。存储卡7800包括诸如非易失性存储器装置的存储器7810以及存储控制器7820。存储器7810和存储控制器7820可存储数据或者读出所存储的数据。存储器7810和存储控制器7820中的至少一个可包括根据实施方式的半导体封装中的至少一个。
存储器7810可包括应用了本公开的实施方式的技术的非易失性存储器装置。存储控制器7820可控制存储器7810，使得响应于来自主机7830的读/写请求，读出所存储的数据或者存储数据。
图7是示出包括根据实施方式的半导体封装中的至少一个的电子系统8710的框图。电子系统8710可包括控制器8711、输入/输出装置8712和存储器8713。控制器8711、输入/输出装置8712和存储器8713可通过提供数据移动的路径的总线8715彼此联接。
在实施方式中，控制器8711可包括一个或更多个微处理器、数字信号处理器、微控制器和/或能够执行与这些组件相同的功能的逻辑器件。控制器8711或存储器8713可包括根据本公开的实施方式的半导体封装中的至少一个。输入/输出装置8712可包括选自键区、键盘、显示装置、触摸屏等中的至少一个。存储器8713是用于存储数据的装置。存储器8713可存储要由控制器8711执行的数据和/或命令等。
存储器8713可包括诸如DRAM的易失性存储器装置和/或诸如闪存的非易失性存储器装置。例如，闪存可被安装到诸如移动终端或台式计算机的信息处理系统。闪存可构成固态盘(SSD)。在这种情况下，电子系统8710可在闪存系统中稳定地存储大量数据。
电子系统8710还可包括被配置为向通信网络发送数据以及从通信网络接收数据的接口8714。接口8714可为有线或无线型。例如，接口8714可包括天线或者有线或无线收发器。
电子系统8710可被实现为移动系统、个人计算机、工业计算机或者执行各种功能的逻辑系统。例如，移动系统可以是个人数字助理(PDA)、便携式计算机、平板计算机、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐系统和信息发送/接收系统中的任一个。
如果电子系统8710是能够执行无线通信的设备，则电子系统8710可用在使用CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强时分多址)、WCDAM(宽带码分多址)、CDMA2000、LTE(长期演进)或Wibro(无线宽带互联网)的技术的通信系统中。
出于例示性目的公开了本公开的实施方式。本领域技术人员将理解，在不脱离本公开和所附权利要求的范围和精神的情况下，可进行各种修改、添加和替换。
相关申请的交叉引用
本申请要求2019年1月25日提交的韩国申请No.10-2019-0009634的优先权，其整体通过引用并入本文。

Claims (10)

1.一种半导体封装，该半导体封装包括：
第一半导体管芯，该第一半导体管芯设置在封装基板上；
第二半导体管芯的层叠物，该层叠物设置在所述封装基板上以与所述第一半导体管芯间隔开；
第一桥接管芯，该第一桥接管芯包括将所述第一半导体管芯电连接到所述封装基板的第一通孔；
第二桥接管芯，该第二桥接管芯包括将所述第二半导体管芯的所述层叠物电连接到所述封装基板的第二通孔；
第三半导体管芯，该第三半导体管芯被设置为与所述第一半导体管芯以及所述第二半导体管芯的所述层叠物交叠；
模塑层，所述第一桥接管芯和所述第二桥接管芯以及所述第三半导体管芯被嵌入在该模塑层中，所述模塑层填充所述第二桥接管芯和所述第三半导体管芯之间的空间；
第一内连接器，所述第一内连接器将所述第一半导体管芯电连接到所述第三半导体管芯；
第二内连接器，所述第二内连接器将所述第二半导体管芯的所述层叠物电连接到所述第三半导体管芯；
介电层，所述介电层设置在所述模塑层、所述第二桥接管芯和所述第三半导体管芯上；以及
再分配线，所述再分配线设置在所述介电层的表面上，以将所述第三半导体管芯电连接到所述第二桥接管芯，
其中，所述第二桥接管芯还包括第三通孔，所述第三通孔电联接到所述再分配线，以将所述第三半导体管芯电连接到所述封装基板，
其中，所述再分配线延伸为使得所述再分配线的第一端连接到所述第三半导体管芯并且所述再分配线的第二端连接到所述第三通孔，并且
其中，所述再分配线在所述第二桥接管芯和所述第三半导体管芯上方延伸。
2.根据权利要求1所述的半导体封装，其中，所述第一桥接管芯位于所述第一半导体管芯和所述封装基板之间以与所述第一半导体管芯交叠。
3.根据权利要求1所述的半导体封装，其中，所述第二桥接管芯位于所述第二半导体管芯的所述层叠物和所述封装基板之间以与所述第二半导体管芯的所述层叠物交叠。
4. 根据权利要求1所述的半导体封装，
其中，所述第一桥接管芯包括所述第一通孔垂直地穿过的第一桥接管芯主体；并且
其中，所述第一桥接管芯主体包括硅材料。
5.根据权利要求1所述的半导体封装，其中，所述第三半导体管芯设置在所述第一桥接管芯和所述第二桥接管芯之间。
6.根据权利要求1所述的半导体封装，其中，所述第三半导体管芯被配置为具有与所述第一半导体管芯交叠的第一部分以及与所述第二半导体管芯的所述层叠物交叠的第二部分。
7.根据权利要求6所述的半导体封装，
其中，所述第一内连接器设置在所述第三半导体管芯的第一部分上；并且
其中，所述第二内连接器设置在所述第三半导体管芯的第二部分上。
8.根据权利要求1所述的半导体封装，
其中，所述第一半导体管芯包括用于与所述第三半导体管芯连通的物理层所在的第一界面区域；并且
其中，所述第三半导体管芯包括与所述第一界面区域交叠的第二界面区域。
9.根据权利要求1所述的半导体封装，
其中，多个所述第二半导体管芯垂直地层叠并通过第三通孔彼此电连接。
10.一种半导体封装，该半导体封装包括：
第一半导体管芯，该第一半导体管芯设置在封装基板上；
第二半导体管芯，该第二半导体管芯设置在所述封装基板上以与所述第一半导体管芯间隔开；
第一桥接管芯，该第一桥接管芯包括将所述第一半导体管芯电连接到所述封装基板的第一通孔；
第二桥接管芯，该第二桥接管芯包括将所述第二半导体管芯电连接到所述封装基板的第二通孔；
第三半导体管芯，该第三半导体管芯被设置为与所述第一半导体管芯和所述第二半导体管芯交叠；
模塑层，所述第一桥接管芯和所述第二桥接管芯以及所述第三半导体管芯嵌入在该模塑层中，所述模塑层填充所述第二桥接管芯和所述第三半导体管芯之间的空间；
第一内连接器，所述第一内连接器将所述第一半导体管芯电连接到所述第三半导体管芯；
第二内连接器，所述第二内连接器将所述第二半导体管芯电连接到所述第三半导体管芯；
介电层，所述介电层设置在所述模塑层、所述第二桥接管芯和所述第三半导体管芯上；以及
再分配线，所述再分配线设置在所述介电层的表面上，以将所述第三半导体管芯电连接到所述第二桥接管芯，
其中，所述第二桥接管芯还包括第三通孔，所述第三通孔电联接到所述再分配线，以将所述第三半导体管芯电连接到所述封装基板，
其中，所述再分配线延伸为使得所述再分配线的第一端连接到所述第三半导体管芯并且所述再分配线的第二端连接到所述第三通孔，并且
其中，所述再分配线在所述第二桥接管芯和所述第三半导体管芯上方延伸。
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