CN112103283A - 包括支撑基板的层叠封装件 - Google Patents
包括支撑基板的层叠封装件 Download PDFInfo
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- CN112103283A CN112103283A CN201911220682.6A CN201911220682A CN112103283A CN 112103283 A CN112103283 A CN 112103283A CN 201911220682 A CN201911220682 A CN 201911220682A CN 112103283 A CN112103283 A CN 112103283A
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- semiconductor die
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Abstract
包括支撑基板的层叠封装件。层叠封装件包括支撑第一半导体管芯和第二半导体管芯的支撑基板。支撑基板设置在封装基板上并且由第一连接凸块和第二连接凸块支撑。再分配线(RDL)图案设置在支撑基板上以将第一半导体管芯电连接至第一连接凸块和第二连接凸块。第二半导体管芯通过接合布线连接至封装基板。
Description
技术领域
本公开的实施方式涉及封装技术,并且更具体地,涉及包括支撑基板的层叠封装件。
背景技术
近来,已经提出了高性能半导体封装件来提高其操作速度。高性能半导体封装件中的每一个可以被制造为包括层叠在封装基板上的多个半导体管芯。可以使用布线接合技术将多个半导体管芯电连接至封装基板。随着电子系统处理的数据量的增加,可能需要增加半导体管芯的输入/输出(I/O)端子的数量,以便高速处理数据。在这种情况下,可能需要先进的技术来将半导体管芯的I/O端子电连接至封装基板。
发明内容
根据实施方式,一种层叠封装件包括:封装基板;安装在封装基板上并由设置在支撑基板和封装基板之间的第一连接凸块和第二连接凸块来进行支撑的支撑基板;设置在支撑基板的第一表面上以面对封装基板的第一半导体管芯;设置在支撑基板的第一表面上以将第一连接凸块电连接至第一半导体管芯的第一再分配线(RDL)图案;设置在支撑基板的第一表面上以将第二连接凸块电连接至第一半导体管芯的第二RDL图案;层叠在支撑基板的与第一半导体管芯相对的第二表面上的第二半导体管芯;层叠在第二半导体管芯上的第三半导体管芯;电连接至第二半导体管芯的第一接合布线;以及电连接至第三半导体管芯的第二接合布线。封装基板包括:电连接至第一接合布线的第一布线接合指;电连接至第二接合布线的第二布线接合指;第一连接凸块所电连接至的第一凸块接合指;以及第二连接凸块所电连接至的第二凸块接合指。
根据另一个实施方式,一种层叠封装件包括:封装基板;安装在封装基板上的支撑基板,并且支撑基板由设置在支撑基板和封装基板之间的第一连接凸块和第二连接凸块支撑;设置在支撑基板的第一表面上以面对封装基板的第一半导体管芯;设置在支撑基板的第一表面上以将第一连接凸块电连接至第一半导体管芯的第一再分配线(RDL)图案;设置在支撑基板的第一表面上以将第二连接凸块电连接至第一半导体管芯的第二RDL图案;层叠在支撑基板的与第一半导体管芯相对的第二表面上的第二半导体管芯;以及将第二半导体管芯电连接至封装基板的接合布线。
附图说明
图1是例示根据实施方式的层叠封装件的截面图。
图2和图3是例示图1所示的层叠封装件的部分的放大截面图。
图4是例示图1所示的层叠封装件的布线接合指、连接凸块和管芯焊盘的平面图。
图5是例示图4所示的管芯焊盘的放大平面图。
图6是例示图4所示的连接凸块和管芯焊盘的平面图。
图7是例示根据实施方式的层叠封装件中所包括的封装基板的边缘部分的放大截面图。
图8是例示根据另一实施方式的层叠封装件的截面图。
图9是例示采用包括根据实施方式的至少一个层叠封装件的存储卡的电子系统的框图。
图10是例示包括根据实施方式的至少一个层叠封装件的另一电子系统的框图。
具体实施方式
本文使用的术语可以对应于考虑到它们在实施方式中的功能而选择的词,并且术语的含义可以根据实施方式所属领域的普通技术人员而解释为不同。如果详细定义了术语,则可以根据定义来解释术语。除非另有定义,否则本文中使用的术语(包括技术术语和科学术语)具有与实施方式所属领域的普通技术人员通常所理解的含义相同的含义。
将理解的是,尽管在本文中可以使用术语“第一”、“第二”、“第三”等来描述各种元件,但是这些元件不应受这些术语的限制。这些术语用于将一个元件与另一元件区分开,但不用于限定单个元件或者暗示元件的具体顺序或数量。
还应理解,当元件或层被称为在另一元件或层“上”、“上方”、“下”、“下方”或“外部”时,该元件或层可以直接接触另一元件或层,或者可以存在中间元件或层。应该以类似的方式来解释用于描述元件或层之间的关系的其它词语(例如,“在……之间”与“直接在……之间”或“相邻”与“直接相邻”)。
诸如“之下”、“下方”、“低于”、“上方”、“高于”、“顶”、“底”等的空间相对术语可以用于描述例如附图中所示出的元件和/或特征与另一元件和/或特征的关系。将理解的是,除了附图中描绘出的方位之外,空间相对术语还旨在涵盖装置在使用和/或操作中的不同方位。例如,当附图中的装置被翻转时,则被描述为在其它元件或特征之下和/或下方的元件将被定向为在其它元件或特征上方。装置可以以其它方式被定向(旋转90度或在其它方位)并且本文使用的空间相对描述符被相应地解释。
层叠封装件可以对应于半导体封装件,并且半导体封装件可以包括诸如半导体芯片或半导体管芯之类的电子装置。半导体芯片或半导体管芯可以通过使用管芯切割工艺将诸如晶圆之类的半导体基板分成多片来获得。半导体芯片可以对应于存储芯片、逻辑芯片或专用集成电路(ASIC)芯片。存储芯片可以包括集成在半导体基板上的动态随机存取存储器(DRAM)电路、静态随机存取存储器(SRAM)电路、NAND型闪存电路、NOR型闪存电路、磁随机存取存储器(MRAM)电路、电阻随机存取存储器(ReRAM)电路、铁电随机存取存储器(FeRAM)电路或相变随机存取存储器(PcRAM)电路。半导体封装件可以用于诸如移动电话之类的通信系统、与生物技术或医疗保健相关联的电子系统、或可穿戴电子系统。半导体封装件可以应用于物联网(IoT)。
在整个说明书中,相同的附图标记指代相同的元件。即使未参照一附图提及或描述附图标记,也可以参照另一附图提及或描述该附图标记。另外,即使附图标记在该附图中未示出,也可以参照另一附图来提及或描述该附图标记。
图1是例示根据实施方式的层叠封装件10的截面图。
参照图1,层叠封装件10可以被配置为包括封装基板100、支撑基板500、第一半导体管芯200和多个第二半导体管芯711。层叠封装件10还可以包括设置在支撑基板500上的第一再分配线(RDL)图案401和第二再分配线(RDL)图案402。层叠封装件10还可以包括多条第一接合布线801和多条第二接合布线802。
多个第二半导体管芯711可以垂直层叠以构成第一层叠物701。多个第三半导体管芯712可以附加层叠在第一层叠物701上。多个第三半导体管芯712可以垂直层叠以构成第二层叠物702。第二层叠物702可以层叠在第一层叠物701上。
可以使用多个第一连接凸块601和多个第二连接凸块602将支撑基板500安装在封装基板100上。可以通过第一连接凸块601和第二连接凸块602来支撑支撑基板500。第一连接凸块601和第二连接凸块602可以被定位为与第一半导体管芯200横向间隔开。支撑基板500可以具有第一表面501和相对的第二表面502。支撑基板500可以是支撑第二半导体管芯711和第三半导体管芯712的构件。第一半导体管芯200可以附接至支撑基板500。支撑基板500可以是其中不存在互连结构、导电图案或集成电路的基板。支撑基板500可以是绝缘基板或诸如硅基板之类的半导体基板。支撑基板500可以是由刚性材料组成的基板,以支撑第二半导体管芯711和第三半导体管芯712。
层叠封装件10还可以包括包封层900,该包封层900设置在封装基板100上以覆盖和保护支撑基板500、第一层叠物701、和第二层叠物702。包封层900可以包括各种包封材料中的任何之一。例如,包封层900可以包括诸如环氧成型化合物(EMC)材料之类的封装成型材料。
封装基板100可以包括将层叠封装件10电连接至外部装置的互连结构。封装基板100可以是印刷电路板(PCB)。支撑基板500可以设置在封装基板100的第一表面101上,并且外连接器109可以设置在封装基板100的与支撑基板500相对的第二表面102上。外连接器109可以包括能够连接至外部装置的连接构件。例如,外连接器109可以包括焊球。
第一布线接合指140和第二布线接合指170可以设置在封装基板100的第一表面101上。第一布线接合指140和第二布线接合指170可以设置在封装基板100的两相对端部上。也就是说,第一布线接合指140可以设置在封装基板100的第一端部的第一表面101上,并且第二布线接合指170可以设置在封装基板100的与第一端部相对的第二端部的第一表面101上。第一布线接合指140可以设置在封装基板100的第一端部上,以与支撑基板500的第一端部相邻,并且第二布线接合指170可以设置在封装基板100的第二端部上,以与支撑基板500的第二端部相邻。第一布线接合指140和第二布线接合指170可以分别设置在封装基板100的与支撑基板500交叠的部分的两侧。因此,第一布线接合指140可以通过封装基板100的与支撑基板500交叠的中央区域与第二布线接合指170分开。
第一接合布线801可以分别电连接至第一布线接合指140。第二接合布线802可以分别电连接至第二布线接合指170。第一接合布线801可以将第一层叠物701的第二半导体管芯711电连接至第一布线接合指140。第二接合布线802可以将第二层叠物702的第三半导体管芯712电连接至第二布线接合指170。第一接合布线801可以设置在第一层叠物701的第一侧,并且第二接合布线802可以设置在第一层叠物701的与第一接合布线801相对的第二侧。
第二半导体管芯711可以顺序地层叠为偏移以提供第一阶梯结构701S。例如,第二半导体管芯711可以顺序地层叠成在从第一布线接合指140指向第二布线接合指170的第一偏移方向上偏移。第二半导体管芯711可以层叠以露出要连接至第一接合布线801的其边缘部分。可以使用第一粘合层721将第二半导体管芯711附接至并层叠在支撑基板500上。
第三半导体管芯712可以顺序地层叠为偏移以提供第二阶梯结构702S。例如,第三半导体管芯712可以顺序地层叠成在从第二布线接合指170指向第一布线接合指140的第二偏移方向上偏移。第二偏移方向可以与第一偏移方向相反。第三半导体管芯712可以层叠以露出要连接至第二接合布线802的其边缘部分。可以使用第二粘合层722将第三半导体管芯712附接至并且层叠在第一层叠物701上。
第一接合布线801可以包括将封装基板100的第一布线接合指140电连接至与第一层叠物701的最底端管芯相对应的第二最底端半导体管芯711B的第一子接合布线811。第二最底端半导体管芯711B可以是第二半导体管芯711当中最靠近封装基板100的半导体管芯。支撑基板500的第一表面501可以面对封装基板100,并且支撑基板500的第二表面502可以面对第二最底端半导体管芯711B。第一接合布线801还可以包括将第二半导体管芯711彼此电连接的第二子接合布线821。第一子接合布线811可以电连接至第二子接合布线821。
第二接合布线802可以将第二接合指170电连接至包括第三半导体管芯712的第二层叠物702,并且可以延伸以将第三半导体管芯712彼此电连接。
第一凸块接合指150和第二凸块接合指180可以设置在封装基板100的第一表面101上。第一凸块接合指150可以电连接至第一布线接合指140。第一凸块接合指150可以通过设置在封装基板100的第一表面101上的第一互连线160电连接至第一布线接合指140。第二凸块接合指180可以通过设置在封装基板100的第一表面101上的第二互连线190电连接至第二布线接合指170。
第一连接凸块601可以分别物理地且机械地接合至并且电连接至第一凸块接合指150。第二连接凸块602可以分别物理地且机械地接合至并且电连接至第二凸块接合指180。第一连接凸块601和第二连接凸块602可以由基本相同的连接构件形成。例如,第一连接凸块601和第二连接凸块602中的每一个可以被配置为包括凸块主体611和导电粘合层612。凸块主体611可以形成为包括诸如铜材料之类的金属材料,并且导电粘合层612可以形成为包括焊料层。第一连接凸块601和第二连接凸块602的凸块主体611可以连接至支撑基板500,并且第一连接凸块601和第二连接凸块602的导电粘合层612可以连接至第一凸块接合指150和第二凸块接合指180。
第一连接凸块601和第二连接凸块602可以支撑支撑基板500,并且支撑基板500可以与封装基板100的第一表面101间隔开一距离。第一半导体管芯200可以设置在封装基板100的第一表面101上。第一半导体管芯200可以设置为使得第一半导体管芯200的第二表面202面对封装基板100的第一表面101。第一半导体管芯200还可以具有面对支撑基板500的第一表面201。第一连接凸块601和第二连接凸块602可以抬起支撑基板500,以在支撑基板500和封装基板100之间提供用于位于支撑基板500和封装基板100之间的第一半导体管芯200的空间。
多个第一管芯焊盘210和多个第二管芯焊盘220可以设置在第一半导体管芯200的第一表面201上。第一管芯焊盘210和第二管芯焊盘220可以是用于将第一半导体管芯200电连接至支撑基板500的连接焊盘。第一半导体管芯200可以设置在封装基板100的中央部分上。也就是说,第一半导体管芯200可以位于包括第一布线接合指140的边缘部分和包括第二布线接合指170的另一边缘部分之间。
第一半导体管芯200可以将第一层叠物701的第二半导体管芯711电连接至第二层叠物702的第三半导体管芯712。第一半导体管芯200可以被配置为包括控制第一层叠物701的第二半导体管芯711的操作和第二层叠物702的第三半导体管芯712的操作的控制器。第一层叠物701的第二半导体管芯711和第二层叠物702的第三半导体管芯712可以是存储数据的存储器半导体管芯。第一层叠物701的第二半导体管芯711和第二层叠物702的第三半导体管芯712可以是向第一半导体管芯200提供数据和存储通过第一半导体管芯200的控制操作所生成的数据的存储器半导体管芯。第二半导体管芯711和第三半导体管芯712可以是诸如NAND型闪存装置之类的非易失性存储器装置。
图2和图3是例示图1所示的层叠封装件10的部分(包括支撑基板500的部分)的放大截面图。
参照图1和图2,第一半导体管芯200可以通过第一半导体管芯200的第一管芯焊盘210、第一内凸块251、第一RDL图案401、第一连接凸块601、第一凸块接合指150、第一互连线160、第一布线接合指140和第一接合布线801电连接至第一层叠物701的第二半导体管芯711。这样,第一RDL图案401、第一连接凸块601、第一凸块接合指150、第一互连线160、第一布线接合指140和第一接合布线801可以提供用于第一半导体管芯200和第二半导体管芯711之间的通信的第一通道。
参照图1和图3,第一半导体管芯200可以通过第一半导体管芯200的第二管芯焊盘220、第二内凸块252、第二RDL图案402、第二连接凸块602、第二凸块接合指180、第二互连线190、第二布线接合指170和第二接合布线802电连接至第二层叠物702的第三半导体管芯712。这样,第二RDL图案402、第二连接凸块602、第二凸块接合指180、第二互连线190、第二布线接合指170和第二接合布线802可以提供用于第一半导体管芯200和第三半导体管芯712之间的通信的第二通道。第一半导体管芯200可以同时通过多个通道(即,第一通道和第二通道)与第二半导体管芯711和第三半导体管芯712进行通信。因此,可以提高层叠封装件10的操作速度。
再次参照图1和图2,第一RDL图案401可以将第一半导体管芯200电连接至第一连接凸块601。第一RDL图案401可以设置在支撑基板500的第一表面501上。第一RDL图案401的第一端可以电连接至第一内凸块251,并且第一RDL图案401可以延伸以使得第一RDL图案401的第二端电连接至第一连接凸块601。第一RDL图案401可以由金属层形成。第一RDL图案401可以包括铜材料或铝材料。第一RDL图案401中的每个可以是包括第一部分411、第一延伸部分412和第二部分413的导电图案。第一RDL图案401的第一部分411可以是第一连接凸块601所连接至的着陆件。第一RDL图案401的第一部分411可以设置在支撑基板500的第一表面501上,并且可以与第一半导体管芯200横向间隔开。第一RDL图案401的第二部分413可以设置为与第一半导体管芯200的第一管芯焊盘210垂直交叠并且可以通过第一内凸块251电连接至第一管芯焊盘210。第一RDL图案401的第一延伸部分412可以是将第一部分411电连接至第二部分413的线形图案。
再次参照图1和图3,第二RDL图案402可以在第一RDL图案401从第一半导体管芯200延伸的方向的相反方向上延伸。第二RDL图案402可以设置在支撑基板500的第一表面上,并且可以朝向第二连接凸块602延伸。第二RDL图案402可以将第一半导体管芯200电连接至第二连接凸块602。第二RDL图案402中的每个可以是包括第三部分415、第二延伸部分416和第四部分417的导电图案。第二RDL图案402的第三部分415可以是第二连接凸块602所连接至的着陆件。第二RDL图案402的第三部分415可以设置在支撑基板500的第一表面501上,并且可以与第一半导体管芯200横向间隔开。第二RDL图案402的第四部分417可以设置为与第一半导体管芯200的第二管芯焊盘220垂直交叠并且可以通过第二内凸块252电连接至第二管芯焊盘220。第二RDL图案402的第二延伸部分416可以是将第三部分415电连接至第四部分417的线形图案。
参照图2和图3,介电层350可以设置在支撑基板500的第一表面501上,以使第一RDL图案401和第二RDL图案402彼此电隔离和绝缘。介电层350可以包括阻焊剂层。内粘合层290可以设置在第一半导体管芯200的第一表面201和介电层350之间。第一半导体管芯200可以通过内粘合层290附接至支撑基板500。内粘合层290可以包括诸如底部填充材料或非导电膜(NCF)之类的介电材料。
第一内凸块251和第二内凸块252可以是将第一半导体管芯200电连接至第一RDL图案401和第二RDL图案402的连接构件。第一内凸块251和第二内凸块252可以具有相对小的直径以与具有相对小的直径D1的第一管芯焊盘210和第二管芯焊盘220接触。第一内凸块251和第二内凸块252可以具有小于第一连接凸块601和第二连接凸块602的直径D2的直径D3。
参照图2,第一电路径P1可以设置为包括第一管芯焊盘210、第一内凸块251、第一RDL图案401、第一连接凸块601、第一凸块接合指150、第一互连线160和第一布线接合指140。参照图3,第二电路径P2可以设置为包括第二管芯焊盘220、第二内凸块252、第二RDL图案402、第二连接凸块602、第二凸块接合指180、第二互连线190和第二布线接合指170。第一电路径P1中的一个可以设置为与第二电路径P2中的任何一个具有基本相同的长度。
在实施方式中,第一RDL图案401中的一个可以形成为与第二RDL图案402中的任何一个具有基本相同的长度。在平面图中,第一RDL图案401可以关于第一半导体管芯200与第二RDL图案402具有对称布局。在这种情况下,当从平面图观看时,第一半导体管芯200的第一管芯焊盘210也可以关于穿过第一半导体管芯200的中心点的直线(即,中心线)与第一半导体管芯200的第二管芯焊盘220对称。
第一凸块接合指150、第一互连线160和第一布线接合指140可以分别与第二凸块接合指180、第二互连线190和第二布线接合指170具有基本相同的长度和形状。当从平面图观看时,第一凸块接合指150、第一互连线160和第一布线接合指140可以设置为关于第一半导体管芯200与第二凸块接合指180、第二互连线190和第二布线接合指170中的相应一个对称。
由于上述布局,可以有效地减小在将第一半导体管芯200连接至第一层叠物701的第二半导体管芯711的路径与将第一半导体管芯200连接至第二层叠物(图1的702)的第三半导体管芯(图1的712)的路径之间的长度差。将第一半导体管芯200连接至第二半导体管芯711的路径可以设置为与将第一半导体管芯200连接至第二层叠物(图1的702)的第三半导体管芯(图1的712)的路径具有基本相同的长度。因此,第一半导体管芯200可以以基本相同的信号路由长度或相似的信号路由长度来访问第二半导体管芯711和第三半导体管芯712,从而提高层叠封装件10的信号完整性。
图4是例示图1所示的层叠封装件10的第一布线接合指140和第二布线接合指170、第一连接凸块601和第二连接凸块602以及第一管芯焊盘210和第二管芯焊盘220的平面图。图5是例示图4所示的第一半导体管芯200的第一管芯焊盘210和第二管芯焊盘220的放大平面图。图6是聚焦于图4的第一连接凸块601和第一管芯焊盘210的平面图。
参照图1和图4,与第二半导体管芯711和第三半导体管芯712相比,第一半导体管芯200可以具有相对小的尺寸或者小的宽度。为了将具有相对小尺寸的第一半导体管芯200设置在包括第二半导体管芯711的第一层叠物701下方,第一半导体管芯200可以设置为附接至支撑基板500的底表面。第一布线接合指140可以在安装有支撑基板500的封装基板100的第一部分上排列成列。第二布线接合指170可以在封装基板100的与第一布线接合指140所排列在其上的第一部分相对的第二部分上排列成列。在平面图中,第一布线接合指140所排列成的列和第二布线接合指170所排列成的列可以关于第一半导体管芯200基本对称。
支撑基板500可以使用第一连接凸块601和第二连接凸块602安装在封装基板100上。第一连接凸块601和第二连接凸块602可以设置在封装基板100和支撑基板500之间。当从平面图观看时,第一连接凸块601和第二连接凸块602可以设置为关于第一半导体管芯200对称。
将第一连接凸块601连接至第一半导体管芯200的第一管芯焊盘210的第一RDL图案401可以设置在支撑基板500上。将第二连接凸块602连接至第一半导体管芯200的第二管芯焊盘220的第二RDL图案402可以设置在支撑基板500上。
将第一布线接合指140连接至第一连接凸块601的第一互连线160可以设置在封装基板100上。将第二布线接合指170连接至第二连接凸块602的第二互连线190可以设置在封装基板100上。
通常,半导体管芯的输入/输出(I/O)端子可以设置在其中形成有分立器件(例如,MOS晶体管)的激活层的表面上。当I/O端子形成在第一半导体管芯200的表面201上时,能够设置在第一半导体管芯200的表面201上的I/O端子的数量会根据第一半导体管芯200的表面201的有限平面面积而受到限制。为了使第一半导体管芯200用作控制第二半导体管芯711和第三半导体管芯712的操作的控制器,第一半导体管芯200必须电连接至第二半导体管芯711和第三半导体管芯712。
参照图1、图4和图5,尽管第一半导体管芯200具有在其上设置I/O端子的表面201的有限面积并且I/O端子的数量正在增加,但是可能需要将第一半导体管芯200电连接至第二半导体管芯711和第三半导体管芯712。根据实施方式,将第一半导体管芯200连接至第二半导体管芯711的第一路径和将第一半导体管芯200连接至第三半导体管芯712的第二路径可以独立地提供,以构成多个通道。另选地,第二半导体管芯711可以通过至少两个通道信号地连接至第一半导体管芯200,并且第三半导体管芯712可以通过至少两个通道信号地连接至第一半导体管芯200。这样,如果在第一半导体管芯200与第二半导体管芯711和第三半导体管芯712之间建立多个通道,则第一半导体管芯200的I/O端子的数量可以显著增加。
随着第一半导体管芯200所需的I/O端子的数量增加,对应于I/O端子的第一管芯焊盘210和第二管芯焊盘220的数量也会增加。此外,随着半导体装置的制造技术的发展,半导体装置形成为更小,并具有相同功能甚至更复杂功能。在这种情况下,随着第一半导体管芯200的尺寸的减小,第一半导体管芯200的表面201的平面面积也会减小。为了增加设置在有限面积上的第一管芯焊盘210和第二管芯焊盘220的数量,第一管芯焊盘210和第二管芯焊盘220可以设置为沿着第一半导体管芯200的四个边缘具有环状图案。在实施方式中,第一管芯焊盘210和第二管芯焊盘220、或者第一管芯焊盘210和第二管芯焊盘220中的一些可以沿着第一半导体管芯200的边缘排列成至少两列。第一管芯焊盘210和第二管芯焊盘220中的一些可以以Z字图案沿着第一半导体管芯200的边缘排列成两列。
在示例性实施方式中,第一半导体管芯200可以具有两个相对边缘,例如,第一边缘291和第二边缘292。在这种情况下,第一组第一管芯焊盘210-1可以在第一半导体管芯200的与第一边缘291相邻的边缘区域上排列成第一列。第二组第一管芯焊盘210-2可以排列成与第一列相邻的第二列,第二列位于与第一边缘291相对。另外,第一组第二管芯焊盘220-1可以在第一半导体管芯200的与第二边缘292相邻的边缘区域上排列成第三列。第二组第二管芯焊盘220-2可以排列成与第三列相邻的第四列,第四列位于与第二边缘292相对。第一半导体管芯200还可以包括将第一边缘291连接至第二边缘292的两个附加的相对边缘,例如,第三边缘293和第四边缘294。在这种情况下,第一管芯焊盘中的附加管芯焊盘210-3和第二管芯焊盘中的附加管芯焊盘220-3可以排列在与第三边缘293和第四边缘294相邻的边缘区域上。第一管芯焊盘中的附加管芯焊盘210-3和第二管芯焊盘中的附加管芯焊盘220-3未排列在第一列至第四列中,而是沿着第三边缘293和第四边缘294排列,以与第一组第一管芯焊盘210-1和第二组第一管芯焊盘210-2以及第一组第二管芯焊盘220-1和第二组第二管芯焊盘220-2一起构成环状图案。
如上所述,第一管芯焊盘210和第二管芯焊盘220中的一些可以沿着第一边缘291和第二边缘292排列成两列,并且第一管芯焊盘210和第二管芯焊盘220中的其余管芯焊盘可以沿第三边缘293和第四边缘294排列。因此,第一管芯焊盘210和第二管芯焊盘220可以排列成在平面图中具有环状图案或圈形。因此,即使第一半导体管芯200的尺寸减小,也可以在不减少I/O端子的数量的情况下制造第一半导体管芯200。结果,即使第一半导体管芯200通过多个通道信号地连接至第二半导体管芯711和第三半导体管芯712,也可以排列相应数量的I/O端子。在诸如层叠封装件10之类的多芯片封装件的架构被实现为具有多个通道的情况下,与具有单通道架构的多芯片封装件相比,具有多通道架构的多芯片封装件的性能可以得到改善。
参照图4、图5和图6,第一管芯焊盘210可以通过第一RDL图案401电连接至第一连接凸块601。第二管芯焊盘220可以通过第二RDL图案402电连接至第二连接凸块602。第一半导体管芯200的第一管芯焊盘210和第二管芯焊盘220的尺寸D1(即,宽度)可以小于第一连接凸块601和第二连接凸块602的直径D2。如上所述,因为虽然第一半导体管芯200的尺寸减小但是第一半导体管芯200可能需要许多I/O端子,所以可能难以增大第一管芯焊盘210和第二管芯焊盘220的尺寸。此外,为了将支撑基板500安装在封装基板100上,可能需要即使封装基板100和支撑基板500在层叠封装件10的封装工艺期间变形也稳定地保持层叠封装件10中的电连接。因此,第一连接凸块601和第二连接凸块602的尺寸应大于一定值。例如,第一管芯焊盘210和第二管芯焊盘220可以形成为具有大约几微米到大约几十微米的尺寸D1(即,宽度),并且第一连接凸块601和第二连接凸块602可以形成为具有大约几十微米至大约几百微米的直径D2。因为第一管芯焊盘210和第二管芯焊盘220的尺寸D1相对小,所以可能难以将第一管芯焊盘210和第二管芯焊盘220直接连接至具有相对大值的直径D2的第一连接凸块601和第二连接凸块602。因此,第一连接凸块601和第二连接凸块602可以通过第一RDL图案401和第二RDL图案402分别连接至第一管芯焊盘210和第二管芯焊盘220。
第一连接凸块601可以沿着支撑基板500的与第一布线接合指140相邻的边缘设置,以与各个第一管芯焊盘210相对应。当第一管芯焊盘210排列成两列时,第一连接凸块601也可以排列成两列以与各个第一管芯焊盘210相对应。第一连接凸块601可以包括第一组第一连接凸块601-1和第二组第一连接凸块601-2。第一组第一连接凸块601-1可以排列成与支撑基板500的边缘相邻的第一列,并且第二组第一连接凸块601-2可以排列成位于第一列和第一半导体管芯200之间的第二列。第一连接凸块601可以以Z字图案排列成两列。因此,可以最大化或高效利用第一组第一连接凸块601-1与第二组第一连接凸块601-2之间的空间。第二连接凸块602也可以排列成两列以与排列成两列的各个第二管芯焊盘220相对应。第二连接凸块602可以以Z字图案排列成两列。与第一连接凸块601类似,第二连接凸块602可以包括第一组第二连接凸块602-1和第二组第二连接凸块602-2。
再次参照图4、图5和图6,第一连接凸块601可以设置为具有第二节距W2,该第二节距W2大于第一管芯焊盘210的第一节距W1。第一布线接合指140可以设置为具有小于第一连接凸块601的第二节距W2的第三节距W3。在第一布线接合指140当中,设置为彼此紧接着相邻的第一子布线接合指141和第二子布线接合指142可以设置为具有第三节距W3。在第一布线接合指140之间的距离当中,第一子布线接合指141和第二子布线接合指142之间的距离可以是最小的。因此,第三节距W3可以表示第一布线接合指140的节距当中的最小节距。
为了将第一管芯焊盘210设置为在有限面积中具有第一节距W1,第一管芯焊盘210可以排列成两列。排列成两列的第一管芯焊盘210的第一节距W1可以大于当第一管芯焊盘210排列成一列时第一管芯焊盘210的节距。因此,当形成连接至第一管芯焊盘210的第一RDL图案401时,可以最大化第一RDL图案401之间的距离。
第一布线接合指140可以设置为具有大于第一管芯焊盘210的第一节距W1的第三节距W3。因为第一布线接合指140形成为具有与第一管芯焊盘210的比例(scale)不同的比例,所以可能难以将第一布线接合指140直接连接至第一管芯焊盘210。因此,可能需要形成将第一布线接合指140电连接至第一管芯焊盘210的互连结构。第一RDL图案401、第一连接凸块601和第一互连线160可以用作将第一布线接合指140电连接至第一管芯焊盘210的互连结构。
参照图1和图4,第一连接凸块601可以通过用于导电粘合层612的焊接工艺而接合至第一凸块接合指150。在这种情况下,为了防止彼此相邻的第一连接凸块601由于焊接工艺不良而导致彼此不期望的连接,第一连接凸块601可以设置为具有大于第一布线接合指140的第三节距W3的第二节距W2。为了使第一连接凸起601设置为具有与相对大的节距相对应的第二节距W2,第一组第一连接凸块601-1和第二组第一连接凸块601-2可以以Z字图案排列成两列。
再次参照图1,支撑基板500的尺寸可以大于与第一层叠物701的最底端管芯相对应的第二最底端半导体管芯711B的尺寸。在实施方式中,支撑基板500可以与第一层叠物701的第二最底端半导体管芯711B具有基本相同的尺寸。第二最底端半导体管芯711B可以对应于第一层叠物701的第二半导体管芯711当中最接近于支撑基板500的第二半导体管芯711。因为支撑基板500与第二最底端半导体管芯711B具有相同的尺寸或具有比第二最底端半导体管芯711B的尺寸大的尺寸,所以第二最底端半导体管芯711B可以设置在支撑基板500上,而没有任何悬垂。因此,第二最底端半导体管芯711B可以设置为与支撑基板500完全交叠。此外,因为层叠在第二最底端半导体管芯711B上的其余第二半导体管芯711能够没有任何悬垂地设置,所以可以在支撑基板500上形成稳定的层叠结构。
图7是例示根据实施方式的层叠封装件10中所包括的支撑基板500的边缘部分500E的放大截面图。
参照图7,支撑基板500可以设置在封装基板100上,以当从平面图观看时具有从第一层叠物701的侧表面突出的突出部500P。在平面图中,支撑基板500的突出部500P可以从第一层叠物701中所包括的第二最底端半导体管芯711B的侧表面突出。第二最底端半导体管芯711B可以设置在支撑基板500上,使得当从平面图观看时支撑基板500的边缘部分500E的一部分从第二最底端半导体管芯711B的侧表面突出。
第一连接凸块601当中的第一组第一连接凸块601-1可以定位为与支撑基板500的突出部500P垂直地交叠。因此,第一组第一连接凸块601-1可以稳定地支撑支撑基板500的突出部500P。
第一连接凸块601当中的第二组第一连接凸块601-2可以定位为与连接部分811A垂直交叠,在连接部分811A处第一接合布线801连接至第二半导体管芯711当中的最靠近支撑基板500的第二最底端半导体管芯711B。
第二组第一连接凸块601-2可以设置为与第二最底端半导体管芯711B的边缘部分711E垂直交叠。与第一子接合布线811的第一端相对应的连接部分811A可以接合至第二最底端半导体管芯711B的边缘部分711E。第二组第一连接凸块601-2可以与第一接合布线801的连接部分811A部分地或完全地交叠。因此,当第一接合布线801接合至第二最底端半导体管芯711B时,第二组第一连接凸块601-2可以支撑第二最底端半导体管芯711B的边缘部分711E,使得支撑基板500和第二最底端半导体管芯711B不会被接合压力损坏。因此,第一接合布线801可以更稳定地接合至第二最底端半导体管芯711B。
为了使第二组第一连接凸块601-2定位为与第一接合布线801的连接部分811A交叠,支撑基板500的边缘部分500E可以延伸以与第一接合布线801的连接部分811A交叠。
图8是例示根据另一实施方式的层叠封装件11的截面图。在图8中,与图1中使用的附图标记相同的附图标记指代相同的元件。
参照图8,层叠封装件11可以包括封装基板100、支撑基板500、第一半导体管芯200、包括第二半导体管芯711的第一层叠物701、包括第三半导体管芯712的第二层叠物702、第一接合布线801和第二接合布线802、第一连接凸块601和第二连接凸块602、以及包封层900。第二半导体管芯711可以层叠在支撑基板500上以提供第一阶梯结构701S,并且第三半导体管芯712可以层叠在第一层叠物701上以提供第二阶梯结构702S。第一RDL图案401和第二RDL图案402可以设置在支撑基板500上。
虚设凸块604可以设置在第一连接凸块601所设置于的位置与第二连接凸块602所设置于的位置之间。虚设凸块604可以包括至少两个凸块,以支撑支撑基板500。虚设凸块604可以设置在介电层350上。因为虚设凸块604设置在介电层350上,所以第一RDL图案401和第二RDL图案402可以通过介电层350与虚设凸块604电绝缘和隔离。封装基板100还可以包括虚设凸块604所接合至的虚设指120。第一虚设指120可以是类似于第一布线接合指140的导电图案。虚设凸块604可以形成为与第一连接凸块601具有基本相同的形状或者与第一连接凸块601具有相似的形状。
虚设凸块604可以设置为与支撑基板500的一些部分垂直交叠,并且可以在水平方向上与第一半导体管芯200间隔开。虚设凸块604可以设置为与第一连接凸块601和第二连接凸块602相邻。例如,虚设凸块604中的一些可以设置为与第二组第一连接凸块601-2相邻。当第一接合布线801接合至第二半导体管芯711时,如上所述设置的虚设凸块604可以附加地支撑第二半导体管芯711。因此,可以防止由于接合压力导致支撑基板500被损坏或第二半导体管芯711弯曲。结果,可以有效地抑制或减轻接合失败的发生。
虚设凸块604可以包括设置在第一连接凸块601所设置于的位置与第二连接凸块602所设置于的位置之间的至少两个凸块。虚设凸块604可以使包封层900更容易地填充支撑基板500和封装基板100之间的空间。在用于形成包封层900的成型工艺期间,成型材料可以填充支撑基板500和封装基板100之间的空间。虚设凸块604可以分散成型材料,以使成型材料在成型工艺期间均匀流动。因此,当执行成型工艺时,虚设凸块604可以防止、抑制或减少在支撑基板500与封装基板100之间的空间中产生空隙。
在实施方式中,支撑基板500和封装基板100之间的空间可以用底部填充材料填充。在这种情况下,虚设凸块604可以改善底部填充材料的可流动性,以降低在支撑基板500与封装基板100之间的空间中形成空隙的可能性或防止在支撑基板500与封装基板100之间的空间中形成空隙。
图9是例示包括采用根据实施方式的至少一个层叠封装件的存储卡7800的电子系统的框图。存储卡7800包括诸如非易失性存储器装置之类的存储器7810和存储器控制器7820。存储器7810和存储器控制器7820可以存储数据或读出所存储的数据。存储器7810和存储器控制器7820中的至少一个可以包括根据实施方式的至少一个层叠封装件。
存储器7810可以包括应用本公开的教导的非易失性存储器装置。存储器控制器7820可以控制存储器7810,使得响应于来自主机7830的读取/写入请求,而读出所存储的数据或对数据进行存储。
图10是例示包括根据实施方式的至少一个层叠封装件的电子系统8710的框图。电子系统8710可以包括控制器8711、输入/输出单元8712和存储器8713。控制器8711、输入/输出单元8712和存储器8713可以通过提供数据移动所经由的路径的总线8715彼此联接。
在实施方式中,控制器8711可以包括微处理器、数字信号处理器、微控制器和/或能够执行与这些组件相同的功能的逻辑器件中的一个或更多个。控制器8711或存储器8713可以包括根据本公开的实施方式的至少一个层叠封装件。输入/输出单元8712可以包括从小键盘、键盘、显示装置、触摸屏等当中选择的至少一个。存储器8713是用于存储数据的装置。存储器8713可以存储控制器8711要执行的命令和/或数据等。
存储器8713可以包括诸如DRAM之类的易失性存储器装置和/或诸如闪存之类的非易失性存储器装置。例如,闪存可以安装到诸如移动终端或台式计算机之类的信息处理系统。闪存可以构成固态盘(SSD)。在这种情况下,电子系统8710可以在闪存系统中稳定地存储大量数据。
电子系统8710还可以包括被配置为向通信网络发送数据和从通信网络接收数据的接口8714。接口8714可以是有线型或无线型。例如,接口8714可以包括天线、或者有线或无线收发器。
电子系统8710可以实现为执行各种功能的移动系统、个人计算机、工业计算机或逻辑系统。例如,移动系统可以是个人数字助理(PDA)、便携式计算机、平板计算机、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐系统、以及信息发送/接收系统中的任何之一。
如果电子系统8710表示能够执行无线通信的装备,则电子系统8710可以用于使用CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强型时分多址)、WCDAM(宽带码分多址)、CDMA2000、LTE(长期演进)、或Wibro(无线宽带互联网)的技术的通信系统中。
已经出于示例的目的公开了本公开的实施方式。本领域技术人员将理解,在不脱离本公开和所附权利要求的范围和精神的情况下,可以进行各种修改、添加和替换。
相关申请的交叉引用
本申请要求于2019年6月17日提交的韩国申请No.10-2019-0071504的优先权,其全部内容通过引用合并于此。
Claims (29)
1.一种层叠封装件,该层叠封装件包括:
封装基板;
支撑基板,所述支撑基板安装在所述封装基板上,并由设置在所述支撑基板和所述封装基板之间的第一连接凸块和第二连接凸块支撑;
第一半导体管芯,所述第一半导体管芯设置在所述支撑基板的第一表面上,使得所述第一半导体管芯的第一表面面对所述封装基板;
第一再分配线RDL图案,所述第一RDL图案设置在所述支撑基板的所述第一表面上以将所述第一连接凸块电连接至所述第一半导体管芯;
第二RDL图案,所述第二RDL图案设置在所述支撑基板的所述第一表面上以将所述第二连接凸块电连接至所述第一半导体管芯;
第二半导体管芯,所述第二半导体管芯层叠在所述支撑基板的与所述第一半导体管芯相对的第二表面上;
第三半导体管芯,所述第三半导体管芯层叠在所述第二半导体管芯上;
第一接合布线,所述第一接合布线电连接至所述第二半导体管芯;以及
第二接合布线,所述第二接合布线电连接至所述第三半导体管芯,
其中,所述封装基板包括:
第一布线接合指,所述第一布线接合指电连接至所述第一接合布线;
第二布线接合指,所述第二布线接合指电连接至所述第二接合布线;
第一凸块接合指,所述第一连接凸块电连接至所述第一凸块接合指;以及
第二凸块接合指,所述第二连接凸块电连接至所述第二凸块接合指。
2.根据权利要求1所述的层叠封装件,
其中,所述第二半导体管芯层叠成沿从所述第一布线接合指指向所述第二布线接合指的第一偏移方向偏移,以提供第一阶梯结构;
其中,所述第三半导体管芯层叠成沿从所述第二布线接合指指向所述第一布线接合指的第二偏移方向偏移,以提供第二阶梯结构;并且
其中,所述第二偏移方向是所述第一偏移方向的相反方向。
3.根据权利要求1所述的层叠封装件,其中,
所述第一布线接合指和所述第二布线接合指位于所述封装基板上彼此相对的位置处并且所述支撑基板和所述第一半导体管芯在所述第一布线接合指和所述第二布线接合指之间。
4.根据权利要求1所述的层叠封装件,其中,所述第一半导体管芯设置在所述封装基板的位于所述第一布线接合指和所述第二布线接合指之间的中央部分上方。
5.根据权利要求1所述的层叠封装件,其中,所述第一连接凸块和所述第二连接凸块与所述第一半导体管芯间隔开。
6.根据权利要求1所述的层叠封装件,其中,所述封装基板还包括:
第一互连线,所述第一互连线将所述第一布线接合指分别电连接至所述第一凸块接合指;以及
第二互连线,所述第二互连线将所述第二布线接合指分别电连接至所述第二凸块接合指。
7.根据权利要求6所述的层叠封装件,其中,所述第一半导体管芯包括:
第一管芯焊盘,所述第一管芯焊盘分别电连接至所述第一RDL图案;以及
第二管芯焊盘,所述第二管芯焊盘分别电连接至所述第二RDL图案,
其中,所述第一管芯焊盘和所述第二管芯焊盘的宽度小于所述第一连接凸块和所述第二连接凸块的直径。
8.根据权利要求7所述的层叠封装件,该层叠封装件还包括:
第一内凸块,所述第一内凸块将所述第一管芯焊盘电连接至所述第一RDL图案;以及
第二内凸块,所述第二内凸块将所述第二管芯焊盘电连接至所述第二RDL图案,
其中,所述第一内凸块和所述第二内凸块设置在所述第一半导体管芯与所述支撑基板的所述第一表面之间,并且具有比所述第一连接凸块和所述第二连接凸块的直径小的直径。
9.根据权利要求8所述的层叠封装件,其中,
其中,所述第一管芯焊盘、所述第一内凸块、所述第一RDL图案、所述第一连接凸块、所述第一凸块接合指、所述第一互连线和所述第一布线接合指组成第一电路径;并且
其中,所述第二管芯焊盘、所述第二内凸块、所述第二RDL图案、所述第二连接凸块、所述第二凸块接合指、所述第二互连线和所述第二布线接合指组成第二电路径。
10.根据权利要求9所述的层叠封装件,其中,所述第一电路径分别与所述第二电路径具有相同长度。
11.根据权利要求7所述的层叠封装件,其中,所述第一半导体管芯的所述第一管芯焊盘沿着所述第一半导体管芯的边缘以Z字图案排列成两列。
12.根据权利要求11所述的层叠封装件,其中,所述第一连接凸块以Z字图案排列成两列,以对应于以Z字图案排列成两列的所述第一管芯焊盘。
13.根据权利要求7所述的层叠封装件,其中,所述第一连接凸块设置为具有比所述第一管芯焊盘的节距大的节距。
14.根据权利要求13所述的层叠封装件,其中,所述第一布线接合指设置为具有比所述第一连接凸块的节距小的节距。
15.根据权利要求7所述的层叠封装件,其中,所述第一管芯焊盘和所述第二管芯焊盘沿着所述第一半导体管芯的边缘以环状图案设置。
16.根据权利要求7所述的层叠封装件,
其中,所述第一管芯焊盘和所述第二管芯焊盘设置在所述第一半导体管芯的所述第一表面上;
其中,在所述第一半导体管芯的所述第一表面上,所述第一管芯焊盘与所述第二管芯焊盘对称;
其中,所述第一连接凸块设置为关于所述第一半导体管芯的中心线与所述第二连接凸块对称;并且
其中,所述第一布线接合指设置为关于所述第一半导体管芯的所述中心线与所述第二布线接合指对称。
17.根据权利要求1所述的层叠封装件,其中,所述第一半导体管芯的尺寸小于所述第二半导体管芯的尺寸。
18.根据权利要求1所述的层叠封装件,其中,所述支撑基板的尺寸基本等于或大于所述第二半导体管芯当中被层叠为最靠近所述支撑基板的所述第二表面的第二最底端半导体管芯的尺寸。
19.根据权利要求18所述的层叠封装件,其中,所述第二最底端半导体管芯设置为与所述支撑基板完全交叠。
20.根据权利要求1所述的层叠封装件,其中,所述支撑基板具有从包括所述第二半导体管芯的第一层叠物的侧表面突出的突出部。
21.根据权利要求20所述的层叠封装件,其中,多个所述第一连接凸块中的至少一个被定位为与所述支撑基板的所述突出部垂直交叠。
22.根据权利要求1所述的层叠封装件,其中,多个所述第一连接凸块中的一些被定位为与连接部分垂直交叠,在所述连接部分处所述第一接合布线连接至所述第二半导体管芯当中最靠近所述支撑基板的第二最底端半导体管芯。
23.根据权利要求1所述的层叠封装件,其中,所述支撑基板延伸以与连接部分交叠,在所述连接部分处所述第一接合布线连接至所述第二半导体管芯当中最靠近所述支撑基板的第二最底端半导体管芯。
24.根据权利要求1所述的层叠封装件,该层叠封装件还包括设置在所述第一连接凸块和所述第二连接凸块之间的虚设凸块,其中,所述虚设凸块被配置为支撑所述支撑基板。
25.根据权利要求24所述的层叠封装件,该层叠封装件还包括介电层,所述介电层设置在所述支撑基板的所述第一表面上以覆盖所述第一RDL图案和所述第二RDL图案并使所述第一RDL图案和所述第二RDL图案彼此电隔离和绝缘,
其中,所述虚设凸块被附接至所述介电层的表面。
26.根据权利要求1所述的层叠封装件,其中,所述支撑基板包括硅。
27.一种层叠封装件,该层叠封装件包括:
封装基板;
支撑基板,所述支撑基板安装在所述封装基板上并由设置在所述支撑基板和所述封装基板之间的第一连接凸块和第二连接凸块支撑;
第一半导体管芯,所述第一半导体管芯设置在所述支撑基板的第一表面上以面对所述封装基板;
第一再分配线RDL图案,所述第一RDL图案设置在所述支撑基板的所述第一表面上以将所述第一连接凸块电连接至所述第一半导体管芯;
第二RDL图案,所述第二RDL图案设置在所述支撑基板的所述第一表面上以将所述第二连接凸块电连接至所述第一半导体管芯;
第二半导体管芯,所述第二半导体管芯层叠在所述支撑基板的与所述第一半导体管芯相对的第二表面上;以及
接合布线,所述接合布线将所述第二半导体管芯电连接至所述封装基板。
28.根据权利要求27所述的层叠封装件,该层叠封装件还包括设置在所述第一连接凸块和所述第二连接凸块之间的虚设凸块,其中,所述虚设凸块被配置为支撑所述支撑基板。
29.根据权利要求28所述的层叠封装件,该层叠封装件还包括:介电层,所述介电层设置在所述支撑基板的所述第一表面上以覆盖所述第一RDL图案和所述第二RDL图案并且使所述第一RDL图案和所述第二RDL图案彼此电隔离和绝缘,
其中,所述虚设凸块被附接至所述介电层的表面。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070287265A1 (en) * | 2006-05-25 | 2007-12-13 | Sony Corporation | Substrate treating method and method of manufacturing semiconductor apparatus |
CN101276809A (zh) * | 2007-03-30 | 2008-10-01 | 日本电气株式会社 | 半导体器件及其制造方法 |
US20080315406A1 (en) * | 2007-06-25 | 2008-12-25 | Jae Han Chung | Integrated circuit package system with cavity substrate |
US20110095418A1 (en) * | 2009-10-26 | 2011-04-28 | Hwan-Sik Lim | Semiconductor package and method for fabricating the same |
US20150035142A1 (en) * | 2013-08-05 | 2015-02-05 | Samsung Electronics Co., Ltd. | Multi-chip package |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070287265A1 (en) * | 2006-05-25 | 2007-12-13 | Sony Corporation | Substrate treating method and method of manufacturing semiconductor apparatus |
CN101276809A (zh) * | 2007-03-30 | 2008-10-01 | 日本电气株式会社 | 半导体器件及其制造方法 |
US20080315406A1 (en) * | 2007-06-25 | 2008-12-25 | Jae Han Chung | Integrated circuit package system with cavity substrate |
US20110095418A1 (en) * | 2009-10-26 | 2011-04-28 | Hwan-Sik Lim | Semiconductor package and method for fabricating the same |
US20150035142A1 (en) * | 2013-08-05 | 2015-02-05 | Samsung Electronics Co., Ltd. | Multi-chip package |
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