CN108878414B - 具有模制通孔的堆叠半导体封装及其制造方法 - Google Patents

具有模制通孔的堆叠半导体封装及其制造方法 Download PDF

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CN108878414B
CN108878414B CN201711162896.3A CN201711162896A CN108878414B CN 108878414 B CN108878414 B CN 108878414B CN 201711162896 A CN201711162896 A CN 201711162896A CN 108878414 B CN108878414 B CN 108878414B
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semiconductor chip
semiconductor
disposed
pad
chip
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CN108878414A (zh
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李尙垠
李炯东
高银
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SK Hynix Inc
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    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

一种具有模制通孔的堆叠半导体封装及其制造方法，该半导体封装包括：第一半导体芯片，其具有第一有源表面，包括周边键合焊盘和中心键合焊盘的第一键合焊盘布置在第一有源表面的上方；第一包封构件；两个第二半导体芯片，其具有第二有源表面，第二键合焊盘在第二有源表面上方布置在一个侧周边处并且被设置成彼此分离，使得第二有源表面面对第一有源表面，并且第二键合焊盘与周边键合焊盘交叠；第一联接构件，其插置在周边键合焊盘和第二键合焊盘之间；第二包封构件，其形成在第二半导体芯片的第二侧表面上方，包括第二半导体芯片之间的区域；以及模制通孔，其通过第二包封构件的在第二半导体芯片之间的区域中的一部分形成并且与中心键合焊盘联接。

Description

具有模制通孔的堆叠半导体封装及其制造方法
技术领域
各种实施方式总体上涉及半导体封装，并且更具体地，涉及具有模制通孔的堆叠半导体封装及其制造方法。
背景技术
随着电子产品变得越来越小，需要具有更高能力的更复杂的半导体芯片来满足所需的功能。另外，已经变得有必要将更多数量的半导体芯片安装在较小尺寸的电子产品中。
但是，制造具有更高能力的半导体芯片或者在有限空间中安装数量增大的半导体芯片的技术不免会有限制。在这种情形下，最近趋势涉及在一个封装中嵌入数量增加的半导体芯片。
在这方面，正在开发能够将不同种类的芯片嵌入一个封装中并且堆叠两个或更多个芯片而不增加封装整个厚度的技术。另外，正在开发能够改善堆叠半导体芯片的电特性的各种技术。
发明内容
在实施方式中，一种堆叠半导体封装可包括：第一半导体芯片，该第一半导体芯片具有第一有源表面，包括周边键合焊盘和中心键合焊盘的第一键合焊盘布置在所述第一有源表面的上方。所述堆叠半导体封装可包括第一包封构件，所述第一包封构件形成在所述第一半导体芯片的至少第一侧表面的上方。所述堆叠半导体封装可包括两个第二半导体芯片，所述两个第二半导体芯片具有第二有源表面，第二键合焊盘在所述第二有源表面上方布置在与所述第一半导体芯片相邻的侧周边处，并且所述两个第二半导体芯片被设置成彼此分离，使得所述第二有源表面面对所述第一有源表面，并且所述第二键合焊盘与所述周边键合焊盘交叠。所述堆叠半导体封装可包括第一联接构件，所述第一联接构件插入所述第一半导体芯片的所述周边键合焊盘和所述第二半导体芯片的所述第二键合焊盘之间。所述堆叠半导体封装可包括第二包封构件，所述第二包封构件形成在所述第二半导体芯片的第二侧表面上方，包括所述第二半导体芯片之间的区域。所述堆叠半导体封装可包括模制通孔，该模制通孔通过所述第二包封构件的在所述第二半导体芯片之间的所述区域中的一部分形成并且与所述中心键合焊盘联接。
在实施方式中，一种用于制造堆叠半导体封装的方法，该方法包括以下步骤：在载体晶圆的上方设置第一半导体芯片，所述第一半导体芯片具有第一有源表面，所述第一有源表面上方布置有包括周边键合焊盘和中心键合焊盘的第一键合焊盘，使得所述载体晶圆和所述第一有源表面彼此面对；所述载体晶圆上的上方形成覆盖所述第一半导体芯片的第一包封构件，使得构造成其中重新设置有所述第一半导体芯片的重新配置晶圆；从所述重新配置晶圆中去除所述载体晶圆；将两个第二半导体芯片彼此以一定距离键合于所述重新配置晶圆上的一个第一半导体芯片，其中，所述第二半导体芯片具有第二有源表面，第二键合焊盘在所述第二有源表面上方布置在与所述第一半导体芯片相邻的侧周边处，其中，所述第二半导体芯片具有形成在所述第二键合焊盘上的第一联接构件，其中，所述第二半导体所拥有的厚度大于目标厚度，并且其中，所述第二半导体芯片设置在所述重新配置晶圆上，使得所述第二有源表面面对所述第一有源表面，所述第二键合焊盘通过所述第一联接构件与所述周边键合焊盘联接并且所述中心键合焊盘被暴露；在所述重新配置晶圆的上方以覆盖所述第二半导体芯片的方式形成第二包封构件；去除所述第二包封构件和所述第二半导体芯片的部分厚度，使得保持所述第二半导体芯片的目标厚度；以及形成模制通孔，所述模制通孔与所述第一半导体芯片的所述中心键合焊盘联接，并且穿过所述第二半导体芯片之间的区域中的所述第二包封构件的一部分。
附图说明
图1是例示了根据实施方式的堆叠半导体封装的示例的表示的截面图。
图2A至图2J是有助于说明根据实施方式的制造堆叠半导体封装的方法的处理的横截图的示例的表示。
图3是例示了根据实施方式的堆叠半导体封装的示例的表示的截面图。
图4是例示了根据实施方式的堆叠半导体封装的示例的表示的截面图。
图5是例示了可应用根据各种实施方式的半导体封装的电子系统的示例的表示的框图。
图6是例示了可包括根据各种实施方式的半导体封装的存储卡的示例的表示的框图。
具体实施方式
下文中，以下将通过实施方式的各个示例参照附图来描述具有模制通孔的堆叠半导体封装及其制造方法。
这些实施方式提供了具有模制通孔的堆叠半导体封装及其制造方法。
参照图1，根据实施方式的堆叠半导体封装100可包括第一半导体芯片10、第一包封构件20、第二半导体芯片30、第一联接构件40、第二包封构件50、模制通孔60、第二联接构件70和基板80。堆叠半导体封装100还可包括凸块焊盘62、虚设焊盘64和支撑构件72。堆叠半导体封装100还可包括第三包封构件90和外部联接构件92。
第一半导体芯片10可以是存储器芯片或逻辑芯片。例如，第一半导体芯片10可以是逻辑芯片。第一半导体芯片10可具有四边形板的形状。第一半导体芯片10可具有第一有源表面10a和背离第一有源表面10a的第一表面10b。第一半导体芯片10可包括在第一有源表面10a上布置成矩阵形式的多个第一键合焊盘12。
第一键合焊盘12可设置在第一有源表面10a中。与此不同，第一键合焊盘12可设置在第一有源表面10a上。当沿第一方向X观察时，第一键合焊盘12可被分成周边键合焊盘12a和中心键合焊盘12b，周边键合焊盘12a设置在第一有源表面10a的两侧周边，中心键合焊盘12b设置在第一有源表面10a的周边键合焊盘12a之间。在实施方式中，周边键合焊盘12a可第一有源表面10a的每侧的周边处布置成三条线，并且中心键合焊盘12b可在第一有源表面10a的两侧周边处的周边键合焊盘12a之间布置成五条线。
第一半导体芯片10可以以面向下的类型设置，使得第一键合焊盘12布置在其上的第一有源表面10a面向下。
尽管未示出，但是可理解，第一半导体芯片10在第一有源表面10a上形成有钝化层，暴露第一键合焊盘12。
第一包封构件20可被形成为覆盖第一半导体芯片10的第一侧表面10c。第一包封构件20可被形成为不覆盖第一半导体芯片10的第一有源表面10a和第一表面10b。第一包封构件20的第一前表面20a可被设置成与第一半导体芯片10的第一有源表面10a共面，并且第一包封构件20的第一后表面20b可被设置成与第一半导体芯片10的第一表面10b共面。第一包封构件20可由环氧成型化合物形成。虽然未示出，但是在其它实施方式中，第一包封构件20可被形成为不覆盖第一半导体芯片10的第一有源表面10a，而是覆盖第一半导体芯片10的第一表面10b和第一侧表面10c。根据该事实，第一包封构件20保护第一半导体芯片10的第一表面10b免受外部环境的影响。
第二半导体芯片30可沿第二方向Y设置在第一半导体芯片10和第一包封构件20的下面。可按这种方式来设置两个第二半导体芯片30。第二半导体芯片30中的每个可具有四边形板的形状。第二半导体芯片30中的每个可具有第一有源表面30a和背离第二有源表面30a的第二表面30b。第二半导体芯片30中的每个可包括在第二有源表面30a上布置的多个第二键合焊盘32。
在第二半导体芯片30中的每个中，第二键合焊盘32可设置在当沿第一方向X观察时与第一半导体芯片10相邻的一个侧周边处。例如，在设置在第一半导体芯片10的左下侧的第二半导体芯片30中，第二键合焊盘32可设置在第二有源表面30a的右侧周边处，并且在设置在第一半导体芯片10的右下侧的第二半导体芯片30中，第二键合焊盘32可设置在第二有源表面30a的左侧周边处。
第二半导体芯片30可按第一半导体芯片10和第一包封构件20的面向上的类型设置，使得第二半导体芯片30的第二有源表面30a面对第一半导体芯片10的第一有源表面10a。第二半导体芯片30可被设置成彼此分离，使得第二半导体芯片30与第一半导体芯片10的周边键合焊盘12a交叠，并且暴露第一半导体芯片10的中心键合焊盘12b。第一半导体芯片10的周边键合焊盘12a和第二半导体芯片30的第二键合焊盘32可一一对应地彼此交叠。
第二半导体芯片30可以是与第一半导体芯片10不同的一种芯片。例如，如果第一半导体芯片10是逻辑芯片，则第二半导体芯片30可以是存储器芯片。尽管未示出，但是可理解，第二半导体芯片30中的每个在第一有源表面30a上形成有钝化层，暴露第二键合焊盘32。第二键合焊盘32可设置在第二有源表面30a中，如所例示的。与此不同，虽然未示出，但是在其它实施方式中，第二键合焊盘32可设置在第二有源表面30a上。
第一联接构件40可分别插入第一半导体芯片10的周边键合焊盘12a和第二半导体芯片30的第二键合焊盘32之间，以便将被设置成彼此交叠的周边键合焊盘12a和第二键合焊盘32电联接。第一联接构件40可由凸块构成。第一联接构件40可形成在第二半导体芯片30的第二键合焊盘32上。第二半导体芯片30可通过第一联接构件40以倒装芯片方式与第一半导体芯片10的第一有源表面10a键合。
第二包封构件50可被形成为覆盖第二半导体芯片30的第二有源表面30a和第二侧表面30c。第二包封构件50可被形成为不覆盖第二半导体芯片30的第二表面30b。第二包封构件50可被形成为填充第二半导体芯片30之间的区域。第二包封构件50的第二前表面50a可被设置成与第一半导体芯片10的第一有源表面10a和第一包封构件20的第一前表面20a接触，并且第二包封构件50的第二后表面50b可被设置成与第二半导体芯片30的第二表面30b共面。第二包封构件50可按与第一包封构件20相同的方式由环氧模制化合物形成。第二包封构件50和第二半导体芯片30的总宽度可与第一半导体芯片10和第一包封构件20的总宽度基本上相同。
模制通孔60可被形成为将第一半导体芯片10和基板80电联接。可通过第二半导体芯片30之间的第二包封构件50的一部分形成模制通孔60。模制通孔60可被形成为穿过第二包封构件50的第二前表面50a和第二后表面50b。模制通孔60可与第二包封构件50的第二前表面50a上的第一半导体芯片10的中心键合焊盘12b联接。模制通孔60可被形成为在第二包封构件50中形成的穿通孔，然后在穿通孔中填充诸如金属层的导电层。
在该实施方式中，凸块焊盘62可形成在模制通孔60的设置在第二包封构件50的第二后表面50b处的一些部分的上面或下面。虚设焊盘64可形成在当沿第一方向X观察时不与模制通孔60相邻的第二半导体芯片30的第二表面30b的侧周边的下面和在该周边处。凸块焊盘62和虚设焊盘64可被形成为金属图案。
第二联接构件70可形成在凸块焊盘62的上面或下面。支撑构件72可形成在虚设焊盘64的上面或下面。第二联接构件70和支撑构件72可由凸块构成。通过第二联接构件70，包括第一半导体芯片10、第一包封构件20、第二半导体芯片30和第二包封构件50的芯片堆叠能够以倒装芯片方式与基板80的顶表面80a键合。虚设焊盘64和支撑构件72的堆叠可被形成为在对芯片堆叠进行倒装芯片键合时确保结构稳定性，并且可设置在当沿第一方向X观察时没有与模制通孔60相邻的第二半导体芯片30的第二表面30b的侧周边处。
基板80可设置在第二半导体芯片30和第二包封构件50的下面。基板80可被设置成面对第二半导体芯片30的第二表面30b和第二包封构件50的第二后表面50b。基板80可以是印刷电路板，并且具有四边形板的形状。基板80的尺寸可大于第二半导体芯片30和第二包封构件50的总尺寸。基板80可具有顶表面80a和背离顶表面80a的底表面80b。基板80可包括布置在顶表面80a上的多个键合指状物82和布置在底表面80b的上面或下面的多个电极端子84。
键合指状物82可设置在基板80的顶表面80a的中心部分处。键合指状物82可按与对应于其的模制通孔60交叠这样的方式进行设置。因此，键合指状物82可通过第二联接构件70与包括凸块焊盘62的模制通孔60电联接。结果，键合指状物82可通过第二联接构件70、凸块焊盘62和模制通孔60与第一半导体芯片10的中心键合焊盘12b电联接。
电极端子84可例如在基板80的底表面80b的上面或下面布置成例如矩阵的形式。电极端子84可与形成在基板80中的内部布线(未示出)联接，并且可与通过内部布线布置在基板80的顶表面80a上的键合指状物82电联接。
第三包封构件90可形成在基板80的顶表面80a的上面或上方。更清楚地，第三包封构件90可被形成为不覆盖第一包封构件20的第一后表面20b和第一半导体芯片10的第一表面10b。第三包封构件90可被形成为覆盖第一包封构件20和第二包封构件50的侧表面。第三包封构件90可被形成为填充第二半导体芯片30和基板80的顶表面80a之间的空间。第三包封构件90可由环氧成型化合物形成。尽管未示出，但是在其它实施方式中，第三包封构件90可被形成为不覆盖第一半导体芯片10的第一表面10b和第一包封构件20的第一后表面20b。
外部联接构件92可形成在布置在基板80的底表面80b上的电极端子84的上方或下面。外部联接构件92可包括焊料球。与此不同，外部联接构件92可包括导电引脚或导电膏。根据该实施方式的堆叠半导体封装100可通过外部联接构件92的介质安装于诸如系统板的外部电路。
如以上提到的根据该实施方式的堆叠半导体封装100可通过以下处理来制造。
参照图2A，制备载体晶圆200。载体晶圆200可以是未处理的硅裸晶圆。具有第一有源表面10a的第一半导体芯片10附接于载体晶圆200。半导体芯片中的每个在第一有源表面10a上形成有第一键合焊盘12。第一半导体芯片10可以附接于载体晶圆200的上面或上方，使得第一有源表面10a面对载体晶圆200。另外，第一半导体芯片10以在考虑到后续将以倒装芯片方式键合的第二半导体芯片的情况下确定的间隔附接。
第一半导体芯片10中的每个具有：第一有源表面10a，其形成有多个第一键合焊盘12；第一表面10b，其背离第一有源表面10a；以及第一侧表面10c，其联接第一有源表面10a和第一表面10b。第一键合焊盘12包括周边键合焊盘12a和中心键合焊盘12b，周边键合焊盘12a设置在第一有源表面10a的两侧周边，中心键合焊盘12b设置在第一有源表面10a的周边键合焊盘12a之间。
参照图2B，通过模制工艺在载体晶圆200上以覆盖第一半导体芯片10这样的方式形成第一包封构件20。第一包封构件20可以是环氧成型化合物，并且被形成为覆盖每个第一半导体芯片10的第一侧表面10c和第一表面10b。第一包封构件20具有与每个第一半导体芯片10的第一有源表面10a共面的第一前表面20a。另外，第一包封构件20可被形成在载体晶圆200上方并且可与载体晶圆200接触。第一包封构件20具有背离第一前表面20a的第一后表面20b。
这里，多个第一半导体芯片10通过第一包封构件20重新设置的所得产品被称为重新配置晶圆250。
参照图2C，从包括第一半导体芯片10和第一包封构件20的重新配置晶圆250移除载体晶圆200。然后，将从中移除了载体晶圆200的重新配置晶圆250颠倒设置，使得第一半导体芯片10的第一有源表面10a向上设置。
参照图2D，制备第二半导体芯片30。第二半导体芯片中的每个具有：第二有源表面30a，其上面或上方布置有多个第二键合焊盘32；第二表面30b，其背离第二有源表面30a；以及第二侧表面30c，其联接第二有源表面30a和第二表面30b。第二键合焊盘32可布置在与第一半导体芯片10相邻的第二有源表面30a的一个侧周边处。第一联接构件40形成在第二半导体芯片30的第二键合焊盘32上。第一联接构件40可由凸块构成。在实施方式中，为了确保容易操纵，第二半导体芯片30的厚度大于目标厚度t，也就是说，最终堆叠半导体封装中的第二半导体芯片30的厚度。
第二半导体芯片30是根据晶圆级封装技术通过第一联接构件40以倒装芯片方式与重新配置晶圆250键合，使得第一半导体芯片10的第一有源表面10a和第二半导体芯片30的第二有源表面30a彼此面对。更清楚地，两个第二半导体芯片30通过第一联接构件40以倒装芯片方式与一个第一半导体芯片10键合，使得这两个第二半导体芯片30相对于这个第一有源表面10a与第一有源表面10a的周边键合焊盘12a交叠。因此，第一半导体芯片10的周边键合焊盘12a和第二半导体芯片30的第二键合焊盘32通过第一联接构件40彼此电联接，并且第一半导体芯片10的中心键合焊盘12b通过两个第二半导体芯片30之间的区域暴露。
参照图2E，在重新配置晶圆250的上面或上方形成第二包封构件50，以覆盖第二半导体芯片30。第二包封构件50可以是环氧成型化合物。第二包封构件50被形成为填充第一半导体芯片10和第二半导体芯片30之间的空间以及第一包封构件20和第二半导体芯片30之间的空间，并且被形成为填充第二半导体芯片30之间的区域。第二包封构件50具有与第一包封构件20接触的第二前表面50a和背离第二前表面50a的第二后表面50b。
参照图2F，第二包封构件50和第二半导体芯片30被部分去除，直到第二半导体芯片30的目标厚度t。可通过例如研磨处理来执行第二包封构件50和第二半导体芯片30的部分移除。在图2F中，最终的第二包封构件50的第二后表面50b和最终的第二半导体芯片30的第二表面30b分别是去除了一定厚度的暴露表面。尽管未示出，但是在部分去除了第二包封构件50和第二半导体芯片30之后，可执行第一包封构件20的第一后表面20b的部分去除，使得第一半导体芯片10的第一表面10a暴露。
参照图2G，第二包封构件50的在第二半导体芯片30之间的部分被蚀刻，使得形成分别暴露第一半导体芯片10的中心键合焊盘12b的孔h。当诸如金属层的导电层被填充在孔h中时，在孔h中分别形成模制通孔60。模制通孔60被形成为在第二半导体芯片30之间的区域中穿过第二包封构件50的第二前表面50a和第二后表面50b，并且分别与第一半导体芯片10的中心焊盘12b电联接。
参考图2H，凸块焊盘62形成在设置在第二包封构件50的第二后表面50b处的模制通孔60的上面或上方，并且同时，在第二半导体芯片30的第二后表面30b的上面或上方形成虚设焊盘64。凸块焊盘62和虚设焊盘64可由金属形成。第二联接构件70形成在凸块焊盘62的上面或上方，并且同时，支撑构件72形成在虚设焊盘64的上面或上方。第二联接构件70和支撑构件72可由例如凸块构成。
在该实施方式中，可形成虚设焊盘64和支撑部件72，以确保在后续通过第二联接构件70的介质进行倒装芯片键合芯片堆叠时结构稳定性。虚设焊盘64和支撑构件72可设置在第二半导体芯片30的不与模制通孔60相邻的第二表面30b的侧周边处。
参照图2I，将具有虚设焊盘64和支撑构件72的所得产品锯切，使得所得产品被分离成多个芯片堆叠。芯片堆叠分别包括第一半导体芯片10和第二半导体芯片30、第一包封构件20和第二包封构件50以及模制通孔60。
制备基板80。基板80具有顶表面80a和底表面80b，多个键合指状物82布置在顶表面80a上，底表面80b背离顶表面80a并且在其上布置有多个电极端子84。芯片堆叠以倒装芯片方式与基板80的顶表面80a键合，使得基板80的顶表面80a和第二半导体芯片30的第二表面30b彼此面对。这里，芯片堆叠被键合，使得第二联接构件70与基板80的键合指状物82联接。因此，第一半导体芯片10的第一键合焊盘12通过模制通孔60、凸块焊盘62和第二联接构件70的介质与基板80的键合指状物82电联接。当以倒装芯片方式将芯片堆叠键合时，包括虚设焊盘64的支撑构件72与基板80的顶表面80a的两侧周边接触，因此确保芯片堆叠的结构稳定性。
通过在基底80的上面或上方进行模制处理来形成第三包封构件90，使得芯片堆叠被完全覆盖。第三包封构件90可被形成为覆盖第一包封构件20和第二包封构件50的侧表面，并且填充第二半导体芯片30和基板80之间的空间。第三包封构件90可由环氧成型化合物形成。
参照图2J，第三包封构件90和第一包封构件20的第一后表面20b被部分地去除，使得第一半导体芯片10的第一表面10b暴露。可通过例如研磨处理来执行第三包封构件90和第一包封构件20的部分移除。这里，最终的第一包封构件20的第一后表面20b是去除了一定厚度的暴露表面。外部联接构件92分别形成在电极端子84上，电极端子84布置在基板80的底表面80b的上面或下面。外部联接构件92可以是焊料球。对其中形成外部联接构件92的所得产品执行切割成型处理，使得以晶圆级制造的封装被分离成个体封装。结果，完成了根据该实施方式的堆叠半导体封装100的制造。
根据如以上提到的实施方式的堆叠半导体封装100的优点在于能够降低制造成本并且简化制造处理。
详细地，在传统技术中，需要用硅插入器来实现平面型堆叠封装，并且需要用TSV(穿硅通孔)来实现垂直型堆叠封装。如果应用硅插入器，则制造成本的增加不免是由于硅插入件的存在而引起的，并且造成了在信号走线方面的负担。类似地，即使在应用TSV的情况下，由于复杂处理，导致也造成了负担，不免也使制造成本增加。
然而，在根据本实施方式的堆叠半导体封装100的情况下，可在不需要应用硅插入件的情况下以平面类型堆叠第二半导体芯片，并且可在不需要应用TSV的情况下以垂直类型堆叠第一半导体芯片和第二半导体芯片。结果，在根据该实施方式的堆叠半导体封装100中，可避免归因于应用硅插入件和TSV的制造成本增加，并且可避免由于信号布线和复杂TSV的形成而导致的处理负担。
因此，与应该应用硅插入器、信号布线和TSV的传统技术相比，根据该实施方式的堆叠半导体封装100会克服商业和技术限制。
参照图3，根据实施方式的堆叠半导体封装300可包括第一半导体芯片10、第一包封构件20、第二半导体芯片30、第一联接构件40、第二包封构件50、模制通孔60、第二联接构件70、基板80和底部填充物95。堆叠半导体封装300还可包括外部联接构件92。
第一半导体芯片10可以是存储器芯片或逻辑芯片。例如，第一半导体芯片10可以是逻辑芯片。第一半导体芯片10可具有第一有源表面10a和背离第一有源表面10a的第一表面10b。第一半导体芯片10可包括在第一有源表面10a上布置的多个第一键合焊盘12。当沿第一方向X观察时，第一键合焊盘12可包括周边键合焊盘12a和中心键合焊盘12b，周边键合焊盘12a设置在第一有源表面10a的两侧周边，中心键合焊盘12b设置在第一有源表面10a的周边键合焊盘12a之间。第一半导体芯片10可以以面向下的类型设置，使得第一键合焊盘12布置在其上的第一有源表面10a面向下。
第一包封构件20可被形成为覆盖第一半导体芯片10的第一侧表面10c。第一包封构件20可被形成为不覆盖第一半导体芯片10的第一有源表面10a和第一表面10b。第一包封构件20可由环氧成型化合物形成。
两个第二半导体芯片30可沿第二方向Y设置在第一半导体芯片10和第二包封构件20下面。第二半导体芯片30中的每个可具有第二有源表面30a和背离第二有源表面30a的第二表面30b。第二半导体芯片30可被设置成使得第二半导体芯片30的第二有源表面30a面对第一半导体芯片10的第一有源表面10a。第二半导体芯片30中的每个可包括在第二有源表面30a上布置的多个第二键合焊盘32。当沿第一方向X观察时，第二半导体芯片30中的每个的第二键合焊盘32可设置在与第一半导体芯片10相邻的第二有源表面30a的一个侧周边处。
两个第二半导体芯片30可被设置成彼此分离，使得第二键合焊盘32布置在其处的第二有源表面30a的侧周边与第一半导体芯片10的周边键合焊盘12a交叠的布置，从而使第一半导体芯片10的中心键合焊盘12b暴露。第二半导体芯片30的第二键合焊盘32可被设置成一一对应地与第一半导体芯片10的周边键合焊盘12a交叠。
第二半导体芯片30可以是与第一半导体芯片10不同的一种芯片。例如，如果第一半导体芯片10是逻辑芯片，则第二半导体芯片30可以是存储器芯片。
第一联接构件40可插入第一半导体芯片10的周边键合焊盘12a和第二半导体芯片30的第二键合焊盘32之间。第一联接构件40可由凸块构成。第一联接构件40可形成在第二半导体芯片30的第二键合焊盘32上。第二半导体芯片30可通过第一联接构件40以倒装芯片方式与第一半导体芯片10的第一有源表面10a键合。
第二包封构件50可被形成为覆盖第二半导体芯片30的第二有源表面30a和第二侧表面30c。第二包封构件50可被形成为不覆盖第二半导体芯片30的第二表面30b。第二包封构件50可被形成为填充第二半导体芯片30之间的区域。第二包封构件50可由环氧成型化合物形成。
可通过第二半导体芯片30之间的第二包封构件50的一部分形成模制通孔60。模制通孔60可被形成为穿过第二包封构件50的第二前表面50a和第二后表面50b。模制通孔60可分别与第二包封构件50的第二前表面50a上的第一半导体芯片10的中心键合焊盘12b联接。
凸块焊盘62可形成在设置在第二包封构件50的第二后表面50b处的模制通孔60的一些部分的上面或下面。虚设焊盘64可形成在当沿第一方向X观察时不与模制通孔60相邻的第二半导体芯片30的第二表面30b的侧面周边的下面和在该周边处。凸块焊盘62和虚设焊盘64可被形成为金属图案。
第二联接构件70可形成在凸块焊盘62的上面或下面。支撑构件72可形成在虚设焊盘64的上面或下面。第二联接构件70和支撑构件72可由凸块构成。通过第二联接构件70，包括第一半导体芯片10、第一包封构件20、第二半导体芯片30和第二包封构件50的芯片堆叠可以倒装芯片方式与基板80的顶表面80a键合。虚设焊盘64和支撑构件72的堆叠可被形成为在对芯片堆叠进行倒装芯片键合时确保结构稳定性。虚设焊盘64和支撑构件72的堆叠可设置在当沿第一方向X观察时没有与模制通孔60相邻的第二半导体芯片30的第二表面30b的侧周边处。
基板80可设置在第二半导体芯片30和第二包封构件50的下面。也就是说，基板80可被设置成面对第二半导体芯片30的第二表面30b和第二包封构件50的第二后表面50b。基板80可以是印刷电路板，并且具有四边形板的形状。基板80可具有顶表面80a和背离顶表面80a的底表面80b。基板80可包括布置在顶表面80a上的多个键合指状物82和布置在底表面80b的上面或下面的多个电极端子84。
键合指状物82可设置在基板80的顶表面80a的中心部分处。键合指状物82可按与对应于其的模制通孔60交叠这样的方式进行设置。因此，键合指状物82可通过第二联接构件70与包括凸块焊盘62的模制通孔60电联接。结果，键合指状物82可通过第二联接构件70、凸块焊盘62和模制通孔60与第一半导体芯片10的中心键合焊盘12b电联接。
电极端子84可布置在基板80的底表面80b的上面或下面。电极端子84可以通过形成在基板80中的内部布线(未示出)与布置在基板80的顶表面80a上的键合指状物82电联接。
底部填充物95可被形成为填充芯片堆叠和基板80之间的空间。更清楚地，底部填充物95可被形成为填充上面设置有凸块焊盘62和第二联接构件70的堆叠和虚设焊盘64和支撑构件72的堆叠所处的第二半导体芯片30的第二表面30b和第二包封构件50的第二后表面50b和基板80的顶表面80a之间的空间。底部填充物95可包括环氧组分。
外部联接构件92可形成在布置在基板80的底表面80b上的电极端子84的上方或下面。外部联接构件92可包括焊料球。与此不同，外部联接构件92可包括导电引脚或导电膏。
参照图4，根据实施方式的堆叠半导体封装400可包括第一半导体芯片10、第一包封构件20、第二半导体芯片30、第一联接构件40、第二包封构件50、模制通孔60和重新分配层110。堆叠半导体封装400还可包括外部联接构件120。
第一半导体芯片10可以是存储器芯片或逻辑芯片。例如，第一半导体芯片10可以是逻辑芯片。第一半导体芯片10可具有第一有源表面10a和背离第一有源表面10a的第一表面10b。第一半导体芯片10可包括在第一有源表面10a上布置的多个第一键合焊盘12。当沿第一方向X观察时，第一键合焊盘12可包括周边键合焊盘12a和中心键合焊盘12b，周边键合焊盘12a设置在第一有源表面10a的两侧周边，中心键合焊盘12b设置在周边键合焊盘12a之间。第一半导体芯片10可以以面向下的类型设置，使得第一键合焊盘12布置在其上的第一有源表面10a面向下。
第一包封构件20可被形成为覆盖第一半导体芯片10的第一侧表面10c。第一包封构件20可被形成为不覆盖第一半导体芯片10的第一有源表面10a和第一表面10b。第一包封构件20可由环氧成型化合物形成。
第二半导体芯片30可沿第二方向Y设置在第一半导体芯片10和第一包封构件20的下面。可设置两个第二半导体芯片。第二半导体芯片30中的每个可具有第一有源表面30a和背离第二有源表面30a的第二表面30b。第二半导体芯片30中的每个可包括在第二有源表面30a上布置的多个第二键合焊盘32。当沿第一方向X观察时，第二半导体芯片30中的每个的第二键合焊盘32可设置在与第一半导体芯片10相邻的第二有源表面30a的一个侧周边处。
第二半导体芯片30可被设置成使得第二半导体芯片30的第二有源表面30a面对第一半导体芯片10的第一有源表面10a。两个第二半导体芯片30可被设置成彼此分离，使得第二键合焊盘32布置在其处的第二有源表面30a的侧周边与第一半导体芯片10的周边键合焊盘12a交叠的布置，从而使第一半导体芯片10的中心键合焊盘12b暴露。两个第二半导体芯片30可被设置成不与第一半导体芯片10的中心键合焊盘12b交叠。第一半导体芯片10的周边键合焊盘12a和第二半导体芯片30的第二键合焊盘32可被设置成一一对应地彼此交叠。
第二半导体芯片30可以是与第一半导体芯片10不同的一种芯片。例如，如果第一半导体芯片10是逻辑芯片，则第二半导体芯片30可以是存储器芯片。
第一联接构件40可分别插入第一半导体芯片10的周边键合焊盘12a和第二半导体芯片30的第二键合焊盘32之间，以便将周边键合焊盘12a和第二键合焊盘32电联接。第一联接构件40可由凸块构成。第一联接构件40可形成在第二半导体芯片30的第二键合焊盘32上。第二半导体芯片30可通过第一联接构件40以倒装芯片方式与第一半导体芯片10的第一有源表面10a键合。
第二包封构件50可被形成为覆盖第二半导体芯片30的第二有源表面30a和第二侧表面30c。第二包封构件50可被形成为不覆盖第二半导体芯片30的第二表面30b。第二包封构件50可被形成为填充第二半导体芯片30之间的区域。第二包封构件50可由环氧成型化合物形成。
模制通孔60可被形成为通过第二半导体芯片30之间的第二包封构件50的一些部分，以穿过第二包封构件50的第二前表面50a和第二后表面50b。模制通孔60可分别与第二包封构件50的第二前表面50a上的第一半导体芯片10的中心键合焊盘12b联接。
重新分配层110可用作将包括第一半导体芯片10和第二半导体芯片30的芯片堆叠安装于外部电路的装置。重新分配层110可包括第一介电层112、重新分配线114和第二介电层116。重新分配层110还可包括重新分配焊盘118。重新分配层110可形成在第二半导体芯片30的第二表面30b、第二包封构件50的第二后表面50b和模制通孔60的下面。
第一介电层112可形成在第二半导体芯片30的第二表面30b、第二包封构件50的第二后表面50b和模制通孔60的上面或下面。第一介电层112可形成在第二半导体芯片30的第二表面30b和第二后表面50b的下面。第一介电层112可被形成为使设置在第二包封构件50的第二后表面50b上的模制通孔60的一些部分暴露。第一介电层112可用作应力缓冲器。重新分配线114可形成在第一介电层112的上面或下面。重新分配线114可被形成为，使得相应的重新分配线114的一端与通过第一介电层112暴露的模制通孔60联接。重新分配线114可由例如铜布线构成。第二介电层116可形成在第一介电层112的上面或下面，覆盖重新分配线114。第二介电层116可被形成为使背离所述一端的重新分配线114的另一端暴露。重新分配焊盘118可形成在第二介电层116的上面或下面。重新分配焊盘118可被形成为，使得分别与通过第二介电层116暴露的重新分配线114的另一端联接。
外部联接构件120可分别形成在重新分配焊盘118的上面或下面。外部联接构件120可由焊料球构成。与此不同，外部联接构件120可由导电引脚或导电膏构成。
根据该实施方式的堆叠半导体封装可具有与图1中所示的实施方式的优点相同的优点。另外，因为根据该实施方式的堆叠半导体封装包括重新分布层而不是基板，所以与图1中所示的实施方式的整个厚度相比，整个厚度可减小，并且可通过去除基板来降低制造成本。
根据上述各种实施方式的半导体封装可应用于各种类型的电子系统和存储卡。
参照图5，电子系统500可包括根据上述各种实施方式的堆叠半导体封装。电子系统500可包括控制器51、输入和输出(输入/输出)单元520和存储装置530。控制器510、输入/输出单元520和存储装置530可通过提供数据移动路径的总线550相互联接。
例如，控制器510可包括至少微处理器、数字信号处理器、微控制器和能够执行与这些部件类似的功能的逻辑器件中的任一个。控制器510和存储装置530可包括根据上述各种实施方式的堆叠半导体封装。输入/输出单元520可包括从键区、键盘、显示装置等之中选择的任一个。
存储装置530可存储将由控制器510执行的数据和/或命令。存储装置530可包括诸如DRAM的易失性存储装置和/或诸如闪存存储器的非易失性存储装置。例如，可将闪存存储器安装于诸如移动终端和台式计算机的信息处理系统。此闪存存储器可由SSD(固态驱动器)构成。在这种情况下，电子系统500可将大量数据稳定存储在闪存存储器系统中。
此电子系统500还可包括用于将数据发送到通信网络或从通信网络接收数据的接口540。接口540可以是有线或无线类型。例如，接口540可包括天线或有线/无线收发器。
尽管未示出，但是电子系统500还可包括应用芯片组、相机图像处理器(CIP)等。
电子系统500可被实现为移动系统、个人计算机、用于工业用途的计算机或执行各种功能的逻辑系统。例如，移动系统可以是个人数字助理(PDA)、便携式计算机、网络平板、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐系统和信息发送/接收系统之中的任一个。
在电子系统500是能够执行无线通信的设备的情况下，电子系统500可用于诸如CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美洲数字蜂窝)、E-TDMA(增强时分多址)、WCDMA(宽带码分多址)、CDMA2000、LTE(长期演进)和Wibro(无线宽带互联网)的通信。
参照图6，存储卡可包括根据上述各种实施方式的堆叠半导体封装。例如，存储卡600可包括诸如非易失性存储装置的存储器610和存储器控制器620。存储器610和存储器控制器620可存储数据或读取所存储的数据。存储器610可包括至少应用根据上述各种实施方式的堆叠半导体封装的非易失性存储器件之中的任一个。响应于来自主机630的读和写(读/写)请求，存储器控制器620可控制存储器610来读取所存储的数据或存储数据。
虽然已经出于例示性目的描述了各种实施方式，但本领域的技术人员应该清楚，在不脱离随附权利要求书限定的本公开的精神和范围的情况下，可进行各种改变和修改。
相关申请的交叉引用
本申请要求2017年5月11日提交的韩国专利申请第10-2017-0058458号的优先权，该专利申请的全部内容以引用方式并入本文中。

Claims (19)

1.一种堆叠半导体封装，该堆叠半导体封装包括：
第一半导体芯片，该第一半导体芯片具有第一有源表面，在所述第一有源表面的上方布置有包括周边键合焊盘和中心键合焊盘的第一键合焊盘；
第一包封构件，该第一包封构件形成在所述第一半导体芯片的至少第一侧表面的上方；
两个第二半导体芯片，所述两个第二半导体芯片具有第二有源表面，在所述第二有源表面上方与所述第一半导体芯片相邻的侧周边处布置有第二键合焊盘，并且所述两个第二半导体芯片被设置成彼此分离，使得所述第二有源表面面对所述第一有源表面，并且所述第二键合焊盘与所述周边键合焊盘交叠；
第一联接构件，该第一联接构件插置在所述第一半导体芯片的所述周边键合焊盘和所述第二半导体芯片的所述第二键合焊盘之间；
第二包封构件，该第二包封构件形成在所述第二半导体芯片的第二侧表面上方，该第二包封构件包括所述第二半导体芯片之间的区域；以及
模制通孔，该模制通孔通过所述第二包封构件的在所述第二半导体芯片之间的所述区域中的一部分形成并且与所述中心键合焊盘联接，
其中，所述第一包封构件具有与所述第一半导体芯片的所述第一有源表面共面的第一前表面和与所述第一半导体芯片的背离所述第一有源表面的第一表面共面的第一后表面，并且
其中，所述第二包封构件具有与所述第一包封构件接触的第二前表面和与所述第二半导体芯片的背离所述第二有源表面的第二表面共面的第二后表面。
2.根据权利要求1所述的堆叠半导体封装，其中，所述第一半导体芯片包括逻辑芯片，并且所述第二半导体芯片包括存储器芯片。
3.根据权利要求1所述的堆叠半导体封装，其中，所述第二包封构件被形成为与所述第一半导体芯片和所述第一包封构件接触。
4.根据权利要求1所述的堆叠半导体封装，所述堆叠半导体封装还包括：
凸块焊盘，该凸块焊盘形成在模制通孔的设置于所述第二包封构件的所述第二后表面处的部分的下方；
虚设焊盘，该虚设焊盘形成在所述第二半导体芯片的所述第二表面的下方；
第二联接构件，该第二联接构件形成在所述凸块焊盘的下方；以及
支撑构件，该支撑构件形成在所述虚设焊盘的下方。
5.根据权利要求4所述的堆叠半导体封装，所述堆叠半导体封装还包括：
基板，该基板被设置成面对所述第二半导体芯片的所述第二表面和所述第二包封构件的所述第二后表面，并且具有顶表面和底表面，在所述顶表面的上方布置有与所述第二联接构件电联接的键合指状物，在所述底表面的下方布置有与所述键合指状物电联接的电极端子。
6.根据权利要求5所述的堆叠半导体封装，所述堆叠半导体封装还包括：
第三包封构件，该第三包封构件形成在所述基板的所述顶表面的上方，以覆盖所述第一包封构件和所述第二包封构件的侧表面并且填充所述第二半导体芯片和所述基板的所述顶表面之间的空间以及所述第二包封构件和所述基板的所述顶表面之间的空间；以及
外部联接构件，该外部联接构件形成在所述电极端子的下方。
7.根据权利要求5所述的堆叠半导体封装，所述堆叠半导体封装还包括：
底部填充物，该底部填充物被形成为填充所述第二半导体芯片的所述第二表面和所述基板的所述顶表面之间的空间、所述第二包封构件的所述第二后表面和所述基板的所述顶表面之间的空间；以及
外部联接构件，该外部联接构件形成在所述电极端子的下方。
8.根据权利要求1所述的堆叠半导体封装，所述堆叠半导体封装还包括：
重新分配层，该重新分配层形成在所述第二半导体芯片的所述第二表面、所述第二包封构件的所述第二后表面和所述模制通孔的下方。
9.根据权利要求8所述的堆叠半导体封装，其中，所述重新分配层包括：
第一介电层，该第一介电层以使所述模制通孔暴露的方式形成在所述第二半导体芯片的所述第二表面、所述第二包封构件的所述第二后表面和所述模制通孔的下方；
重新分配线，该重新分配线形成在所述第一介电层的下方，使得所述重新分配线的一端与被暴露的所述模制通孔联接；
第二介电层，该第二介电层以这样的方式形成在所述第一介电层的下方，即，覆盖所述重新分配线的除了背离所述重新分配线的所述一端的另一端之外的部分；以及
重新分配焊盘，该重新分配焊盘以与被暴露的所述重新分配线的另一端联接的方式形成在所述第二介电层的下方。
10.根据权利要求9所述的堆叠半导体封装，所述堆叠半导体封装还包括：
外部联接构件，该外部联接构件形成在所述重新分配焊盘的下方。
11.一种用于制造堆叠半导体封装的方法，该方法包括以下步骤：
在载体晶圆的上方设置第一半导体芯片，所述第一半导体芯片具有第一有源表面，所述第一有源表面上方布置有包括周边键合焊盘和中心键合焊盘的第一键合焊盘，使得所述载体晶圆和所述第一有源表面彼此面对；
在所述载体晶圆上方形成覆盖所述第一半导体芯片的第一包封构件，使得构造成其中重新设置有所述第一半导体芯片的重新配置晶圆，其中，所述第一包封构件具有与所述第一半导体芯片的所述第一有源表面共面的第一前表面和与所述第一半导体芯片的背离所述第一有源表面的第一表面共面的第一后表面；
从所述重新配置晶圆中去除所述载体晶圆；
将两个第二半导体芯片彼此以一定距离键合于所述重新配置晶圆上的一个第一半导体芯片，其中，所述第二半导体芯片具有第二有源表面，第二键合焊盘在所述第二有源表面上方布置在与所述第一半导体芯片相邻的侧周边处，其中，所述第二半导体芯片具有形成在所述第二键合焊盘上的第一联接构件，其中，所述第二半导体芯片具有大于目标厚度的厚度，并且其中，所述第二半导体芯片设置在所述重新配置晶圆上，使得所述第二有源表面面对所述第一有源表面，所述第二键合焊盘通过所述第一联接构件与所述周边键合焊盘联接并且所述中心键合焊盘被暴露；
在所述重新配置晶圆的上方以覆盖所述第二半导体芯片的方式形成第二包封构件，其中，所述第二包封构件具有与所述第一包封构件接触的第二前表面和与所述第二半导体芯片的背离所述第二有源表面的第二表面共面的第二后表面；
去除所述第二包封构件和所述第二半导体芯片的部分厚度，使得保持所述第二半导体芯片的目标厚度；以及
形成模制通孔，所述模制通孔与所述第一半导体芯片的所述中心键合焊盘联接，并且穿过所述第二包封构件的在所述第二半导体芯片之间的区域中的一部分。
12.根据权利要求11所述的方法，该方法在形成所述模制通孔之后还包括以下步骤：
形成设置在所述模制通孔上方的凸块焊盘和设置在所述第二半导体芯片的第二表面上方的虚设焊盘；以及
在所述凸块焊盘的上方形成第二联接构件，并且在所述虚设焊盘的上方形成支撑构件。
13.根据权利要求12所述的方法，该方法在形成所述第二联接构件和所述支撑构件之后还包括以下步骤：
锯切具有所述第二联接构件和所述支撑构件的所得产品，使得所述所得产品被分离成包括所述第一半导体芯片和所述第二半导体芯片、所述第一包封构件和所述第二包封构件和所述模制通孔的多个芯片堆叠。
14.根据权利要求13所述的方法，该方法在锯切所述所得产品之后还包括以下步骤：
将所述芯片堆叠键合于具有顶表面和底表面的基板的顶表面，使得所述第二联接构件和键合指状物彼此联接，在所述顶表面上方布置有所述键合指状物，在所述底表面下方布置有电极端子；
在所述基板的上方以覆盖所述第一包封构件和所述第二包封构件的侧表面的方式形成第三包封构件；
部分地去除所述第一包封构件的第一后表面和所述第三包封构件，使得所述第一半导体芯片的第一表面被暴露；以及
在所述电极端子上方形成外部联接构件。
15.根据权利要求14所述的方法，该方法在形成所述外部联接构件之后还包括以下步骤：
将所得产物分割成型，使得所述所得产物被分离成个体封装。
16.根据权利要求13所述的方法，该方法在锯切所述所得产品之后还包括以下步骤：
将所述芯片堆叠键合于具有顶表面和底表面的基板的顶表面，使得所述第二联接构件和键合指状物彼此联接，在所述顶表面上方布置有所述键合指状物，在所述底表面下方布置有电极端子；
形成底部填充物，以填充所述第二半导体芯片和所述基板的所述顶表面之间的空间以及所述第二包封构件和所述基板的所述顶表面之间的空间；以及
在所述电极端子上方形成外部联接构件。
17.根据权利要求16所述的方法，该方法在形成所述外部联接构件之后还包括以下步骤：
将所得产物分割成型，使得所述所得产物被分离成个体封装。
18.根据权利要求13所述的方法，该方法还包括在形成所述模制通孔之后的以下步骤：
在所述第二半导体芯片的背离所述第二有源表面的第二表面和所述第二包封构件的下方以暴露所述模制通孔的方式形成第一介电层；
在所述第一介电层的下方形成重新分配线，所述重新分配线的一端与暴露的所述模制通孔联接；
在所述重新分配线和所述第一介电层的下方以暴露所述重新分配线的背离所述一端的另一端的方式形成第二介电层；以及
在所述第二介电层的下方形成重新分配焊盘，所述重新分配焊盘与所述重新分配线的暴露的所述另一端联接。
19.根据权利要求18所述的方法，该方法在形成所述重新分配焊盘之后还包括以下步骤：
在所述重新分配焊盘的下方形成外部联接构件；以及
将所得产物分割成型，使得所述所得产物被分离成个体封装。
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US9911629B2 (en) * 2016-02-10 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated passive device package and methods of forming same
US10304697B2 (en) * 2017-10-05 2019-05-28 Amkor Technology, Inc. Electronic device with top side pin array and manufacturing method thereof
KR102438456B1 (ko) * 2018-02-20 2022-08-31 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
CN110875268A (zh) * 2018-09-04 2020-03-10 中芯集成电路（宁波）有限公司 晶圆级封装方法及封装结构
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7361533B1 (en) * 2002-11-08 2008-04-22 Amkor Technology, Inc. Stacked embedded leadframe
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US8115301B2 (en) * 2006-11-17 2012-02-14 Stats Chippac, Inc. Methods for manufacturing thermally enhanced flip-chip ball grid arrays
US8513784B2 (en) * 2010-03-18 2013-08-20 Alpha & Omega Semiconductor Incorporated Multi-layer lead frame package and method of fabrication
US20130277855A1 (en) * 2012-04-24 2013-10-24 Terry (Teckgyu) Kang High density 3d package
TWI496270B (zh) * 2013-03-12 2015-08-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9111870B2 (en) * 2013-10-17 2015-08-18 Freescale Semiconductor Inc. Microelectronic packages containing stacked microelectronic devices and methods for the fabrication thereof
US9396300B2 (en) * 2014-01-16 2016-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof
US9443824B1 (en) * 2015-03-30 2016-09-13 Qualcomm Incorporated Cavity bridge connection for die split architecture
US9613942B2 (en) 2015-06-08 2017-04-04 Qualcomm Incorporated Interposer for a package-on-package structure

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