CN102651323B - 半导体封装结构的制法 - Google Patents

半导体封装结构的制法 Download PDF

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CN102651323B
CN102651323B CN201110062437.4A CN201110062437A CN102651323B CN 102651323 B CN102651323 B CN 102651323B CN 201110062437 A CN201110062437 A CN 201110062437A CN 102651323 B CN102651323 B CN 102651323B
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chip
primer layer
packaging
base plate
making
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CN102651323A (zh
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蔡宪聪
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UTAC Headquarters Pte Ltd
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UTAC Taiwan Corp
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Abstract

一种半导体封装结构的制法，包括：提供一具有主动面的芯片及一表面上设有底胶层的基材，其中，该芯片的主动面上具有多个导电凸块；将该芯片的主动面结合于该底胶层上，以令各该导电凸块嵌埋入该底胶层中；移除该基材，以外露该底胶层；以及将该芯片通过该底胶层结合于封装基板上，使该芯片通过该多个导电凸块电性连接该封装基板。本发明通过先在芯片的主动面上结合底胶层，再将该底胶层设于该封装基板上，因而无需进行焊接制程，有效减少材料成本，且可简化制程。

Description

半导体封装结构的制法
技术领域
本发明涉及一种半导体装置的制法，尤其涉及一种半导体封装结构的制法。
背景技术
随着电子产业的蓬勃发展，电子产品亦朝着轻、薄、短、小、高积集度、多功能化方向发展。而为满足封装结构高集成化(Integration)以及微型化(Miniaturization)的封装需求，封装基板除了导入球栅阵列(BGA)的设计，封装形式逐渐由打线式(Wire Bonding)封装进展到覆晶式(Flip Chip,FC)封装，此种封装件能避免打线用的金线占用空间，可有效缩减整体半导体装置的体积并提升电性功能。
图1A至图1C为习知覆晶式封装结构制法的说明图。如图1A所示，提供一表面具有焊垫120的封装基板12。如图2B所示，提供一具有相对的主动面10a及非主动面10b的芯片10，该主动面10a上具有多个导电凸块100。接着，进行焊接制程，将该导电凸块100通过该焊锡凸块11电性连接各该焊垫120，使该芯片10设于该封装基板12上。如图2C所示，形成底胶层(underfill)110于该芯片10的主动面10a与该封装基板12之间，以包覆各该焊锡凸块11，从而完成覆晶制程。
然而，习知覆晶式封装结构的制法中，需先进行焊接制程，再进行填充底胶的制程，不仅因需使用焊锡材料而增加材料成本，且导致制程繁琐。
因此，如何克服上述习知制法的问题，实已成为目前亟欲解决的课题。
发明内容
鉴于上述习知技术的种种缺失，本发明的主要目的在于提供一种半导体封装结构的制法，无需进行焊接制程，并可有效减少材料成本。
本发明的半导体封装结构的制法包括：提供一芯片及一表面上设有底胶层的基材，该芯片具有相对的主动面及非主动面，其中，主动面上具有多个导电凸块；将该芯片的主动面结合于该底胶层上，以令各该导电凸块嵌埋入该底胶层中；移除该基材，以外露该底胶层；以及将该芯片通过该底胶层结合于封装基板上，使该芯片通过该多个导电凸块电性连接该封装基板。
前述的制法中，是通过剥离的方式移除该基材，且为轻易剥除该基材，该基材与该底胶层之间的结合力以小于该芯片主动面与该底胶层之间的结合力为佳。
在另一实施例中，前述的制法中，该基材与该底胶层之间可具有离形层，以通过剥离该离形层而移除该基材。
前述的制法中，由于该底胶层保护该芯片的主动面，且该基材可提供稳定的承载及支撑性，故于移除该基材之前，还可研磨该芯片的非主动面。
此外，该芯片通过该底胶层结合于封装基板上的步骤中，通过热融该底胶层，使该多个导电凸块电性连接该封装基板，再固化该底胶层。当然，也可通过形成封装胶体于该封装基板上，以包覆该芯片。
由上可知，本发明的半导体封装结构的制法，通过先在芯片的主动面上结合底胶层，再使芯片通过该底胶层设于该封装基板上，相较于习知技术，本发明无需进行焊接制程，得以有效减少材料成本，且可简化制程。
附图说明
图1A至图1C为习知覆晶式基板结构的制法的剖视示意图；以及
图2A至图2E为本发明半导体封装结构的制法的剖视示意图，其中，图2B’及图2D’图为图2B及图第2D的另一实施方式。
主要元件符号说明
10、20      芯片
10a、20a    主动面
10b、20b    非主动面
100、200    导电凸块
11          焊锡凸块
110、210    底胶层
12、22      封装基板
120、220    焊垫
21          基材
211         离形层
230         封装胶体。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，熟悉本领域的普通技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须说明者为，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉本领域的技术人员进行了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍涵盖在本发明所揭示的技术内容的范围内。
请参阅图2A至图2E，其为本发明的半导体封装结构的制法。
如图2A所示，提供一具有相对的主动面20a及非主动面20b的芯片20，该主动面20a上具有多个导电凸块200。
如图2B所示，提供一表面上设有底胶层210的基材21，将该芯片20的主动面20a结合于该底胶层210上，以令各该导电凸块200嵌埋入该底胶层210中。于具体实施上，该底胶层210可为非导电胶膜(NCF，NAMICS CORPORATION)，且可于进行研磨制程时保护导电凸块200。于本实施例中，该基材21与该底胶层210之间的结合力小于该主动面20a与该底胶层210之间的结合力。
如图2B’所示，于另一实施方式中，该基材21与该底胶层210之间具有离形层211。
如图2C所示，还可研磨该芯片20的非主动面20b至L-L虚线以降低芯片厚度。
如图2D图所示，因该基材21与该底胶层210之间的结合力小于该芯片20的主动面20a与该底胶层210之间的结合力，故可通过剥离的方式移除该基材21，以使该底胶层210附着于该主动面20a上。
如图2D’所示，若以图2B’所示的结构进行移除制程，则可通过剥离该离形层211而移除该基材21。
如图2E所示，将该芯片20通过底胶层210设于一封装基板22上，再经热融该底胶层210，使该多个导电凸块200碰触该封装基板22，以电性连接该封装基板22的焊垫220，再固化该底胶层210，使该底胶层210黏固于该封装基板22上，令该芯片20固定于该封装基板22上。当然，也可通过形成封装胶体230于该封装基板22上，以包覆该芯片20。
本发明的半导体封装结构的制法，通过先在该芯片20的主动面20a上结合该底胶层210，再将该底胶层210设于该封装基板22上，相较于习知技术，本发明不仅无需进行焊接制程，且减少材料成本，以简化制程步骤。
上述实施例用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟习本领域的普通技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求范围所列。

Claims (7)

1.一种半导体封装结构的制法，其特征在于，包括：
提供一具有相对的主动面及非主动面的芯片及一表面上设有底胶层的基材，其中，该主动面上具有多个导电凸块，该底胶层为非导电胶膜；
将该芯片的主动面结合于该底胶层上，以令各该导电凸块嵌埋入该底胶层中，且各该导电凸块不碰触该基材；
移除该基材，以外露该底胶层；
将该芯片通过该底胶层结合于封装基板上，使该芯片通过该多个导电凸块电性连接该封装基板，使各该导电凸块碰触该封装基板，令各该导电凸块电性连接该封装基板的焊垫；以及
固化该底胶层，使该底胶层黏固于该封装基板上，令该芯片固定于该封装基板上，而该导电凸块与该焊垫无进行焊接制程。
2.根据权利要求1所述的半导体封装结构的制法，其特征在于，移除该基材的方式是通过剥离的方式。
3.根据权利要求2所述的半导体封装结构的制法，其特征在于，该基材与该底胶层之间的结合力小于该芯片主动面与该底胶层之间的结合力。
4.根据权利要求1所述的半导体封装结构的制法，其特征在于，该基材与该底胶层之间具有离形层，以通过剥离该离形层而移除该基材。
5.根据权利要求1所述的半导体封装结构的制法，其特征在于，还包括于移除该基材之前，研磨该芯片的非主动面。
6.根据权利要求1所述的半导体封装结构的制法，其特征在于，该芯片通过该底胶层结合于封装基板上的步骤中，是通过热融该底胶层，使该多个导电凸块电性连接该封装基板，再固化该底胶层。
7.根据权利要求1所述的半导体封装结构的制法，其特征在于，还包括形成封装胶体于该封装基板上，以包覆该芯片。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW455966B (en) * 2000-02-23 2001-09-21 Fujitsu Ltd Method for fixing a semiconductor device having stud bumps to a substrate by an electrically non-conductive adhesive
CN1387244A (zh) * 2001-03-30 2002-12-25 琳得科株式会社 带导电体的粘接板、半导体装置的制造方法及半导体装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4180206B2 (ja) * 1999-11-12 2008-11-12 リンテック株式会社 半導体装置の製造方法
JP2002118147A (ja) * 2000-10-11 2002-04-19 Mitsui Chemicals Inc 半導体チップをプリント配線基板に装着する方法及びその方法の実施に用いる装着用シート
JP3717899B2 (ja) * 2002-04-01 2005-11-16 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP4776188B2 (ja) * 2004-08-03 2011-09-21 古河電気工業株式会社 半導体装置製造方法およびウエハ加工用テープ
WO2006118033A1 (ja) * 2005-04-27 2006-11-09 Lintec Corporation シート状アンダーフィル材および半導体装置の製造方法
KR101131366B1 (ko) * 2006-06-23 2012-04-04 히다치 가세고교 가부시끼가이샤 반도체 디바이스의 제조 방법 및 접착 필름
JP2008251869A (ja) * 2007-03-30 2008-10-16 Kyocer Slc Technologies Corp 配線基板およびその製造方法
JP5064288B2 (ja) * 2008-04-15 2012-10-31 新光電気工業株式会社 半導体装置の製造方法
JP5569121B2 (ja) * 2009-05-29 2014-08-13 日立化成株式会社 接着剤組成物、回路部材接続用接着剤シート及び半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW455966B (en) * 2000-02-23 2001-09-21 Fujitsu Ltd Method for fixing a semiconductor device having stud bumps to a substrate by an electrically non-conductive adhesive
CN1387244A (zh) * 2001-03-30 2002-12-25 琳得科株式会社 带导电体的粘接板、半导体装置的制造方法及半导体装置

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