TWI430376B - The Method of Fabrication of Semiconductor Packaging Structure - Google Patents

The Method of Fabrication of Semiconductor Packaging Structure Download PDF

Info

Publication number
TWI430376B
TWI430376B TW100106344A TW100106344A TWI430376B TW I430376 B TWI430376 B TW I430376B TW 100106344 A TW100106344 A TW 100106344A TW 100106344 A TW100106344 A TW 100106344A TW I430376 B TWI430376 B TW I430376B
Authority
TW
Taiwan
Prior art keywords
substrate
wafer
primer layer
layer
fabricating
Prior art date
Application number
TW100106344A
Other languages
English (en)
Other versions
TW201236090A (en
Inventor
Shiann Tsong Tsai
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to TW100106344A priority Critical patent/TWI430376B/zh
Priority to CN201110062437.4A priority patent/CN102651323B/zh
Priority to US13/170,321 priority patent/US20120220081A1/en
Priority to KR1020110063772A priority patent/KR20120098376A/ko
Priority to EP11172138A priority patent/EP2498284A2/en
Priority to JP2012038739A priority patent/JP2012178565A/ja
Publication of TW201236090A publication Critical patent/TW201236090A/zh
Application granted granted Critical
Publication of TWI430376B publication Critical patent/TWI430376B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/27003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the layer preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Description

半導體封裝結構之製法
本發明係有關於一種半導體裝置之製法，尤指一種半導體封裝結構之製法。
隨著電子產業的蓬勃發展，電子產品亦朝著輕、薄、短、小、高積集度、多功能化方向發展。而為滿足封裝結構高積集度(Integration)以及微型化(Miniaturization)的封裝需求，封裝基板除了導入球柵陣列(BGA)的設計，封裝形式逐漸由打線式(Wire Bonding)封裝進展到覆晶式(Flip Chip,FC)封裝，此種封裝件能避免打線用之金線佔用空間，可有效縮減整體半導體裝置之體積並提昇電性功能。
第1A至1C圖係習知覆晶式封裝結構製法之說明圖。如第1A圖所示，提供一表面具有銲墊120之封裝基板12。如第2B圖所示，提供一具有相對之主動面10a及非主動面10b之晶片10，該主動面10a上具有複數導電凸塊100。接著，進行銲接製程，將該導電凸塊100藉由該銲錫凸塊11電性連接各該銲墊120，使該晶片10設於該封裝基板12上。如第2C圖所示，形成底膠層(underfill)110於該晶片10之主動面10a與該封裝基板12之間，以包覆各該銲錫凸塊11，俾完成覆晶製程。
然，習知覆晶式封裝結構之製法中，需先進行銲接製程，再進行填充底膠之製程，不僅因需使用銲錫材料而增加材料成本，且導致製程繁瑣。
因此，如何克服上述習知製法之問題，實已成為目前亟欲解決之課題。
鑑於上述習知技術之種種缺失，本發明提供一種半導體封裝結構之製法，係包括：提供一晶片及一表面上設有底膠層之基材，該晶片具有相對之主動面及非主動面，其中，主動面上具有複數導電凸塊；將該晶片之主動面結合於該底膠層上，以令各該導電凸塊嵌埋入該底膠層中；移除該基材，以外露該底膠層；以及將該晶片藉由該底膠層結合於封裝基板上，使該晶片藉由該些導電凸塊電性連接該封裝基板。
前述之製法中，係藉由剝離之方式移除該基材，且為輕易剝除該基材，該基材與該底膠層之間的結合力以小於該晶片主動面與該底膠層之間的結合力為佳。
或者，前述之製法中，該基材與該底膠層之間可具有離形層，以藉由剝離該離形層而移除該基材。
前述之製法中，由於底膠層保護該晶片之主動面，且該基材可提供穩定的承載及支撐性，故於移除該基材之前，復可研磨該晶片之非主動面。
此外，該晶片藉由該底膠層結合於封裝基板上之步驟中，係透過熱融該底膠層，使該些導電凸塊電性連接該封裝基板，再固化該底膠層。當然，亦可形成封裝膠體於該封裝基板上，以包覆該晶片。
由上可知，本發明之半導體封裝結構之製法，係藉由先於晶片之主動面上結合底膠層，再使晶片藉由該底膠層設於該封裝基板上，相較於習知技術，本發明因而無需進行銲接製程，得以有效減少材料成本，且可簡化製程。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須說明者為，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍涵蓋在本發明所揭示之技術內容之範圍內。
請參閱第2A至2E圖，係提供本發明之半導體封裝結構之製法。
如第2A圖所示，提供一具有相對之主動面20a及非主動面20b之晶片20，該主動面20a上具有複數導電凸塊200。
如第2B圖所示，提供一表面上設有底膠層210之基材21，將該晶片20之主動面20a結合於該底膠層210上，以令各該導電凸塊200嵌埋入該底膠層210中。於具體實施上，該底膠層210可為非導電膠膜(NCF，NAMICS CORPORATION)，且可於進行研磨製程時保護導電凸塊200。於本實施例中，該基材21與該底膠層210之間的結合力小於該主動面20a與該底膠層210之間的結合力。
如第2B’圖所示，於另一實施態樣中，該基材21與該底膠層210之間具有離形層211。
如第2C圖所示，復可研磨該晶片20之非主動面20b至L-L虛線以降低晶片厚度。
如第2D圖所示，因該基材21與該底膠層210之間的結合力小於該晶片20之主動面20a與該底膠層210之間的結合力，故可藉由剝離之方式移除該基材21，以使該底膠層210附著於該主動面20a上。
如第2D’圖所示，若以第2B’圖所示之結構進行移除製程，則可藉由剝離該離形層211而移除該基材21。
如第2E圖所示，將該晶片20藉由底膠層210設於一封裝基板22上，再經熱融該底膠層210，使該些導電凸塊200碰觸該封裝基板22，以電性連接該封裝基板22之銲墊220，再固化該底膠層210，使該底膠層210黏固於該封裝基板22上，令該晶片20固定於該封裝基板22上。當然，亦可形成封裝膠體230於該封裝基板22上，以包覆該晶片20。
本發明之半導體封裝結構之製法，係藉由先於該晶片20之主動面20a上結合該底膠層210，再將該底膠層210設於該封裝基板22上，相較於習知技術，本發明不僅無需進行銲接製程並於銲接後行程底膠層，且減少材料成本，以簡化製程步驟。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10、20．．．晶片
10a、20a．．．主動面
10b、20b．．．非主動面
100、200．．．導電凸塊
11．．．銲錫凸塊
110、210．．．底膠層
12、22．．．封裝基板
120、220．．．銲墊
21．．．基材
211．．．離形層
230．．．封裝膠體
第1A至1C圖係為習知覆晶式基板結構之製法之剖視示意圖；以及
第2A至2E圖係為本發明半導體封裝結構之製法之剖視示意圖；第2B’圖及第2D’圖係為第2B圖及第2D圖之另一實施態樣。
20．．．晶片
20a．．．主動面
20b．．．非主動面
200．．．導電凸塊
21．．．基材
210．．．底膠層

Claims (7)

  1. 一種半導體封裝結構之製法，係包括：提供一具有相對之主動面及非主動面之晶片及一表面上設有底膠層之基材，其中，該主動面上具有複數導電凸塊，該底膠層係為非導電膠膜，且該基材係為軟質材；將該晶片之主動面結合於該底膠層上，以令各該導電凸塊嵌埋入該底膠層中；移除該基材，以外露該底膠層；以及將該晶片藉由該底膠層結合於封裝基板上，使該晶片藉由該些導電凸塊電性連接該封裝基板。
  2. 如申請專利範圍第1項所述之半導體封裝結構之製法，其中，移除該基材之方式係藉由剝離之方式。
  3. 如申請專利範圍第2項所述之半導體封裝結構之製法，其中，該基材與該底膠層之間的結合力係小於該晶片主動面與該底膠層之間的結合力。
  4. 如申請專利範圍第1項所述之半導體封裝結構之製法，其中，該基材與該底膠層之間具有離形層，以藉由剝離該離形層而移除該基材。
  5. 如申請專利範圍第1項所述之半導體封裝結構之製法，復包括於移除該基材之前，研磨該晶片之非主動面。
  6. 如申請專利範圍第1項所述之半導體封裝結構之製法，該該晶片藉由該底膠層結合於封裝基板上之步驟中，係透過熱融該底膠層，使該些導電凸塊電性連接該 封裝基板，再固化該底膠層。
  7. 如申請專利範圍第1項所述之半導體封裝結構之製法，復包括形成封裝膠體於該封裝基板上，以包覆該晶片。
TW100106344A 2011-02-25 2011-02-25 The Method of Fabrication of Semiconductor Packaging Structure TWI430376B (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
TW100106344A TWI430376B (zh) 2011-02-25 2011-02-25 The Method of Fabrication of Semiconductor Packaging Structure
CN201110062437.4A CN102651323B (zh) 2011-02-25 2011-03-11 半导体封装结构的制法
US13/170,321 US20120220081A1 (en) 2011-02-25 2011-06-28 Method of fabricating a semiconductor package structure
KR1020110063772A KR20120098376A (ko) 2011-02-25 2011-06-29 반도체 패키지 구조를 가공하는 방법
EP11172138A EP2498284A2 (en) 2011-02-25 2011-06-30 Method of fabricating a semiconductor package
JP2012038739A JP2012178565A (ja) 2011-02-25 2012-02-24 半導体パッケージ構造の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW100106344A TWI430376B (zh) 2011-02-25 2011-02-25 The Method of Fabrication of Semiconductor Packaging Structure

Publications (2)

Publication Number Publication Date
TW201236090A TW201236090A (en) 2012-09-01
TWI430376B true TWI430376B (zh) 2014-03-11

Family

ID=44514475

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100106344A TWI430376B (zh) 2011-02-25 2011-02-25 The Method of Fabrication of Semiconductor Packaging Structure

Country Status (6)

Country Link
US (1) US20120220081A1 (zh)
EP (1) EP2498284A2 (zh)
JP (1) JP2012178565A (zh)
KR (1) KR20120098376A (zh)
CN (1) CN102651323B (zh)
TW (1) TWI430376B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10410988B2 (en) * 2016-08-09 2019-09-10 Semtech Corporation Single-shot encapsulation
CN107527554B (zh) * 2017-08-23 2020-12-11 京东方科技集团股份有限公司 柔性显示面板及其制备方法、柔性显示装置
CN108436604B (zh) * 2018-04-23 2020-12-08 苏试宜特(上海)检测技术有限公司 应用于低介电材质覆晶芯片的防脱层研磨方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4180206B2 (ja) * 1999-11-12 2008-11-12 リンテック株式会社 半導体装置の製造方法
JP3625268B2 (ja) * 2000-02-23 2005-03-02 富士通株式会社 半導体装置の実装方法
JP2002118147A (ja) * 2000-10-11 2002-04-19 Mitsui Chemicals Inc 半導体チップをプリント配線基板に装着する方法及びその方法の実施に用いる装着用シート
JP2002299378A (ja) * 2001-03-30 2002-10-11 Lintec Corp 導電体付接着シート、半導体装置製造方法および半導体装置
JP3717899B2 (ja) * 2002-04-01 2005-11-16 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP4776188B2 (ja) * 2004-08-03 2011-09-21 古河電気工業株式会社 半導体装置製造方法およびウエハ加工用テープ
WO2006118033A1 (ja) * 2005-04-27 2006-11-09 Lintec Corporation シート状アンダーフィル材および半導体装置の製造方法
KR101129762B1 (ko) * 2006-06-23 2012-03-26 히다치 가세고교 가부시끼가이샤 반도체 디바이스의 제조 방법
JP2008251869A (ja) * 2007-03-30 2008-10-16 Kyocer Slc Technologies Corp 配線基板およびその製造方法
JP5064288B2 (ja) * 2008-04-15 2012-10-31 新光電気工業株式会社 半導体装置の製造方法
JP5569121B2 (ja) * 2009-05-29 2014-08-13 日立化成株式会社 接着剤組成物、回路部材接続用接着剤シート及び半導体装置の製造方法

Also Published As

Publication number Publication date
EP2498284A2 (en) 2012-09-12
TW201236090A (en) 2012-09-01
US20120220081A1 (en) 2012-08-30
KR20120098376A (ko) 2012-09-05
CN102651323B (zh) 2015-09-02
CN102651323A (zh) 2012-08-29
JP2012178565A (ja) 2012-09-13

Similar Documents

Publication Publication Date Title
TWI420640B (zh) 半導體封裝裝置、半導體封裝結構及其製法
US8378480B2 (en) Dummy wafers in 3DIC package assemblies
TWI631676B (zh) 電子封裝件及其製法
US9953907B2 (en) PoP device
TWI643307B (zh) 電子封裝件及其製法
TWI496270B (zh) 半導體封裝件及其製法
TWI240399B (en) Chip package structure and process for fabricating the same
JP2012160707A (ja) 積層半導体チップ、半導体装置およびこれらの製造方法
TWI635585B (zh) 半導體封裝件及其製法
TW201812932A (zh) 電子封裝件及其製法
TWI421956B (zh) 晶片尺寸封裝件及其製法
TWI488270B (zh) 半導體封裝件及其製法
TWI469310B (zh) 覆晶堆疊封裝結構及其封裝方法
TWI430376B (zh) The Method of Fabrication of Semiconductor Packaging Structure
JP2012009713A5 (zh)
TWI409932B (zh) 具凹槽之封裝結構及其製造方法
TWI467723B (zh) 半導體封裝件及其製法
KR20090041936A (ko) 반도체 소자의 금속 패드
TW201637139A (zh) 電子封裝結構及電子封裝件之製法
JP6792322B2 (ja) 半導体装置及び半導体装置の製造方法
TWI529825B (zh) 半導體結構之製法
TW201405733A (zh) 半導體封裝件及其製法
TWM521807U (zh) 封裝結構及其中介板
TWI381508B (zh) 半導體封裝裝置、半導體封裝結構及其製法
JP7088242B2 (ja) 半導体装置及び半導体装置の製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees