TW201405733A - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TW201405733A
TW201405733A TW101126923A TW101126923A TW201405733A TW 201405733 A TW201405733 A TW 201405733A TW 101126923 A TW101126923 A TW 101126923A TW 101126923 A TW101126923 A TW 101126923A TW 201405733 A TW201405733 A TW 201405733A
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Taiwan
Prior art keywords
interposer
semiconductor package
carrier
semiconductor
encapsulant
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TW101126923A
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English (en)
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TWI614858B (zh
Inventor
陳琬婷
詹慕萱
廖怡茜
林畯棠
賴顗喆
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矽品精密工業股份有限公司
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Priority to TW101126923A priority Critical patent/TWI614858B/zh
Priority to US13/872,468 priority patent/US9087780B2/en
Publication of TW201405733A publication Critical patent/TW201405733A/zh
Priority to US14/716,272 priority patent/US9418874B2/en
Application granted granted Critical
Publication of TWI614858B publication Critical patent/TWI614858B/zh

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Abstract

一種半導體封裝件，其包括承載件、設於該承載件上之中介板、包覆該中介板且外露該中介板頂側之封裝膠體、設置於該中介板頂側之半導體元件、以及形成於該中介板與該半導體元件之間的膠材，以藉該中介板與該封裝膠體之表面幾乎等高，而能提供一平坦度高之置放表面，故當該半導體元件置放於該中介板上時，使該中介板不會產生因翹曲而使中介板與半導體元件間之電性連接發生可靠度不佳之問題。本發明復提供該半導體封裝件之製法。

Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件，尤指一種具矽穿孔之半導體封裝件及其製法。
在現行之覆晶技術因具有縮小晶片封裝面積及縮短訊號傳輸路徑等優點，目前已經廣泛應用於晶片封裝領域，例如，晶片尺寸構裝(Chip Scale Package,CSP)、晶片直接貼附封裝(Direct Chip Attached,DCA)以及多晶片模組封裝(Multi-Chip Module,MCM)等型態的封裝模組，均可利用覆晶技術而達到封裝的目的。
於覆晶封裝製程中，因晶片與封裝基板之熱膨脹係數的差異甚大，故晶片外圍的凸塊無法與封裝基板上對應的接點形成良好的接合，使得凸塊可能自封裝基板上剝離。另一方面，隨著積體電路之積集度的增加，因晶片與封裝基板之間的熱膨脹係數不匹配(mismatch)，其所產生的熱應力(thermal stress)與翹曲(warpage)的現象也日漸嚴重，其結果將導致晶片與封裝基板之間的可靠度(reliability)下降，並造成信賴性測試失敗。
為了解決上述問題，遂發展出以半導體基材作為中介結構的製程，如第1圖所示，係於一封裝基板10與一半導體晶片15之間增設一矽中介板(Silicon interposer)11。因該矽中介板11與該半導體晶片15的材質接近，故可有效避免熱膨脹係數不匹配所產生的問題。
習知半導體封裝件1之製法，係將一整片晶圓形成複數矽穿孔(Through-silicon via,TSV)110後，再將晶圓之欲接置半導體晶片15之一側依需求形成線路重佈結構(Redistribution layer,RDL)111，再將其欲接置封裝基板10之一側形成導電凸塊12，待該晶圓切割形成複數矽中介板11後，再將每一矽中介板11放至該封裝基板10上，再填充底膠14於該矽中介板11與該封裝基板10之間，以包覆該些導電凸塊12。之後，該半導體晶片15藉由複數銲錫凸塊150電性連接該線路重佈結構111，再形成底膠16於該矽中介板11與該半導體晶片15之間，以包覆該些銲錫凸塊150。最後，於該封裝基板10底側形成複數銲球13以接置電路板。
惟，習知半導體封裝件1之製法中，該矽中介板11很薄，經過銲錫凸塊150接置半導體晶片15或導電凸塊12接置封裝基板10時皆須經過熱回銲製程，致使該矽中介板11易發生翹曲，而使該矽中介板11表面之平坦度不佳，故當該半導體晶片15置放於該矽中介板11前後，該半導體晶片15與線路重佈結構111之間的銲錫凸塊150或該矽中介板11與封裝基板10之間的導電凸塊12易發生斷裂之問題，導致該些凸塊之結合可靠度不佳。
再者，單一半導體封裝件1需進行兩次填底膠製程，即於該矽中介板11與該封裝基板10之間、於該矽中介板11與該半導體晶片15之間；故於整版面製程(即量產)中，需於每一半導體封裝件1上一一進行兩次填底膠製 程，因而導致製程時間冗長。
又，若需很薄之矽中介板11(如厚度4mil)進行封裝，於該矽中介板11與該封裝基板10之間形成底膠14時，該底膠14容易發生爬升(creeping)現象，致使該底膠14擴散至該矽中介板11之線路重佈結構111之墊面上，而使該導電凸塊12無法有效接觸該線路重佈結構111之墊面，導致該線路重佈結構111與外接電子元件(如該半導體晶片15)之電性連接失效。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，係包括：承載件；至少一中介板，係設於該承載件上，該中介板具有相對之第一側與第二側，且該中介板以其第一側結合該承載件；封裝膠體，係形成於該承載件上，且包覆該中介板，又該封裝膠體之側面與該承載件之側面齊平；半導體元件，係設置於該中介板之第二側上；以及膠材，係形成於該中介板之第二側與該半導體元件之間。
前述之半導體封裝件中，該中介板係為含矽材質之板體。
本發明復提供一種半導體封裝件之製法，係包括：設置複數中介板於一承載件上，該中介板具有相對之第一側與第二側，該中介板以其第一側結合該承載件；形成封裝 膠體於該承載件上，且包覆該中介板，並令該中介板之第二側外露於該封裝膠體；設置半導體元件於該中介板之第二側上；以及進行切割製程，以形成複數半導體封裝件。
前述之製法中，形成該封裝膠體之製程係包括：形成保護膜於該中介板之第二側上；藉由模具形成該封裝膠體；以及移除該模具與該保護膜。
前述之製法中，形成該封裝膠體之製程係包括：提供具有遮蓋部之模具；置放該中介板和承載件於該模具中，且令該遮蓋部抵靠該中介板之第二側；使該封裝膠體注入該模具中，以包覆該中介板；以及移除該模具。
前述之製法中，復包括形成膠材於該半導體元件與該中介板之第二側之間。
前述之半導體封裝件及製法中，該中介板之第二側與該封裝膠體之表面齊平。
前述之半導體封裝件及其製法中，該承載件係為封裝基板。
前述之半導體封裝件及其製法中，該半導體元件係電性連接該中介板。
另外，前述之半導體封裝件及其製法中，該中介板中係具有連通該第一、二側之導電穿孔。詳細地，該導電穿孔係電性連接該承載件，且該中介板之第二側具有電性連接該導電穿孔之線路重佈結構，該線路重佈結構係電性連接該半導體元件。
由上可知，本發明之半導體封裝件及其製法，係藉由 該承載件提供一平整大版面以使接置於其上之中介板得以平整，再經模壓製程取代習知填底膠製程，使該封裝膠體固定該中介板，以避免該中介板因發生翹曲，而導致中介板連接半導體元件之導電凸塊發生斷裂而電性傳導不佳之可靠度問題，且不會產生底膠(即該膠材)爬升之問題。
再者，該封裝膠體包覆該中介板，使該中介板被保護於該封裝膠體中，使該中介板不會受外界環境影響而發生碎裂。
又，形成該封裝膠體於該承載件上以固定該中介板，故於整版面製程中，僅需一次模壓製程即可固定所有中介板，而不需如習知技術之一一進行填底膠製程，故本發明之製法能大幅縮短製程時間。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”及“一”等之用語，亦僅為便 於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之半導體封裝件2之製法的剖面示意圖。
如第2A圖所示，提供一具有複數封裝基板200之承載件20，且該些封裝基板200上具有一放置區A。
於本實施例中，該封裝基板200之結構種類繁多，並無特別限制。
如第2B圖所示，設置複數中介板21於各該放置區A上，且該中介板21係藉由複數如銲球之導電凸塊22電性連接該封裝基板200，又該中介板21具有相對之第一側21a與第二側21b，而該中介板21係以其第一側21a結合該承載件20。
於本實施例中，如第2B’圖所示，該中介板21中係具有連通該第一側21a並電性連接該承載件20之導電穿孔210，且於該第二側21b具有電性連接該導電穿孔210之線路重佈結構211。
再者，該線路重佈結構211係包含至少一介電層211a與複數線路層211b疊構而成。
又，該中介板21係為含矽材質之板體，如半導體晶片、晶圓或玻璃等。
如第2C圖所示，形成一保護膜23於該中介板21之第二側21b上，再置放該中介板21與該承載件20於一模 具(圖略)中。
如第2D圖所示，形成封裝膠體24於該承載件20上，且該封裝膠體24包覆該些中介板21與該些導電凸塊22。接著，先移除該模具，再移除該保護膜23，以令該中介板21之第二側21b外露於該封裝膠體24。
於本實施例中，該保護膜23係用以保護該中介板21第二側21b後續欲用以接置半導體晶片之墊面不被該封裝膠體24所覆蓋之目的，且該中介板21之第二側21b係齊平該封裝膠體24之表面，且可以紫外線(UV)、化學藥液或加熱等方式移除該保護膜23。
再者，亦可藉由該模具與該保護膜23相結合，以一併移除該模具與該保護膜23。
又，如第2D’圖所示，形成該封裝膠體24以包覆該中介板21之製程亦可不形成該保護膜23，係先提供具有遮蓋部30之模具上蓋3，再置放該中介板21和承載件20於該模具中，使該遮蓋部30抵靠該中介板21之全部第二側21b(即完全蓋住該中介板21之第二側21b)，再注入該封裝膠體24至模具中，以包覆該中介板21，之後移除該模具。
另外，藉由該封裝膠體24(模壓製程)取代習知填底膠製程，故本發明之製法不會產生底膠爬升(creeping)之問題，且藉由該保護膜23或該遮蓋部30，能確保該線路重佈結構211之線路層211b欲接置半導體元件之墊面不會被該封裝膠體24覆蓋。因此，於後續外接電子元件時， 可有效確保該線路重佈結構211之電性傳導。
如第2E圖所示，以覆晶方式設置複數半導體元件25於各該中介板21之第二側21b上，且該半導體元件25係藉由複數導電凸塊250電性連接該中介板21之線路重佈結構211；亦或，將半導體元件25以非作動面接置於該中介板21之第二側21b上，且以打線方式電性連接該中介板21之第二側21b。
接著，形成作為底膠之膠材26於該半導體元件25與該中介板21之第二側21b之間，以包覆該些導電凸塊250；亦或，於打線方式中，可將該半導體元件25之非作動面以該膠材26形成於該中介板21上。
如第2F圖所示，沿該些封裝基板200之邊緣進行切割製程，如第2E圖所示之切割路徑S，以完成複數半導體封裝件2之製作。
本發明之製法中，藉由形成該封裝膠體24作支撐，使極薄之中介板21不會發生翹曲(warpage)，且可保護該中介板21不受外界環境影響而碎裂。
再者，藉由該中介板21之第二側21b齊平該封裝膠體24之表面，以提供一較習知技術更為平坦之置放表面，故當該中介板21連接該半導體元件25時，連接用之導電凸塊250不會發生斷裂而產生電性傳導不佳之可靠度問題，因而有效改善該些導電凸塊250之結合可靠度。
又，形成該封裝膠體24於該承載件20與該些中介板21之間，故複數半導體封裝件1僅需進行一次填膠製程， 即形成該封裝膠體24。因此，於整版面製程(即量產)中，僅需一次模壓製程即可固定所有中介板21於承載件20上，而不需如習知技術之一一進行填底膠製程，故本發明之製法能大幅縮短製程時間。
本發明復提供一種半導體封裝件2，其包括：一承載件20、設於該承載件20上之一中介板21、形成於該承載件20上之封裝膠體24、設置於該中介板21上之一半導體元件25、以及形成於該半導體元件25與該中介板21之間的膠材26。
所述之承載件20係為封裝基板200。
所述之中介板21係具有相對之第一側21a與第二側21b，且該中介板21以其第一側21a結合該承載件20，又該中介板21中係具有連通該第一側21a並電性連接該承載件20之導電穿孔210，且於該第二側21b具有電性連接該導電穿孔210之線路重佈結構211。
所述之封裝膠體24係包覆該中介板21，且該封裝膠體24之側面與該承載件20之側面齊平。於其它實施例中，該中介板21之第二側21b與該封裝膠體24之表面齊平。
所述之半導體元件25係設置於該中介板21之第二側21b上，且電性連接該線路重佈結構211。
所述之膠材26係形成於該半導體元件25與該中介板21之第二側21b之間。
綜上所述，本發明之半導體封裝件及其製法，主要藉由於該承載件上形成包覆該中介板之封裝膠體，使該中介 板不會發生翹曲，且能提供一平坦度高之置放表面，以當置放該半導體元件時，該中介板不會產生因翹曲而導致用於連接該中介板與該半導體元件之導電凸塊發生斷裂進而使電性傳導不佳之可靠度之問題。
再者，於該承載件上進行模壓製程，故於整版面製程中，僅需一次模壓製程即可固定所有該中介板，因而能大幅縮短製程時間。
又，於該中介板之第一側並無進行填底膠製程，故不會產生膠材爬升之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2‧‧‧半導體封裝件
10,200‧‧‧封裝基板
11‧‧‧矽中介板
110‧‧‧矽穿孔
111,211‧‧‧線路重佈結構
12,22,250‧‧‧導電凸塊
13‧‧‧銲球
14,16‧‧‧底膠
15‧‧‧半導體晶片
150‧‧‧銲錫凸塊
20‧‧‧承載件
21‧‧‧中介板
21a‧‧‧第一側
21b‧‧‧第二側
210‧‧‧導電穿孔
211a‧‧‧介電層
211b‧‧‧線路層
23‧‧‧保護膜
24‧‧‧封裝膠體
25‧‧‧半導體元件
26‧‧‧膠材
3‧‧‧模具上蓋
30‧‧‧遮蓋部
A‧‧‧放置區
S‧‧‧切割路徑
第1圖係為習知半導體封裝件之剖視示意圖；以及第2A至2F圖係為本發明之半導體封裝件之製法的剖視示意圖；其中，第2B’圖係為第2B圖之局部放大圖，第2D’圖係為第2C圖之另一實施例。
2‧‧‧半導體封裝件
20‧‧‧承載件
21‧‧‧中介板
21a‧‧‧第一側
21b‧‧‧第二側
24‧‧‧封裝膠體
25‧‧‧半導體元件
26‧‧‧膠材

Claims (18)

  1. 一種半導體封裝件，係包括：承載件；至少一中介板，係設於該承載件上，該中介板具有相對之第一側與第二側，且該中介板以其第一側結合該承載件；封裝膠體，係形成於該承載件上，且包覆該中介板，又該封裝膠體之側面與該承載件之側面齊平；半導體元件，係設置於該中介板之第二側上；以及膠材，係形成於該中介板之第二側與該半導體元件之間。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該承載件係為封裝基板。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該中介板中係具有連通該第一、二側之導電穿孔。
  4. 如申請專利範圍第3項所述之半導體封裝件，其中，該導電穿孔係電性連接該承載件。
  5. 如申請專利範圍第3項所述之半導體封裝件，其中，該中介板之第二側具有電性連接該導電穿孔之線路重佈結構，該線路重佈結構係電性連接該半導體元件。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該中介板之第二側與該封裝膠體之表面齊平。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中， 該半導體元件係電性連接該中介板。
  8. 如申請專利範圍第1項所述之半導體封裝件，其中，該中介板係為含矽材質之板體。
  9. 一種半導體封裝件之製法，係包括：設置複數中介板於一承載件上，該中介板具有相對之第一側與第二側，該中介板以其第一側結合該承載件；形成封裝膠體於該承載件上，且包覆該中介板，並令該中介板之第二側外露於該封裝膠體；設置半導體元件於該中介板之第二側上；以及進行切割製程，以形成複數半導體封裝件。
  10. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該承載件係為封裝基板。
  11. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該中介板之第二側與該封裝膠體之表面齊平。
  12. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該中介板中係具有連通該第一、二側之導電穿孔。
  13. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，該導電穿孔係電性連接該承載件。
  14. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，該中介板之第二側具有電性連接該導電穿孔之線路重佈結構，該線路重佈結構係電性連接該半導體元件。
  15. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，形成該封裝膠體之製程係包括：形成保護膜於該中介板之第二側上；藉由模具形成該封裝膠體；以及移除該模具與該保護膜。
  16. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，形成該封裝膠體之製程係包括：提供具有遮蓋部之模具；置放該中介板和承載件於該模具中，且令該遮蓋部抵靠該中介板之第二側；使該封裝膠體注入該模具中，以包覆該中介板；以及移除該模具。
  17. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該半導體元件係電性連接該中介板。
  18. 如申請專利範圍第9項所述之半導體封裝件之製法，復包括形成膠材於該半導體元件與該中介板之第二側之間。
TW101126923A 2012-07-26 2012-07-26 半導體封裝件及其製法 TWI614858B (zh)

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