CN102556938B - 芯片叠层封装结构及其制造方法 - Google Patents
芯片叠层封装结构及其制造方法 Download PDFInfo
- Publication number
- CN102556938B CN102556938B CN201110456798.7A CN201110456798A CN102556938B CN 102556938 B CN102556938 B CN 102556938B CN 201110456798 A CN201110456798 A CN 201110456798A CN 102556938 B CN102556938 B CN 102556938B
- Authority
- CN
- China
- Prior art keywords
- chip
- support metal
- substrate
- metal line
- package structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本发明提供了一种芯片叠层封装结构及其制造方法,所述芯片叠层封装结构包括:基底;第一芯片,设置在基底上并电连接到基底;支撑金属线,设置在基底上,支撑金属线的端部结合到基底并与基底电断开;第二芯片,设置在第一芯片和支撑金属线上,第二芯片具有延伸超出第一芯片的悬臂梁部分,第二芯片与第一芯片背对的上表面上设置有结合焊盘,其中,所述结合焊盘位于支撑金属线上方;包封材料,包封第一芯片、支撑金属线和第二芯片。
Description
技术领域
本发明涉及一种芯片叠层封装结构及其制造方法,更具体地讲,本发明涉及一种利用支撑金属线支撑上层芯片从而不仅提高多芯片悬臂梁封装结构的设计自由度,而且还提高了其产品的稳定性与品质的芯片叠层封装结构及其制造方法。
背景技术
随着半导体产业的飞速发展及其向各行业的迅速渗透,电子封装已经逐步成为实现半导体芯片功能的一个瓶颈,电子封装因此在近二三十年内获得了巨大的发展,并已经取得了长足的进步。
现代便携式电子产品对微电子封装提出了更高的要求,其对更轻、更薄、更小、高可靠性、低功耗的不断追求推动微电子封装朝着密度更高的三维封装方式发展。芯片叠层封装(Stacked die package)是一种得到广泛应用的三维封装技术。芯片叠层封装不但提高了封装密度,降低了封装成本,同时也减小了芯片之间的互连导线长度,从而提高了器件的运行速度,而且通过叠层封装还可以实现器件的多功能化。初级的3D芯片叠层封装是把多个芯片在垂直方向上累叠起来,利用传统的引线封装结构,然后再进行封装。由于这种结构的特殊性,芯片和基底之间,芯片和芯片之间的互连是叠层封装的关键,现在普遍是以引线键合方式实现叠层封装的互连,其方式主要有2种:一种是金字塔型的叠层封装,使用大小不同的芯片,上层的芯片的面积要小于下层,这样下层芯片表面就有足够的面积和空间可以用来进行引线键合;另一种是使用大小相同的芯片,通过在上下层芯片之间加入一层芯片(即垫片)以便于下层芯片的引线键合,垫片是一块面积比上下层芯片小的普通硅片,使用这两种结构都可以制造出多层芯片的叠层封装。为避免对现有工艺进行大的改动,叠层封装一般通过减薄芯片的厚度来保证总的封装厚度不变,但是芯片厚度的减少会造成芯片刚度减小,芯片易于变形,在热处理过程中芯片内应力集中点甚至会造成芯片的破坏。此外,由于塑封料厚度的减小,阻止水汽侵入芯片和塑封料界面的能力减弱,水汽的侵入会促使裂纹的产生和扩展。
已经开发出了另外一种实现叠层封装的互连结构,其中,上层芯片与下层芯片交叉设置,即,上层芯片形成悬臂梁结构。然而,在现有的多芯片悬臂梁叠层结构中,超薄芯片由于自身内应力和封装工程中的力学加载,不可避免会遇到封装设计和工程作业上的困难。如果上层芯片悬臂梁太长,芯片在引线键合过程中弹性变形很容易造成芯片碎裂。不仅大大降低了工程良率,也使多层芯片结构在设计时的自由度降低。
发明内容
为了解决上述问题中的至少一个,本发明提供了一种芯片叠层封装结构,所述芯片叠层封装结构包括:基底;第一芯片,设置在基底上并电连接到基底;支撑金属线,设置在基底上,支撑金属线的端部结合到基底并与基底电断开;第二芯片,设置在第一芯片和支撑金属线上,第二芯片具有延伸超出第一芯片的悬臂梁部分,第二芯片与第一芯片背对的上表面上设置有结合焊盘,其中,所述结合焊盘位于支撑金属线上方;包封材料,包封第一芯片、支撑金属线和第二芯片。
根据本发明的芯片叠层封装结构,其特征在于,第一芯片通过引线键合或倒装芯片的方式电连接到基底。
根据本发明的芯片叠层封装结构,其特征在于,支撑金属线与第一芯片的一侧边缘相邻。
根据本发明的芯片叠层封装结构,其特征在于,支撑金属线与第一芯片的彼此相对的两侧边缘相邻。
根据本发明的芯片叠层封装结构,其特征在于,基底上设置有无电连接的结合焊盘,支撑金属线的端部通过键合结合到基底的所述无电连接的结合焊盘。
根据本发明的芯片叠层封装结构,其特征在于,支撑金属线的外表面可以但不限于涂覆有不导电粘合材料。
根据本发明的芯片叠层封装结构,其特征在于,所述不导电粘合材料为环氧树脂或胶膜。
根据本发明的芯片叠层封装结构,其特征在于,第二芯片通过粘合材料粘结到第一芯片和支撑金属线。
根据本发明的芯片叠层封装结构,其特征在于,支撑金属线由金、铜、铝或合金材料制成。
根据本发明的芯片叠层封装结构,其特征在于,支撑金属线的直径由第二芯片的悬臂梁部分与基底之间的空隙的大小决定。
本发明的示例性实施例还提供了一种制造芯片叠层封装结构的方法,所述方法包括下述步骤:准备基底;将第一芯片设置在基底上并将第一芯片电连接到基底;在基底上设置支撑金属线,支撑金属线的端部结合到基底并与基底电断开;将第二芯片设置在第一芯片和支撑金属线上,第二芯片具有延伸超出第一芯片的悬臂梁部分,第二芯片与第一芯片背对的上表面上设置有结合焊盘,其中,所述结合焊盘位于支撑金属线上方;利用包封材料包封第一芯片、支撑金属线和第二芯片。
根据本发明的制造芯片叠层封装结构的方法,其特征在于,通过引线键合或倒装芯片的方式将第一芯片电连接到基底。
根据本发明的制造芯片叠层封装结构的方法,其特征在于,将支撑金属线设置成与第一芯片的一侧边缘相邻。
根据本发明的制造芯片叠层封装结构的方法,其特征在于,将支撑金属线设置成与第一芯片的彼此相对的两侧边缘相邻。
根据本发明的制造芯片叠层封装结构的方法,其特征在于,所述方法还包括:在基底上设置无电连接的结合焊盘,支撑金属线的端部通过键合结合到基底的所述无电连接的结合焊盘。
根据本发明的制造芯片叠层封装结构的方法,其特征在于,所述方法还包括:可以用不导电粘合材料涂覆支撑金属线的外表面,但不限于此。
根据本发明的制造芯片叠层封装结构的方法,其特征在于,所述不导电粘合材料为环氧树脂或胶膜。
根据本发明的制造芯片叠层封装结构的方法,其特征在于,将第二芯片设置在第一芯片和支撑金属线上的步骤包括:通过粘合材料将第二芯片粘结到第一芯片和支撑金属线。
根据本发明的制造芯片叠层封装结构的方法,其特征在于,由金、铜、铝或合金材料制成支撑金属线。
根据本发明的制造芯片叠层封装结构的方法,其特征在于,由第二芯片的悬臂梁部分与基底之间的空隙的大小决定支撑金属线的直径。
根据本发明的示例性实施例,提出一种在上层芯片的悬臂梁结构下方使用支撑金属线的方法,不仅提高多芯片悬臂梁封装结构的设计自由度,而且还提高了其产品的稳定性与品质。
附图说明
通过结合附图对本发明示例性实施例进行的以下详细描述,本发明的这些和/或其他方面和优点将变得清楚和更易于理解,其中:
图1a是示出根据现有技术的采用倒装芯片的芯片叠层封装结构的示意性剖视图;
图1b是示出根据现有技术的采用倒装芯片的芯片叠层封装结构的示意性平面图;
图2a是示出根据现有技术的采用引线键合的芯片叠层封装结构的示意性剖视图;
图2b是示出根据现有技术的采用引线键合的芯片叠层封装结构的示意性平面图;
图3是示出根据现有技术的半导体芯片叠层封装结构的形成工艺的示意性流程图;
图4a是示出根据本发明示例性实施例的芯片叠层封装结构的示意性剖视图;
图4b是示出根据本发明示例性实施例的芯片叠层封装结构的示意性剖视图;
图4c是示出根据本发明示例性实施例的芯片叠层封装结构的示意性平面图;
图5是示出根据本发明另一示例性实施例的芯片叠层封装结构的示意性平面图;
图6a是示出根据本发明另一示例性实施例的芯片叠层封装结构的示意性剖视图;
图6b是示出根据本发明另一示例性实施例的芯片叠层封装结构的示意性平面图;
图6c是示出根据本发明另一示例性实施例的芯片叠层封装结构的示意性平面图;
图7a1、图7b 1、图7c1、图7d1、图7e 1、图7f1是示出根据本发明示例性实施例的制造芯片叠层封装结构的方法的示意性平面图;
图7a2、图7b2、图7c2、图7d2、图7e2、图7f2是示出根据本发明示例性实施例的制造芯片叠层封装结构的方法的示意性剖视图;
图8a1、图8b 1、图8c1、图8d1、图8e1、图8f1是示出根据本发明另一示例性实施例的制造芯片叠层封装结构的方法的示意性平面图;
图8a2、图8b2、图8c2、图8d2、图8e2、图8f2是示出根据本发明另一示例性实施例的制造芯片叠层封装结构的方法的示意性剖视图。
具体实施方式
在下文中参照附图更充分地描述了本发明,在附图中示出了本发明的示例性实施例。然而,本发明可以以许多不同的形式来实施,且不应该解释为局限于在这里所提出的实施例。相反,提供这些实施例使得本公开将是彻底和完全的,并将本发明的范围充分地传达给本领域技术人员。在附图中,为了清晰起见,会夸大层和区域的尺寸和相对尺寸。附图中,相同或相似的标记始终表示相同的元件。
图1a是示出根据现有技术的采用倒装芯片的芯片叠层封装结构的示意性剖视图,图1b是示出根据现有技术的采用倒装芯片的芯片叠层封装结构的示意性平面图。如图1a所示,第一芯片20设置在基底(例如,所述基底可以为印刷电路板)10上,并以倒装芯片的方式实现与基底10的电连接,第二芯片30通过粘合材料70设置在第一芯片20上,第二芯片30形成有悬臂梁结构。第二芯片30通过引线键合与基底10实现电连接,具体地,利用例如金线的引线50将第二芯片30上的结合焊盘200与基底10上的结合焊盘210电连接,其中两个芯片20和30可以呈交叉(例如垂直)叠层结构分布,并且第二芯片30具有悬臂梁结构,通过包封材料(例如环氧树脂)40将芯片叠层结构包封。
图2a是示出根据现有技术的采用引线键合的芯片叠层封装结构的示意性剖视图,图2b是示出根据现有技术的采用引线键合的芯片叠层封装结构的示意性平面图。图2a和图2b中示出的芯片叠层封装结构与图1a中示出的芯片叠层封装结构相似,其区别仅在于第一芯片20是通过引线键合的方式实现与基底10的电连接。
图3是示出根据现有技术的半导体芯片叠层封装结构的形成工艺的示意性流程图。
半导体封装通过两种方式来实现:方式一,通过环氧树脂,胶膜等粘合材料将第一芯片贴装在印刷电路板上;烘烤将粘合材料固化后,进行引线键合,连接芯片焊盘与基底金手指;然后再通过粘合材料将第二芯片贴装在第一芯片上面,呈悬臂梁式叠层结构,固化后,进行金线键合,连接芯片焊盘与基底金手指;铸模后进行烘烤对环氧树脂进行固化,打标完成后,将锡焊球贴装在基底背面焊球焊盘上;然后进行颗粒切割分离;目检后完成半导体封装流程,进入测试流程。方式二,第一芯片通过倒贴片方式贴装在印刷电路板上;使用焊球或者金属凸点连接芯片焊盘与基底金手指;回流完毕后再使用填充材料进行倒贴片,并将芯片与基底间空隙填充并固化。然后再通过粘合材料将第二芯片贴装在第一芯片上面,呈悬臂梁式叠层结构,固化后,进行引线键合,连接芯片焊盘与基底金手指;铸模后进行烘烤对环氧树脂进行固化,打标完成后,将锡焊球贴装在基底背面焊球焊盘上;然后进行颗粒切割分离;目检后完成半导体封装流程,进入测试流程。
在图1a至图2b所示的芯片悬臂梁叠层结构中,超薄芯片由于自身内应力和封装工程中的力学加载,不可避免会遇到封装设计和工程作业上的困难。如果上层芯片悬臂梁太长,芯片在引线键合过程中弹性变形,很容易造成芯片碎裂,不仅大大降低了工程良率,也使多层芯片结构在设计时的自由度降低。
为了解决上述问题,本发明提供了一种芯片叠层封装结构及其制造方法。图4a是示出根据本发明示例性实施例的芯片叠层封装结构的示意性剖视图,图4b是示出根据本发明示例性实施例的芯片叠层封装结构的另一角度的示意性剖视图,图4c是示出根据本发明示例性实施例的芯片叠层封装结构的示意性平面图。
参照图4a至图4c,根据本发明示例性实施例的芯片叠层封装结构包括:基底10;第一芯片20,通过粘合材料60设置在基底10上并电连接到基底10,所述粘合材料60可包括例如环氧树脂、胶膜等,第一芯片20包括背对基底10的第一表面和面对基底10的第二表面;支撑金属线80,设置在基底10上,支撑金属线80的端部结合到基底10并与基底10电断开,即,支撑金属线80与基底10电绝缘;第二芯片30,通过粘合材料70设置在第一芯片20和支撑金属线80上,第二芯片30在第一芯片20上形成悬臂梁结构,并且悬臂梁部分超出第一芯片20并与基底10平行,第二芯片30与第一芯片20背对的上表面上设置有结合焊盘200,其中,所述结合焊盘200位于支撑金属线80上方,第二芯片30可以通过结合焊盘200通过例如金线的引线50以引线键合的方式实现与基底10上的结合焊盘210的电连接;包封材料40,包封第一芯片20、支撑金属线80和第二芯片30,包封材料40可包括环氧树脂等。
在根据本发明的示例性实施例的芯片叠层封装结构中,第一芯片20的第一表面上设置有结合焊盘100,第一芯片20通过设置在第一表面上的结合焊盘100通过例如金线的引线150以引线键合方式电连接到基底上的结合焊盘110(如图4c所示)。然而,本发明不限于此。例如,根据本发明的另一示例性实施例,第一芯片20的第二表面上设置有结合焊盘,第一芯片20可以通过设置在第二表面上的结合焊盘以倒装芯片的方式电连接到基底10。
图4c示出了第一芯片与第二芯片相交(例如垂直相交)并且支撑金属线与第一芯片的彼此相对的两侧边缘相邻的情况。在这种情况下,参照图4c,在设置在第二芯片30上的结合焊盘下方设置有支撑金属线80,所述支撑金属线80能够支撑第二芯片30的相对的两侧边缘,以此结构,第二芯片30的悬臂梁部分就能够由支撑金属线80形成较坚固的有效支撑,从而减小第二芯片在进行键合过程中发生弹性变形,提高了封装结构的稳定性与品质。
然而,本发明不限于此。例如,图5是示出根据本发明另一示例性实施例的芯片叠层封装结构的示意性平面图。参照图5,根据本发明的另一示例性实施例,支撑金属线80可以与第一芯片20的一侧边缘相邻。在这种情况下,第二芯片30设置为与第一芯片20相交(例如垂直相交),第二芯片30的一侧边缘下方设置有支撑金属线80,其中,支撑金属线80设置在位于第二芯片上的结合焊盘200的正下方,从而第二芯片的悬臂梁部分就能够由支撑金属线80形成较坚固的有效支撑,从而减小第二芯片在进行键合过程中发生弹性变形,提高了封装结构的稳定性与品质。
参照图4b和图4c,基底10上设置有无电连接的结合焊盘90,支撑金属线80的端部通过键合结合到基底10的所述无电连接的结合焊盘90。
根据本发明的示例性实施例,支撑金属线80可以由金、铜、铝或合金材料制成。支撑金属线80的直径由第二芯片30的悬臂梁部分与基底10之间的空隙大小决定。在一个示例性实施例中,支撑金属线80的直径与第二芯片30的悬臂梁部分与基底10之间的空隙的大小大致相当。
以下,参照图6a至图6c详细描述根据本发明的另一示例性实施例的芯片叠层封装结构。
图6a是示出根据本发明另一示例性实施例的芯片叠层封装结构的示意性剖视图,图6b是示出根据本发明另一示例性实施例的芯片叠层封装结构的示意性平面图,图6c是示出根据本发明另一示例性实施例的芯片叠层封装结构的示意性平面图。
参照图6a,图6a中示出的根据本发明另一示例性实施例的芯片叠层封装结构与图4b中示出的根据本发明示例性实施例的芯片叠层封装结构相似,在此将省略对于重复部分的详细描述,其区别仅在于:在图6a中示出的芯片叠层封装结构中,利用非导电粘合材料300对支撑金属线80进行涂覆,从而通过涂覆有非导电粘合材料300的支撑金属线80对第二芯片30的侧部提供支撑。
图6b中示出的根据本发明另一示例性实施例的芯片叠层封装结构与图4c中示出的根据本发明示例性实施例的芯片叠层封装结构相对应,在此将省略对于重复部分的详细描述,其区别仅在于:在图6b中示出的芯片叠层封装结构中,利用非导电粘合材料300对支撑金属线80进行涂覆,从而通过涂覆有非导电粘合材料300的支撑金属线80对第二芯片30的两侧边缘提供支撑。
图6c中示出的根据本发明另一示例性实施例的芯片叠层封装结构与图5中示出的根据本发明示例性实施例的芯片叠层封装结构相对应,在此将省略对于重复部分的详细描述,其区别仅在于:在图6c中示出的芯片叠层封装结构中,利用非导电粘合材料300对支撑金属线80进行涂覆,从而通过涂覆有非导电粘合材料300的支撑金属线80对第二芯片30的一侧边缘提供支撑。
以下,将参照图7a1至图7f2详细描述根据本发明的示例性实施例的制造芯片叠层封装结构的方法。
图7a1、图7b1、图7c1、图7d1、图7e1、图7f1是示出根据本发明示例性实施例的制造芯片叠层封装结构的方法的示意性平面图,图7a2、图7b2、图7c2、图7d2、图7e2、图7f2是示出根据本发明示例性实施例的制造芯片叠层封装结构的方法的示意性剖视图。
首先,参照图7a1和图7a2,准备基底10,在基底10上形成无电连接的结合焊盘90和结合焊盘210;之后,参照图7b1和图7b2,通过粘合材料60将第一芯片20设置在基底10上,所述粘合材料60可包括例如环氧树脂、胶膜等,第一芯片20可通过利用例如金线引线键合到基底10上实现与基底10的电连接或者以倒装芯片的方式与基底10电连接,如果第一芯片采用倒装芯片方式,则是通过焊球或者金属凸点将其贴装在基底上,并在回流后进行底部填充,然后进行烘烤,固化贴装完成的第一芯片20;之后,参照图7c1和图7c2,将支撑金属线80设置在基底10上,支撑金属线80的端部可通过键合的方式结合到基底10的无电连接的结合焊盘90上,这里图7c 1示出了支撑金属线80设置在第一芯片两侧的结构,然而,本发明不限于此,例如可根据需要将支撑金属线80设置在第一芯片的一侧,以形成图5中示出的芯片叠层封装结构;然后,参照图7d1和图7d2,使支撑金属线80平坦化;然后,参照图7e1和图7e2,通过粘合材料70将第二芯片30设置在第一芯片20和支撑金属线80上,使得第二芯片30在第一芯片20上形成悬臂梁结构,并且悬臂梁部分超出第一芯片20并与基底10平行;之后进行烘烤,固化贴装完成的第二芯片30;在第二芯片30与第一芯片20背对的上表面上设置结合焊盘200,其中,所述结合焊盘200位于支撑金属线80上方,第二芯片30可以通过结合焊盘200通过例如金线的引线50以引线键合的方式实现与基底10上的结合焊盘210的电连接;最后利用包封材料40包封第一芯片20、支撑金属线80和第二芯片30,并对包封材料40进行固化,包封材料40可包括环氧树脂等。打标完成后,将锡焊球贴装在基底背面焊球焊盘上;最后进行颗粒切割分离;目检后完成半导体封装流程。在示例性实施例中,支撑金属线的直径可由第二芯片的悬臂梁部分与基底之间的空隙的大小决定,即,支撑金属线的直径可与第二芯片的悬臂梁部分与基底之间的空隙的大小大致相当。
这里,可以使用两种方法使支撑金属线80平坦化,一是使用上压板下压方式,一是直接利用第二芯片30贴片,在贴片工艺中第二芯片30下压使支撑金属线80自然平坦。支撑金属线80上表面通过第二芯片背面的粘合材料(例如贴片胶膜或环氧树脂)与之实现连接,从而对悬臂梁结构实现有效支撑,大大减少金线键合工程中悬臂梁部分的振动对产品造成的不良影响。
图8a1至图8f2示出了根据本发明的另一示例性实施例的制造芯片叠层封装结构的方法。
图8a1至图8f2中示出的根据本发明的另一示例性实施例的制造芯片叠层封装结构的方法与图7a1至图7f2中示出的根据本发明的示例性实施例的制造芯片叠层封装结构的方法相似,因此省略对相同步骤的详细描述,它们之间的区别仅在于:利用非导电粘合材料300对支撑金属线80进行涂覆,从而通过涂覆有非导电粘合材料300的支撑金属线80对第二芯片30的侧部提供支撑。这里,非导电粘合材料300可以包括环氧树脂或胶膜等粘合材料。
根据本发明的示例性实施例的芯片叠层封装结构,通过在上层芯片的悬臂梁结构下方使用支撑金属线的方法,上层芯片的悬臂梁部分就能够由支撑金属线形成坚固有效支撑,从而减小顶层芯片在进行键合过程中发生弹性变形,不仅提高多芯片悬臂梁封装结构的设计自由度,而且提高了封装结构的稳定性与品质。
尽管已经给出了本发明的一些示例性实施例,但对于本领域普通技术人员来说清楚的是,应当仅以描述的意义理解示例性实施例,而不是出于限制本发明的目的。在不脱离权利要求限定的本发明的精神和范围的情况下,可以在此作出形式和细节上的多种改变。
Claims (12)
1.一种芯片叠层封装结构,所述芯片叠层封装结构包括:
基底,基底上设置有无电连接的结合焊盘;
第一芯片,设置在基底上并电连接到基底;
外表面涂覆有不导电粘合材料的支撑金属线,设置在基底上,支撑金属线的端部通过键合结合到基底的所述无电连接的结合焊盘并与基底电断开;
第二芯片,设置在第一芯片和支撑金属线上,第二芯片具有延伸超出第一芯片的悬臂梁部分,第二芯片与第一芯片背对的上表面上设置有结合焊盘,其中,所述结合焊盘位于支撑金属线上方;
包封材料,包封第一芯片、支撑金属线和第二芯片,
其中,支撑金属线与第一芯片的仅一侧边缘相邻或与第一芯片的彼此相对的仅两侧边缘相邻。
2.如权利要求1所述的芯片叠层封装结构,其特征在于,第一芯片通过引线键合或倒装芯片的方式电连接到基底。
3.如权利要求1所述的芯片叠层封装结构,其特征在于,所述不导电粘合材料为环氧树脂或胶膜。
4.如权利要求1所述的芯片叠层封装结构,其特征在于,第二芯片通过粘合材料粘结到第一芯片和支撑金属线。
5.如权利要求1所述的芯片叠层封装结构,其特征在于,支撑金属线由金、铜、铝或合金材料制成。
6.如权利要求1所述的芯片叠层封装结构,其特征在于,支撑金属线的直径由第二芯片的悬臂梁部分与基底之间的空隙的大小决定。
7.一种制造芯片叠层封装结构的方法,所述方法包括下述步骤:
准备基底并在基底上设置无电连接的结合焊盘;
将第一芯片设置在基底上并将第一芯片电连接到基底;
在基底上设置支撑金属线,支撑金属线的端部通过键合结合到基底的所述无电连接的结合焊盘并与基底电断开;
用不导电粘合材料涂覆支撑金属线的外表面;
将第二芯片设置在第一芯片和支撑金属线上,第二芯片具有延伸超出第一芯片的悬臂梁部分,第二芯片与第一芯片背对的上表面上设置有结合焊盘,其中,所述结合焊盘位于支撑金属线上方;
利用包封材料包封第一芯片、支撑金属线和第二芯片,
其中,将支撑金属线设置成与第一芯片的仅一侧边缘相邻或与第一芯片的彼此相对的仅两侧边缘相邻。
8.如权利要求7所述的方法,其特征在于,通过引线键合或倒装芯片的方式将第一芯片电连接到基底。
9.如权利要求7所述的方法,其特征在于,所述不导电粘合材料为环氧树脂或胶膜。
10.如权利要求7所述的方法,其特征在于,将第二芯片设置在第一芯片和支撑金属线上的步骤包括:通过粘合材料将第二芯片粘结到第一芯片和支撑金属线。
11.如权利要求7所述的方法,其特征在于,由金、铜、铝或合金材料制成支撑金属线。
12.如权利要求7所述的方法,其特征在于,由第二芯片的悬臂梁部分与基底之间的空隙的大小决定支撑金属线的直径。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110456798.7A CN102556938B (zh) | 2011-12-27 | 2011-12-27 | 芯片叠层封装结构及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110456798.7A CN102556938B (zh) | 2011-12-27 | 2011-12-27 | 芯片叠层封装结构及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102556938A CN102556938A (zh) | 2012-07-11 |
CN102556938B true CN102556938B (zh) | 2015-07-15 |
Family
ID=46403779
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110456798.7A Active CN102556938B (zh) | 2011-12-27 | 2011-12-27 | 芯片叠层封装结构及其制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN102556938B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109087895B (zh) * | 2017-06-13 | 2020-09-25 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制作方法、电子装置 |
CN117641722A (zh) * | 2022-08-19 | 2024-03-01 | 长鑫存储技术有限公司 | 半导体封装基板及其制造方法、半导体封装结构 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100702968B1 (ko) * | 2005-11-24 | 2007-04-03 | 삼성전자주식회사 | 플로팅된 히트 싱크를 갖는 반도체 패키지와, 그를 이용한적층 패키지 및 그의 제조 방법 |
KR20080020137A (ko) * | 2006-08-30 | 2008-03-05 | 주식회사 하이닉스반도체 | 역피라미드 형상의 적층 반도체 패키지 |
CN101232004A (zh) * | 2007-01-23 | 2008-07-30 | 联华电子股份有限公司 | 芯片堆叠封装结构 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001320014A (ja) * | 2000-05-11 | 2001-11-16 | Seiko Epson Corp | 半導体装置及びその製造方法 |
TWI231977B (en) * | 2003-04-25 | 2005-05-01 | Advanced Semiconductor Eng | Multi-chips package |
TWI229434B (en) * | 2003-08-25 | 2005-03-11 | Advanced Semiconductor Eng | Flip chip stacked package |
-
2011
- 2011-12-27 CN CN201110456798.7A patent/CN102556938B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100702968B1 (ko) * | 2005-11-24 | 2007-04-03 | 삼성전자주식회사 | 플로팅된 히트 싱크를 갖는 반도체 패키지와, 그를 이용한적층 패키지 및 그의 제조 방법 |
KR20080020137A (ko) * | 2006-08-30 | 2008-03-05 | 주식회사 하이닉스반도체 | 역피라미드 형상의 적층 반도체 패키지 |
CN101232004A (zh) * | 2007-01-23 | 2008-07-30 | 联华电子股份有限公司 | 芯片堆叠封装结构 |
Also Published As
Publication number | Publication date |
---|---|
CN102556938A (zh) | 2012-07-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5529371B2 (ja) | 半導体装置及びその製造方法 | |
KR101661442B1 (ko) | 반도체 패키지 조립체를 위한 스터드 범프 구조 | |
CN102456677A (zh) | 球栅阵列封装结构及其制造方法 | |
TW201351579A (zh) | 高密度立體封裝 | |
TW201511209A (zh) | 半導體裝置及半導體裝置之製造方法 | |
KR20050119414A (ko) | 에지 패드형 반도체 칩의 스택 패키지 및 그 제조방법 | |
CN101872757B (zh) | 凹穴芯片封装结构及使用其的层叠封装结构 | |
CN202549824U (zh) | 芯片封装结构 | |
CN101477979B (zh) | 多芯片封装体 | |
CN105762084A (zh) | 倒装芯片的封装方法及封装装置 | |
KR101640078B1 (ko) | 적층형 반도체 패키지 및 이의 제조 방법 | |
TWI416700B (zh) | 晶片堆疊封裝結構及其製造方法 | |
CN103187404A (zh) | 半导体芯片堆叠封装结构及其工艺 | |
TWI578472B (zh) | 封裝基板、半導體封裝件及其製法 | |
CN102556938B (zh) | 芯片叠层封装结构及其制造方法 | |
TWI424552B (zh) | 三維立體堆疊晶片封裝結構 | |
US9312243B2 (en) | Semiconductor packages | |
CN101131992A (zh) | 多芯片堆栈式的封装结构 | |
CN105914155A (zh) | 一种倒装芯片及其封装方法 | |
KR101494411B1 (ko) | 반도체패키지 및 이의 제조방법 | |
KR20110138788A (ko) | 적층형 반도체 패키지 | |
JP2010147225A (ja) | 半導体装置及びその製造方法 | |
CN102651323B (zh) | 半导体封装结构的制法 | |
CN113410215B (zh) | 半导体封装结构及其制备方法 | |
CN102751203A (zh) | 半导体封装结构及其制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |