CN101477979B - 多芯片封装体 - Google Patents

多芯片封装体 Download PDF

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CN101477979B
CN101477979B CN2008100020067A CN200810002006A CN101477979B CN 101477979 B CN101477979 B CN 101477979B CN 2008100020067 A CN2008100020067 A CN 2008100020067A CN 200810002006 A CN200810002006 A CN 200810002006A CN 101477979 B CN101477979 B CN 101477979B
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chip
substrate
window
encapsulation body
chips
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CN101477979A (zh
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杜茂华
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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Abstract

本发明提供了一种多芯片封装体。所述多芯片封装体包括基板、多个芯片和有机树脂，其特征在于：所述基板至少具有一个窗口，所述多个芯片的至少一个芯片位于所述窗口内并与连接到所述窗口周围的基板的至少另一个芯片相连接。本发明通过基板的窗口设计，充分提高了封装体基板的利用率，从而增加了封装的集成度。

Description

多芯片封装体
                         技术领域
本发明涉及一种半导体封装体。更具体地讲，本发明涉及一种封装有多个芯片的半导体封装体。
                         背景技术
随着移动消费型电子产品对于小型化、功能集成以及大容量存储空间要求的进一步提升，元器件的小型化、高密度封装结构也越来越多，如多模块封装(MCM)、系统封装(SiP)、倒装芯片等应用得越来越多。
为了提高封装密度，通常采用芯片堆叠的方式进行封装。图1和图2分别示出了多芯片封装体，图1示出了多个芯片形成在基板同一侧的情况，图2示出了多个芯片形成在基板不同侧的情况。
如图1所示，芯片10通过非导电胶或非导电薄膜30被固定在基板32的一侧上。基板32用于支撑芯片10。芯片20通过非导电胶或非导电薄膜30被固定在芯片10上。这样，芯片10和芯片20位于基板32的同一侧。芯片10和芯片20分别通过金线34与基板32相互连接。在基板32的形成有芯片的一侧，将封装树脂注塑成模封树脂31来保护芯片10、芯片20和金线34。在基板32的另一侧形成有多个焊球33，用于将基板32通过该焊球33与外部电路相互连接。
如图2所示，芯片10通过非导电胶或非导电薄膜30被固定在基板32的一侧上，而芯片20通过非导电胶或非导电薄膜30被固定在基板32的另一侧上。基板32用于支撑芯片10和芯片20。这样，芯片10和芯片20分别位于基板32的两侧。芯片10和芯片20分别通过金线34与基板32相互连接。在基板32形成有芯片10和20的两侧，将封装树脂注塑成模封树脂31来分别保护芯片10和金线34以及芯片20和金线34。在形成有芯片20的基板32一侧，在除了形成有模封树脂31之外的区域上形成焊球33。基板32通过焊球33与外部电路相互连接。可选择地，焊球33也可以形成在基板32的形成有芯片10的一侧上。焊球33的形成在基板32的哪一侧上可以由工艺设计人员进行设计。
在图1和图2所示的两种结构中，封装体的厚度由焊球厚度、模封树脂的厚度和基板的厚度决定。对于多芯片封装体，模封树脂的厚度极大地依赖于封装体中芯片的数量和厚度。因此，随着电子产业对于轻薄封装结构的需求，图1和图2所示的封装体在减小整体厚度方面存在技术上的困难。而且，对于高速处理的器件而言，图1和图2所示的封装体存在信号延迟的缺陷，严重影响器件间的互连性能。
                         发明内容
本发明的目的在于提供一种提高封装体集成度的多芯片封装体，该多芯片封装体通过在基板上设计一个窗口来提高封装体基板厚度的利用率，从而提高封装体的集成度。
本发明的另一目的在于提供一种保障高速器件性能的多芯片封装体，该封装体通过芯片间直接连接来减小芯片间的信号延迟。
为了实现上述目的，本发明提供了一种多芯片封装体，该多芯片封装体包括基板、多个芯片和有机树脂，其特征在于：所述基板至少具有一个窗口，所述多个芯片的至少一个芯片位于所述窗口内并与连接到所述窗口周围的基板的至少另一个芯片相连接。
在上述多芯片封装体中，基板和芯片之间利用有机导电胶或焊球进行连接。芯片之间利用有机导电胶、焊球、合金材料或各向异性导电膜进行连接。位于所述窗口内的芯片还与所述至少另一芯片垂直互连。所述垂直互连包含侧壁互连或芯片内通柱互连。
当所述多个芯片为三个芯片时，一个芯片位于所述窗口内，另外两个芯片分别在基板上下两侧与所述窗口周围的基板相连接，其中，位于所述窗口内的芯片与所述另外两个芯片之一垂直互连。。
优选地，位于窗口内的芯片的上表面与基板的上表面位于同一水平面上。有机树脂为底部填充胶。
                         附图说明
下面，通过参照附图对本发明的实施例进行详细地描述，本发明特点将会变得更加清楚，其中：
图1示出了多个芯片位于基板同一侧的现有多芯片封装体；
图2示出了多个芯片位于基板两侧的现有多芯片封装体；
图3是示出了根据本发明第一示例性实施例的多芯片封装体的剖视图；
图4是示出了根据本发明第二示例性实施例的多芯片封装体的剖视图；
图5是示出了图3中的多芯片封装体中的芯片111的背面的示意图；
图6是示出了图3中的多芯片封装体中的芯片110的上表面的示意图；
图7是示出了图3中的芯片110和芯片111互连的三维结构图；
图8是示出了图3中的基板的下表面的示意图；
图9示出了根据本发明第一示例性实施例的多芯片封装体的堆叠结构。
                       具体实施方式
以下，参照附图来详细说明本发明的实施例。
第一示例性实施例
图3是示出了根据本发明第一示例性实施例的多芯片封装体的剖视图。
芯片111通过焊点301被固定在芯片110上。焊点301的材料可为合金材料或各向异性导电胶，但不限于此。在完成芯片111与芯片110的固定之后，通过侧壁互连材料302将芯片111的背面111a上的焊盘区303(见图5)和芯片110的上表面上的焊盘区311(见图6)相互连接。侧壁互连材料302可为导电胶、电镀铜或导线板。
发明名称为“Semiconductor chip，chip stack package and manufacturemethod”的第6,849,802号美国专利公开了利用侧壁互连材料连接多个焊盘区的方法。在该公开中，利用导电粘合剂作为互连构件。将导电粘合剂沿着连接线的暴露于堆叠的芯片的侧表面的垂直列进行涂覆，从垂直列的端部一直涂覆到接触焊盘区，从而形成互连构件，用于连接多个芯片。在此不再详细描述该发明的具体公开内容。
在完成芯片111和芯片110的侧壁互连之后，芯片110通过凸点300与基板200的下表面相连接。同时，芯片111进入基板200的窗口201(见图8)中。优选地，芯片111的背面111a与基板200的上表面在同一水平面上。凸点300位于芯片110上的固定有芯片111的区域的外围区域中。另外，芯片112通过凸点300与基板200的上表面及芯片111的背面111a相互连接。
凸点300可以为有机导电胶或焊球。当凸点300为焊球时，芯片110和112与基板200和芯片111的连接可通过焊接的方法来实现。焊接的方法可为超声压焊或热压焊。另外，当凸点300为焊球时，芯片112通过倒装焊与芯片111和基板200连接。
在完成芯片110、111和112的连接之后，在芯片110、111和112的中间区域填充有机树脂400。有机树脂400可为底充胶。
在基板200的与芯片110和112连接的区域的外围区域上，形成有焊球304。如图3所示的根据本发明第一示例性实施例的封装体通过焊球304与外部电路连接。
图5是示出了图3中的多芯片封装体中的芯片111的背面111a的示意图。在芯片111的背面111a上，分布有至少一个焊盘区303。焊盘区303的分布与芯片112上的凸点300的分布相对应。每个焊盘区303利用金属线连接到芯片111的边缘。焊盘区303可为金属焊盘区。
图6是示出了图3中的多芯片封装体中的芯片110上表面的示意图。对应于芯片111，在芯片110的中心区域上分布着焊盘区311。更具体地讲，焊盘区311的分布对应于焊点301的分布。例如，焊盘区311可为金属焊盘区。另外，对应于基板200，在芯片110的两侧区域上分布着焊盘阵列310。具体地讲，焊盘阵列310的分布与凸点300的分布相对应。
图7是示出了图3中的芯片110和芯片111互连的三维结构图。侧壁互连材料302依附在芯片111的侧面，并分别与芯片111的背面111a上的焊盘区303和芯片110上表面110a上的焊盘区311相连接。三个芯片110、111和112通过垂直互连相互连接。
图8是示出了图3中的基板下表面的示意图。在基板200的中心区域处设置有窗口201，用于放置芯片111。可选择地，窗口201可位于基板200的一侧的区域中。为了更容易放置芯片111，窗口201的面积通常被设置得大于芯片111的面积。在基板200的窗口201两侧设置有焊盘阵列330。焊盘阵列330对应于芯片110上表面110a上的焊盘阵列310。在基板200的焊盘阵列330的外围，设置有焊球304的焊盘区320。焊盘区320用于将该封装体连接到外部电路。
图9示出了根据本发明第一示例性实施例的多芯片封装体的堆叠结构。基于图3所示的封装体的结构，在基板201、202、203和204的上表面上设置焊盘305。各个独立的封装体通过将焊球304连接到焊盘305来实现封装体的堆叠和互连。
第二示例性实施例
图4是示出了根据本发明第二示例性实施例的多芯片封装体的剖视图。除了芯片111连接到芯片110的方式与图3所示的第一示例性实施例中的连接方式不同之外，图4所示的根据本发明第二示例性实施例的多芯片封装体的结构与图3所示的根据本发明第一示例性实施例的多芯片封装体的结构相同。为了简洁，将省略对相同结构的重复描述。
在图4中，芯片111通过芯片内互连通柱306来实现芯片111的上下表面上的焊盘307的连通。芯片111通过凸点300被固定在芯片110上，以与芯片110互连。另外，凸点300可为有机导电胶或焊球。
本发明通过在基板上设置一个窗口来容纳芯片，充分提高了封装体厚度的利用率。因此，在同等厚度的情况下，可以提高封装体的集成度。
同时，通过芯片间的垂直互连，可以缩小芯片间互连延迟，有力保障了高速器件的性能。
另外，根据本发明的多芯片封装体还可以用于封装体的堆叠结构，从而大大提高器件的集成性能。
尽管本发明仅对三个芯片和带有一个窗口的基板的示例性实施例进行了说明，但是本发明还可以通过其它实施方式来实现。例如，所述多芯片封装体可具有基板和两个芯片，基板具有一个窗口，两个芯片之一位于基板的窗口中，另一芯片位于基板的上侧或下侧；所述多个芯片封装体可具有基板和四个芯片，基板具有一个窗口，四个芯片中两个芯片位于基板的窗口内，另外两个芯片分别位于基板的上侧和下侧；所述多个芯片封装体可具有基板和四个芯片，基板具有两个窗口，四个芯片中两个芯片分别位于基板的两个窗口内，另外两个芯片分别位于基板的上侧和下侧。
因此，本发明不限于上述实施例。在不脱离本发明范围的情况下，可以对本发明的实施例进行各种变形和修改。

Claims (7)

1.一种多芯片封装体，其特征在于所述多芯片封装体包括：
基板，所述基板至少具有一个窗口；
多个芯片，所述多个芯片中的至少一个芯片位于所述窗口内，所述多个芯片中的其它芯片位于所述基板的上侧和下侧，并且所述至少一个芯片与连接到所述窗口周围基板上的所述其它芯片中的至少另一芯片相连接；
有机树脂，填充在所述多个芯片和所述基板之间。
2.根据权利要求1所述的多芯片封装体，其特征在于所述基板和芯片之间利用有机导电胶或焊球进行连接。
3.根据权利要求1所述的多芯片封装体，其特征在于所述芯片之间利用有机导电胶、焊球、合金材料或各向异性导电膜进行连接。
4.根据权利要求1所述的多芯片封装体，其特征在于位于所述窗口内的所述至少一个芯片还与所述其它芯片中的所述至少另一芯片垂直互连。
5.根据权利要求4所述的多芯片封装体，其特征在于所述垂直互连包含侧壁互连或芯片内通柱互连。
6.根据权利要求1至权利要求5中的任意一项所述的多芯片封装体，其特征在于当所述多个芯片为三个芯片时，一个芯片位于所述窗口内，另外两个芯片分别在基板上下两侧与所述窗口周围的基板相连接，其中，位于所述窗口内的芯片至少与所述另外两个芯片之一垂直互连。
7.根据权利要求1至权利要求5中的任意一项所述的多芯片封装体，其特征在于位于所述窗口内的所述至少一个芯片的上表面与所述基板的上表面位于同一水平面上。
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CN102403308A (zh) * 2010-09-13 2012-04-04 上海新储集成电路有限公司 一种不对称多芯片系统级集成封装器件及其封装方法
CN102468277A (zh) * 2010-11-11 2012-05-23 三星半导体(中国)研究开发有限公司 多芯片层叠封装结构及其制造方法
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6486006B2 (en) * 1997-10-02 2002-11-26 Matsushita Electric Industrial Co., Ltd. Semiconductor chip bonded to a thermal conductive sheet having a filled through hole for electrical connection
CN1949468A (zh) * 2006-09-01 2007-04-18 中国航天时代电子公司第七七一研究所 一种三维多芯片模块互连及封装方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6486006B2 (en) * 1997-10-02 2002-11-26 Matsushita Electric Industrial Co., Ltd. Semiconductor chip bonded to a thermal conductive sheet having a filled through hole for electrical connection
CN1949468A (zh) * 2006-09-01 2007-04-18 中国航天时代电子公司第七七一研究所 一种三维多芯片模块互连及封装方法

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