CN102403308A - 一种不对称多芯片系统级集成封装器件及其封装方法 - Google Patents

一种不对称多芯片系统级集成封装器件及其封装方法 Download PDF

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CN102403308A
CN102403308A CN2010102794106A CN201010279410A CN102403308A CN 102403308 A CN102403308 A CN 102403308A CN 2010102794106 A CN2010102794106 A CN 2010102794106A CN 201010279410 A CN201010279410 A CN 201010279410A CN 102403308 A CN102403308 A CN 102403308A
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chip
pad
bottom chip
system level
asymmetric
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陈邦明
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Shanghai Xinchu Integrated Circuit Co Ltd
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Shanghai Xinchu Integrated Circuit Co Ltd
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Abstract

本发明公开了一种不对称多芯片系统级集成封装器件，包括顶部芯片、底部芯片、放置于底部芯片下方的基板、和连接线，所述顶部芯片的尺寸小于底部芯片的尺寸；底部芯片上设置有接线焊盘或焊料凸点；顶部芯片按焊盘面朝下方向放置，底部芯片按焊盘面朝上方向放置，底部芯片放置于基板之上，顶部芯片和底部芯片的焊盘面对面键合，底部芯片通过连接线和基板导通。本发明还公开了所述不对称多芯片系统级集成封装器件的封装方法。本发明成本较低，可实现高密度、高频率、低信号RC延迟的有益效果。

Description

一种不对称多芯片系统级集成封装器件及其封装方法
技术领域
本发明具体涉及一种不对称多芯片系统级集成封装器件及其封装方法。
背景技术
虽然通过系统之间的标准逻辑制程及嵌入式动态随机存储器或嵌入式闪存或嵌入式射频或嵌入式传感器等流程的整合，可以实现高带宽互连以及低信号RC延迟的互连，快速提升掩模板计数，但是，低产量和晶圆厂高成本的几个参考因数使重新考虑封装的系统封装从2维向3维的高密度封装。从垂直堆叠晶圆层级到倒装的顶部芯片和底部晶片的芯片之间的封装。如嵌入式动态随机存储器，嵌入式闪存，嵌入式射频和嵌入式传感器等系统芯片的高成本，导致本技术领域的国际大厂家转向开发由穿透硅通道（TSV技术）垂直的芯片堆叠技术。但是，TSV技术的顶部芯片和底部芯片的尺寸大小非常接近，以至于没有足够的空间可供连接基板或主板。因此，用50～100um 硅刻蚀和铜电镀的TSV技术，因其开发制造成本较高，已成为中国3D系统封装初始阶段的主要障碍。
现有技术中的多芯片系统级集成封装器件，一种类型为顶部芯片与底部芯片通过焊盘由连接线导通，底部芯片再跟基板通过焊盘由连接线导通。此种结构成本低，但过长的连接线会造成RC延迟，每个封装器件布线密度较高，如图1(a)。另一种类型为顶部芯片与底部芯片尺寸接近，顶部芯片与底部芯片面对面接触，在顶部芯片内做穿透硅通道，链接顶部芯片和底部芯片的焊盘，并在顶部芯片表面形成锡球。此种穿透硅通道（TSV技术）通过最短的线路长度保证高密度的RC延迟布线，但TSV技术高宽比成本也较高，如图2。
本发明克服现有技术的上述缺陷，提供一种不对称多芯片系统级集成封装器件，使用高精密模具和晶圆及底胶设备和半导体晶圆厂的成熟工艺完成半导体制作，成本较低，可实现高密度、高频率、低信号RC延迟的有益效果。本发明提供创新性、带有自对准结构的电路设计，以实现远远超出现有芯片结合工具的对准能力。
发明内容
本发明提供一种不对称多芯片系统级集成封装器件，包括顶部芯片、底部芯片、放置于底部芯片下方的基板、和连接线，其特征在于，所述顶部芯片的尺寸小于底部芯片的尺寸；底部芯片上设置有接线焊盘或焊料凸点；顶部芯片按焊盘面朝下方向放置，底部芯片按焊盘面朝上方向放置，底部芯片放置于基板之上，顶部芯片和底部芯片的焊盘面对面键合，底部芯片通过连接线和基板导通。
本发明的所述封装器件可以通过在相邻封装器件之间设置间隔阻挡层进行多层叠加。
所述底部芯片设有引线访问焊盘，所述底部芯片的焊盘以接线连接到基板。
所述顶部芯片与底部芯片垂直焊盘跟焊盘链接。
在所述底部芯片焊盘之间纵向或横向设置小焊盘。
在所述顶部芯片和底部芯片的焊盘之间横向或纵向设置冗余修补焊盘，所述焊盘与所述冗余修补焊盘由修补金属层互连，所述冗余修补焊盘与所述修补金属层之间设有晶体管。
所述冗余修补焊盘与焊盘由修补金属层互连但互不干扰。顶部芯片的冗余修补焊盘和低部芯片的冗余修补焊盘结构相同。
在顶部芯片和底部芯片键合后，可能会有焊盘和焊盘接触失效的情况，因此，本发明在正常焊盘的附近设计冗余修补焊盘，是为了确保芯片键合后焊盘跟焊盘的接触有效。
对于顶部芯片和底部芯片的焊盘存在对准误差的情况，本发明在一块芯片的正常焊盘四周设计了小焊盘，每个小焊盘与焊盘间晶体管相连接。当顶部芯片焊盘键合底部芯片的位置发生偏移时，即有对准误差时，顶部焊盘接触到小焊盘，小焊盘的晶体管导通底部焊盘的位置相连。导致整个芯片的焊盘朝相同的方向偏置，小焊盘的电路偏向相同方向，让顶部芯片和底部芯片的焊盘接触面尽量地大。这些开关在顶部和底部晶片内来控制逻辑，基于测试以后的结果存放在嵌入式存储内。
本发明的不对称多芯片系统级集成封装器件，包括如下结构：具有顶小底大的的封装内系统芯片，底部芯片和顶部芯片的焊盘键合，每平方毫米的链接能达到10～10000link/mm2，然后通过低成本的导线连接基板。实现整体低垂直距离高密度配线低RC延迟。本发明中可以做到多叠层多芯片系统级集成。顶部芯片和底部芯片焊盘接触达到高的速度和垂直密度，多芯片之间由间隔层相连。本发明中，在底部芯片做引线可访问顶部芯片焊盘并方便连接到基板。
本发明在现有结构的基础上，结合两种结构各自的特点，用第一种结构中较低成本的连接线和第二种结构中最短的链接线路长度达到低成本高密度低信号RC延迟的解决方法。本发明提供一种非对称、低成本、顶小底大的封装内系统芯片。顶部芯片对底部芯片焊盘的垂直键合，焊盘对准精度高，底部芯片链接到基板，形成垂直互连的、顶部芯片与底部芯片不对称晶圆的集成工艺技术，实现高密度、高频率的各种解决方案的集成。本发明不但运用了低成本的导线压焊，每平方毫米垂直连接，最短的最低垂直距离，以及高密度布线使最低RC延迟相比单个芯片的横向接触。从而使多芯片封装后的集成电路的适用范围更加广阔。
本发明还提供一种不对称多芯片系统级集成封装器件的封装方法，在真空或半真空条件下，将所述顶部芯片与所述底部芯片键合连接，其特征在于，在接有等离子体发生器的环状内，所述顶部芯片与所述底部芯片接口接触，以所述顶部芯片外圆环小孔产生的高温电浆冲击并除去杂质，所述顶部芯片与所述底部芯片的焊盘接口键合连接。
本发明封装方法是在真空或半真空状态下进行。在底部芯片与顶部芯片焊盘键合过程中，上下芯片接口处会有杂质、氧化残留物等。顶部芯片在接有等离子体发生器的环状内，当顶部芯片与底部芯片接口接触时，顶部芯片外圆环小孔产生的高温电浆(25～400度)，可以冲击并除去杂质，完成顶部芯片与底部芯片焊盘接口键合。
在顶部芯片与底部芯片焊盘接口连接时产生对准误差的情况下，本发明的封装方法，还可以通过刻蚀1～20 um厚度的聚合物沟道并采用自对准全压铸模具沟槽，在晶圆表面形成聚合物沟槽；所述顶部芯片通过聚合物沟槽键合在所述底部芯片焊盘的正确位置；蚀刻掉聚合物材料开放连接线导通基板。
在顶部芯片与底部芯片焊盘接口链接产生失效链接的情况下，本发明的封装方法在焊盘周围布置冗余修补焊盘，冗余焊盘连接修补金属层。例如，修补金属层可用金属层4或金属层6制作。修补金属层和焊盘之间存在晶体管。顶部芯片和底部芯片焊盘结构相同。修补焊盘必须有好的成品率，可分布在中间纵向或横向。也可做多个修补焊盘连对应的修补金属层。
在顶部芯片与底部芯片焊盘接口连接时如果出现位置偏移的，即当顶部芯片的焊盘键合底部芯片位置发生偏移时，本发明的封装方法可以在焊盘四周分布小焊盘，每个小焊盘与焊盘间晶体管连接。顶部芯片焊盘接触小焊盘后，小焊盘的晶体管导通跟底部焊盘的位置连接。小焊盘的电路偏向相同方向，这些开关在顶部芯片和底部芯片内来控制逻辑，基于测试以后的结果存放在嵌入式存储内。
本发明的封装方法，进一步特征在于，所述键合是在设置附加晶圆键合机架构条件下进行，采用真空压焊吸头吸住所述顶部芯片使其发射在所述底部芯片上，所述顶部芯片在水平或垂直方向均不移动，控制所述晶圆在水平或垂直方向移动并对准精度。本发明的封装方法中，控制干涉仪精确测量所述晶圆移动位置，同时由步进马达控制晶圆在水平或垂直方向上下移动，使晶圆停在2??50毫米移动距离。运用晶圆探测机或光刻机的高精度测量定位和反馈控制板如xy干涉仪控制对准精度。控制晶片在正负5~2um之间移动或静止及指数移动晶圆对准精度。
与现有技术相比，本发明安装精度高，芯片到芯片垂直互相连接，芯片链接的晶片，开发和筛选高密度、高频率的垂直互连芯片集成工艺，将成为各种垂直互连芯片和不对称晶圆的集成工艺技术的解决方案。
附图说明
图1(a)、图2分别是现有技术的结构示意图。 
图3、图4分别是本发明不对称多芯片系统级集成封装器件的结构示意图。
图5是本发明封装器件的多叠层结构示意图。
图6是顶部芯片和底部芯片的键合的示意图。
图7(a)、图7(b)分别是本发明封装方法的焊盘失效时的修补示意图。
图8(a)到图8(f)分别是本发明封装方法的对准工艺的示意图。
图9(a)到图9(e)分别是本发明封装方法的实施对准设计示意图。
图10(a)是现有技术的封装系统平台结构示意图。
图10(b)是本发明的封装系统平台开发结构示意图。
具体实施方式
以下结合附图，详细说明本发明。
附图中：1焊盘，2基板，3底部芯片，4连接线，5压焊头，6顶部芯片，7穿透硅通道，8锡球，9间隔阻挡层，10芯片内金属线，11等离子发生器，12等离子出气孔环，13真空罩，14失效焊盘，15冗余修补焊盘，16冗余修补金属层，17晶体管，18聚合物，19小焊盘，20真空压焊吸头，21晶片移动平台。
图3、图4是本发明一个实施例的结构示意图。包括：焊盘1、如CU，基板、如PCB 2，底部芯片3，连接线4、如AL等，顶部芯片6，芯片内金属线10。通过顶部芯片与底部芯片面对面接触，顶部芯片与底部芯片的焊盘1压焊，底部芯片通过连接线4与基板 2连接。此种结构保留了低成本的连接线4压焊，且实现TVS技术中每平方毫米1000～10000垂直连接，正如最短的最低垂直距离高密度布线RC延迟。不同于TVS技术，此种结构对顶部芯片的厚薄没有要求，底部芯片尺寸要大于顶部芯片尺寸。图4中的芯片内金属线10可使顶部小芯片通过它访问接线焊盘以便连接到基板2。使用底部硅功能。本发明中，顶部芯片可由12寸晶片,为先进的低功耗，例如，低于1.5伏的90nm～16nmCMOS ，由 CPU+cache+high speed emMemory 提供；底部芯片可由8寸晶片, I/O或高功耗，例如，20V，5V,3V，2.5V的1um~90nm 混合信号技术，由ADC, PWM, I2C, SPI , power FET等提供。焊盘可以是铜或铝；基板是PCB；连接线可以是金线、铝线等。
图5是本发明另一个实施例的结构示意图。包括：焊盘1、如CU，基板、如PCB 2，底部芯片3，连接线4、如AL等，顶部芯片6，阻挡间隔层9。尺寸为顶小底大的芯片，可以做到多叠层多芯片系统级集成。非常高的速度与密度垂直铜跟铜链接，每平方毫米垂直密度连接1000～10000，垂直速度焊盘1的链接100M～1000M Hz，多芯片之间由阻挡间隔层9相连。不对称的顶小底大结构中，顶部芯片可由12寸晶片的45～16nm CPU + cache + high speed emMemory提供，底部芯片可由8寸晶片的500～90nm ADC, PWM, I2C, SPI , power FET等提供。
图6是本发明实施过程示意图。包括：焊盘1，底部芯片3，顶部芯片6，等离子体发生器11，等离子出气孔环12，真空罩13。在顶部芯片6和底部芯片3的焊盘1键合时，焊盘1表面有大量空气湿度氧化物或污染物残留，20～300度铜与铜键合或氧化物。这些都降影响接触电阻的大小和影响高频总线的速度。所以在焊盘1键合时有必要除去焊盘1表面的杂质，等离子发生器11连上等离子出气孔环12并吸住顶部芯片6，顶部芯片和底部芯片的焊盘1接触时等离子出气孔环12产生高温电浆，冲击杂质并使杂质除去，并完成顶部与底部芯片的焊盘1键合。
图7(a)、图7(b)是本发明失效修补示意图。包括：焊盘1，失效焊盘14，冗余修补焊盘15，冗余修补金属层16，晶体管17。顶部与底部芯片焊盘1接口连接会产生失效连接，如图7中失效焊盘14。在焊盘1周围布置冗余修补焊盘15，冗余修补焊盘15连接修补金属层16，修补金属层16可用其它金属层制作，例如，为了防止和其它已有金属层串扰，可以采用金属层4或6，或其他金属层。修补金属层16和基本焊盘1之间存在晶体管17。顶部芯片和低部芯片的焊盘结构相同。修补焊盘必须有好的成品率，可分布在中间纵向或横向。如图7(b)也可做多个修补焊盘15连相应的修补金属层16。冗余修补焊盘15均可以设置在顶部芯片和底部芯片上，如图7(a)、图7 (b)所示，每一行或列连接1至2个，每一个冗余修补焊盘15对应一条修补金属层。冗余修补焊盘设置过多，则要求芯片的尺寸更大。 
图8(a)到图8(f)是本发明实施对准工艺示意图。包括：焊盘1、如CU，基板 2，底部芯片3，连接线4、如AL等，顶部芯片6，聚合物18。现在低成本的芯片压焊机台对准值在+/-5um，不能提供高密度准确键合。但可通过刻蚀1-20 um深的聚合物18材料沟道并采用自对准全压铸模具沟槽，可在晶圆表面形成聚合物18沟槽材料，顶部芯片通过聚合物18沟槽键合底部芯片的正确位置后蚀刻掉聚合物18沟槽材料并开放焊线底部基板。提高顶部芯片6和底部芯片3的焊盘1压焊对准性。
图9(a)到图9(e)是本发明实施对准设计示意图。包括：焊盘1，晶体管17，小焊盘19。小焊盘19设置在焊盘1的四周位置，如图9（d）所示。小焊盘19可设置在顶部芯片或底部芯片，设置一个芯片上即可。，因为底部芯片的尺寸大于顶部芯片的尺寸，因此小焊盘19通常设置在底部芯片上。
如图9(a)所示当顶部芯片的焊盘1键合底部芯片位置发生偏移时，从上至下设计规则为1：相同焊盘1的尺寸大小和间距（典型的中密度和中速度），2：大尺寸的焊盘1/微小的间距（低密度和高速度），3：微小尺寸的焊盘1/大的间距（高密度和低速度）。图9(b)(c)在焊盘1四周分布小焊盘19，横向或纵向的排列。每个小焊盘19与焊盘1间晶体管17连接。顶部芯片的焊盘接触小焊盘19后，小焊盘19的晶体管导通跟底部芯片的焊盘的位置连接。小焊盘19的电路偏向相同方向。如图9(c)给了一个模块的设计规则（焊盘1的尺寸和间距）排列和连接区域（电阻）主要是在速度和密度之间，顶部芯片（全数字化，纯低电压）最先进的节点（90??20纳米）的内建自测试电路，还可以测试:1)垂直总线2)底部更大，高电压（很少数目的门电路）。通过打开右边的平行转移开关或者左边的平行转移开关以达到最高的内建自修复的垂直总线在实际阻抗最佳的选择：上不移动或者左移动或者右移动或者向上平行移动或者向下平行移动。如图9(d)(e)，给了一个模块的设计规则（焊盘1的尺寸和间距）排列和连接区域（电阻）主要是在速度和密度之间，可选的内建自测试/内建自修复仅仅需要打开两个字线上的开关，右下方或左上方平行帮助替换的焊盘1的字线。平行移动替代不好的列，连接的电阻高速度(>200MHZ)高密度(1K /mm2)。先进的MCHP技术应用在没有任何模拟信号的数字总线上，相变锁存器（可能是顶部或是底部芯片）可以确保高带宽通信的数据集成，即使在很坏的排列作为垂直链接高密度、高速度和平移为那些封装时对不准的接口。
图10(a)是已有封装系统平台结构示意图。包括：底部芯片3，顶部芯片6，真空罩13，真空压焊吸头20，晶片移动平台21。如图10(a)所示，传统的芯片粘接，芯片粘接不动晶圆，大范围的移动真空压焊吸头20，工具放置存在+/- 5um的误差，越过8寸晶圆的距离，高吞吐量每分钟100-300个芯片。缺少高精度测量和反馈控制板（如xy干涉仪）。如图10(b)所示，精密模具附加晶圆键合机架构：真空罩13内的真空压焊吸头20吸住顶部芯片一动不动，干涉仪可非常精确的测量晶圆运动 。停在晶圆2??50毫米移动距离（+/-5um之间精度）。运用晶圆探测机或光刻机的高精度测量定位和反馈控制板（xy干涉仪）。晶圆探针行业或光刻的视野工具能很好的控制晶片实现+/- 5~2um之间探针卡静止和指数移动晶圆对准精度。
以上结合附图描述了本发明的实施方式，实施例给出的结构并不构成对本发明的限制，本领域内熟练的技术人员在所附权利要求的范围内做出各种变形或修改均在保护范围内。

Claims (9)

1.一种不对称多芯片系统级集成封装器件，包括顶部芯片、底部芯片、放置于底部芯片下方的基板、和连接线，其特征在于，所述顶部芯片的尺寸小于底部芯片的尺寸；底部芯片上设置有接线焊盘或焊料凸点；顶部芯片按焊盘面朝下方向放置，底部芯片按焊盘面朝上方向放置，底部芯片放置于基板之上，顶部芯片和底部芯片的焊盘面对面键合，底部芯片通过连接线和基板导通。
2.根据权利要求1所述的不对称多芯片系统级集成封装器件，其特征在于，所述封装器件可以通过在相邻封装器件之间设置间隔阻挡层进行多层叠加。
3.根据权利要求1所述的不对称多芯片系统级集成封装器件，其特征在于，所述底部芯片设有引线访问焊盘，所述底部芯片的焊盘以接线连接到基板。
4.根据权利要求1所述的不对称多芯片系统级集成封装器件，其特征在于，所述顶部芯片与底部芯片垂直焊盘跟焊盘链接。
5.根据权利要求1所述的不对称多芯片系统级集成封装器件，其特征在于，在所述底部芯片焊盘四周纵向或横向设置小焊盘。
6.根据权利要求3所述的不对称多芯片系统级集成封装器件，其特征在于，在所述顶部芯片和底部芯片的焊盘四周横向或纵向设置冗余修补焊盘，所述焊盘与所述冗余修补焊盘由修补金属层互连，所述冗余修补焊盘与所述修补金属层之间设有晶体管。
7.如权利要求1所述不对称多芯片系统级集成封装器件的封装方法，在真空或半真空状态下，将所述顶部芯片与所述底部芯片的焊盘键合连接，其特征在于，在接有等离子体发生器的环状内，所述顶部芯片与所述底部芯片的焊盘接触，以所述顶部芯片外圆环小孔产生的高温电浆冲击并除去杂质，所述顶部芯片与所述底部芯片的焊盘键合连接。
8.如权利要求7所述不对称多芯片系统级集成封装器件的封装方法，其特征在于，还可以通过刻蚀1～20 um厚度的聚合物沟道并采用自对准全压铸模具沟槽，在晶圆表面形成聚合物沟槽；所述顶部芯片通过聚合物沟槽键合在所述底部芯片焊盘的正确位置；蚀刻掉聚合物材料开放连接线导通基板。
9.如权利要求7所述不对称多芯片系统级集成封装器件的封装方法，其进一步特征在于，所述键合是在设置附加晶圆键合机架构条件下进行，采用真空压焊吸头吸住所述顶部芯片使其发射在所述底部芯片上，所述顶部芯片在水平或垂直方向均不移动，控制所述晶圆在水平或垂直方向移动并对准精度。
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