TWI700753B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

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TWI700753B
TWI700753B TW108116669A TW108116669A TWI700753B TW I700753 B TWI700753 B TW I700753B TW 108116669 A TW108116669 A TW 108116669A TW 108116669 A TW108116669 A TW 108116669A TW I700753 B TWI700753 B TW I700753B
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layer
chip
molding compound
redistribution
redistribution layer
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TW108116669A
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TW201947679A (zh
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鄭家明
李柏漢
楊惟中
吳冠榮
張恕銘
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精材科技股份有限公司
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Abstract

本發明提供一種晶片封裝體。第一接合結構位於第一重佈線層上。第一晶片包括鄰近一主動面的一感測區及一導電墊。第一晶片透過第一接合結構接合於第一重佈線層上，且第一接合結構位於導電墊與第一重佈線層之間。模塑料層覆蓋第一重佈線層且環繞第一晶片。第二重佈線層位於模塑料層及第一晶片上，且第二重佈線層電性連接至第一重佈線層。第二晶片堆疊於第一晶片的非主動面上，且第二晶片透過第二重佈線層、第一重佈線層及第一接合結構電性連接至第一晶片。本發明亦提供一種晶片封裝體的製造方法。

Description

晶片封裝體及其製造方法
本發明係有關於一種半導體封裝技術，特別為有關於一種晶片封裝體及其製造方法。
晶片封裝製程是形成電子產品過程中之重要步驟。晶片封裝體除了將晶片保護於其中，使其免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路，例如晶片封裝體內具有導線以形成導電路徑。隨著電子產品逐漸朝向小型化發展，晶片封裝體的尺寸也逐漸縮小。
一般而言，晶片封裝體與其他電子元件(例如，各種積體電路晶片或各種被動元件)各自獨立地設置於電路板上，且間接地彼此電性連接。雖然目前已發展出系統級封裝(System in Package，SiP)的技術來縮小電子產品的尺寸，然而具有感測功能的晶片的感測面不能受到遮蔽，因此製作具有感測功能的系統級封裝的晶片封裝體是一大挑戰，進而導致電路板及所形成的電子產品的尺寸難以進一步縮小。
因此，有必要尋求一種新穎的晶片封裝體及其製造方法，其能夠解決或改善上述的問題。
本發明實施例係提供一種晶片封裝體，包括一第一重佈線層、一第一接合結構、一第一晶片、一模塑料層、一第二重佈線層及一第二晶片。第一接合結構位於第一重佈線層上。第一晶片包括鄰近主動面的一感測區及一導電墊。第一晶片透過第一接合結構接合於第一重佈線層上，且第一接合結構位於導電墊與第一重佈線層之間。模塑料層覆蓋第一重佈線層且環繞第一晶片。第二重佈線層位於模塑料層及第一晶片上，且第二重佈線層電性連接至第一重佈線層。第二晶片堆疊於第一晶片的非主動面上，且第二晶片透過第二重佈線層、第一重佈線層及第一接合結構電性連接至第一晶片。
本發明實施例係提供一種晶片封裝體的製造方法，包括形成一第一重佈線層。在第一重佈線層上形成一第一接合結構。透過第一接合結構將一第一晶片接合於第一重佈線層上。第一晶片包括鄰近主動面的一感測區及一導電墊，且第一接合結構位於導電墊與第一重佈線層之間。形成一模塑料層，以覆蓋第一重佈線層且環繞第一晶片。在模塑料層及第一晶片上形成一第二重佈線層。第二重佈線層電性連接至第一重佈線層。堆疊一第二晶片。第二晶片位於第一晶片的非主動面上，且第二晶片透過第二重佈線層、第一重佈線層及第一接合結構電性連接至第一晶片。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(optoelectronic devices)、微機電系統(Micro Electro Mechanical System，MEMS)、生物辨識元件(biometric device)、微流體系統(micro fluidic systems)、或利用熱、光線、電容及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package，WSP)製程對影像感測元件、發光二極體(light-emitting diodes，LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、指紋辨識器(fingerprint recognition device)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
以下所述實施例可能討論特定的內容，例如所述晶片封裝體及其製造方法係應用於影像感測技術，然而所屬技術領域中具有通常知識者閱讀所揭露內容可理解在其他實施例中可考慮其他各種應用，例如生物特徵感測技術。應注意的是，此處所討論的實施例可能未必敘述出可能存在於結構內的每一個部件，舉例來說，當部件的討論說明足以傳達實施例的各個樣態時可能將其從圖式中省略。再者，此處所討論的實施例可能未必敘述出每一個製造步驟，且可能以特定的進行順序討論晶片封裝體的製造方法，然而在其他實施例中，可以以任何合理的順序進行晶片封裝體的製造。
以下配合第1A至1J圖說明本發明一些實施例之晶片封裝體及其製造方法，其中第1A至1J圖係繪示出根據本發明一些實施例之晶片封裝體的製造方法的剖面示意圖。
請參照第1A圖，提供一蓋板100。在一些實施例中，蓋板100包括透光材料，例如蓋板100可包括玻璃、氮化鋁(AlN)或其他適合的透光材料。在一些其他實施例中，蓋板100可作為暫時性載板(carrier)，且將會在後續的製程中被移除，此時蓋板100可以包括透光或不透光的載板材料。在一些實施例中，蓋板100的形狀可為圓形或矩形，且蓋板100的尺寸並不受限，例如蓋板100可具有8吋或12吋的晶圓尺寸。
之後，在一些實施例中，在蓋板100上形成一間隔層(或稱作圍堰(dam))110，間隔層110具有多個開口115，如第1A圖所示。在一些實施例中，間隔層110大致上不吸收水氣。間隔層110可直接接觸蓋板100，且間隔層110可不具有黏性。在一些實施例中，可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)形成間隔層110。在一些實施例中，間隔層110可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂(polyimide)、苯環丁烯(butylcyclobutene，BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))或其他適合的絕緣材料。或者，間隔層110可包括光阻材料，且可透過曝光及顯影製程而圖案化，以形成開口115。
本發明的實施例具有許多變化。在一些其他實施例中，可以以一黏著層取代間隔層110。此黏著層不具有開口，且包括透光材料。
請參照第1B圖，在間隔層110上形成圖案化的一重佈線層120(也稱為第一重佈線層)。在一些實施例中，重佈線層120可包括鋁、銅、金、鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料(例如，氧化銦錫或氧化銦鋅)或其他適合的導電材料。在一些實施例中，可透過沉積製程(例如，塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，形成圖案化的重佈線層120。
接著，在重佈線層120上形成多個導電結構130，如第1B圖所示。在一些實施例中，導電結構130及間隔層110直接接觸重佈線層120，且一部分的重佈線層120夾置於導電結構130與間隔層110之間。
導電結構130可以包括導電柱、導電凸塊或其他適合的導電結構。在一些實施例中，導電結構130可包括銅、銅合金、鈦、鈦合金、前述之組合或其他適合的導電材料。在一些實施例中，可透過沉積製程(例如，電鍍製程、無電鍍製程或其他適合的製程)，在重佈線層120上形成導電結構130。舉例來說，可在間隔層110及重佈線層120上形成具有開口的一遮罩層 (未繪示)，此遮罩層可包括光阻材料。遮罩層的開口定義出導電結構130預定形成的位置。接著，進行沉積製程，以在遮罩層的開口內形成導電結構130。之後，將遮罩層去除。
請參照第1C圖，透過多個第一接合結構140，將一第一晶片150接合於重佈線層120上。第一接合結構140可以包括導電層、導電膏、導電膠、導電凸塊或其他適合的接合結構。在一些實施例中，第一接合結構140可包括錫、焊料、銀、前述之組合或其他適合的導電材料。在一些實施例中，第一接合結構140及導電結構130包括不同的材料，舉例來說，第一接合結構140包括錫，而導電結構130包括銅，然而本發明實施例並不限定於此。
在一些實施例中，在重佈線層120上形成第一接合結構140，且將第一晶片150以主動面朝向蓋板100的方式放置於第一接合結構140上，並進行回焊(reflow)製程，使得第一晶片150經由第一接合結構140連接到重佈線層120。在一些其他實施例中，在重佈線層120上塗佈第一接合結構140，且經由第一接合結構140將第一晶片150直接黏著於重佈線層120上。
在一些實施例中，第一接合結構140及間隔層110直接接觸重佈線層120，且一部分的重佈線層120夾置於第一接合結構140與間隔層110之間。在一些實施例中，如第1C圖所示，導電結構130的厚度(或高度)小於第一晶片150的厚度(或高度)，且導電結構130的厚度大於第一接合結構140的厚度。
在一些實施例中，第一晶片150具有感測影像或生物特徵的功能，例如第一晶片150為互補式金屬氧化物半導體(complementary metal-oxide-semiconductor，CMOS)影像感測 (CMOS image sensor，CIS)晶片、光學式指紋感測(fingerprint sensor，FPS)晶片、電容式指紋感測晶片或其他適用的感測晶片。
在一些實施例中，第一晶片150包括一基底160、一感測區165、一絕緣層170、多個導電墊180及一光學部件190，如第1C圖所示。感測區165、絕緣層170、導電墊180及光學部件190鄰近於第一晶片150的主動面，而第一晶片150的非主動面大致上等同於基底160的背表面。在一些其他實施例中，第一晶片150可不包括光學部件190。
在一些實施例中，基底160可為一矽基底或其他半導體基底。絕緣層170位於基底160的前表面上。一般而言，絕緣層170可由層間介電(interlayer dielectric，ILD)層、金屬間介電(inter-metal dielectric，IMD)層及覆蓋之鈍化(passivation)層組成。為簡化圖式，此處僅繪示出單層絕緣層170。在一些實施例中，絕緣層170可包括無機材料，例如氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合或其他適合的絕緣材料。
導電墊180位於絕緣層170內，且絕緣層170內的鈍化層具有露出導電墊180的開口。在一些實施例中，導電墊180可為單層導電層或具有多層之導電層結構。在一些實施例中，導電墊180透過位於絕緣層170內的內連線結構(未繪示)電性連接至感測區165。內連線結構可包括導線、導電介層窗(via)及導電插塞(contact)。
感測區165內包括一感測元件或其他適合的電子元件。在一些實施例中，感測區165內包括感光元件或其他適合的光電元件。在一些其他實施例中，感測區165內可包括感測生物特徵的元件(例如，一指紋辨識元件)、感測環境特徵的元件(例如，一溫度感測元件、一溼度感測元件、一壓力感測元件、一電容感測元件)或其他適合的感測元件。
光學部件190設置於絕緣層170上，且對應於感測區165。在一些實施例中，光學部件190可為微透鏡陣列、濾光層、前述之組合或其他適合的光學部件。在一些實施例中，間隔層110具有開口115(標示於第1A圖中)，在第一晶片150接合於重佈線層120上之後，間隔層110在第一晶片150的主動面與蓋板100之間圍繞出對應於感測區165的一空腔155(如第1C圖所示)，使得光學部件190可容納於空腔155內，並透過蓋板100保護光學部件190。
請參照第1D圖，在間隔層110及重佈線層120上形成一模塑料層200，模塑料層200環繞導電結構130及第一晶片150。模塑料層200也可稱為封膠層(encapsulating layer)。在一些實施例中，模塑料層200直接接觸間隔層110、重佈線層120、導電結構130及第一晶片150。在一些實施例中，模塑料層200包括模塑成型化合物，例如模塑料層200包括環氧化物(epoxy)、樹脂(resin)、可塑形聚合物(moldable polymer)或其他適合的材料。
在一些實施例中，模塑料層200為具延展性的固體，例如由模塑成型化合物所構成的膠片(tape)，可將此膠片貼合在間隔層110上，且包覆住重佈線層120、導電結構130及第一晶片150。在一些實施例中，可利用模具注入及固化模塑料層200。在一些實施例中，可塗佈大致上為液體的模塑料層200，並經由化學反應固化模塑料層200。在一些實施例，模塑料層200可為紫外光(ultraviolet，UV)固化或熱固化聚合物的膠體，並利用紫外光或熱將模塑料層200固化。
在一些實施例中，模塑料層200覆蓋導電結構130及第一晶片150的非主動面(亦即，基底160的背表面)。之後，對模塑料層200進行薄化製程，直到露出導電結構130，如第1E圖所示。薄化製程可包括研磨(polishing)製程、磨削(grinding)製程、銑削(milling)製程或其他適用的製程。在一些實施例中，導電結構130的厚度小於第一晶片150的厚度，因此在薄化模塑料層200的期間，第一晶片150也被薄化，以露出導電結構130。例如，從基底160的背表面薄化，減少基底160的厚度。
在一些其他實施例中，可能在接合第一晶片150之前先對基底160進行薄化製程，使得第一晶片150的厚度小於或大致上相同於導電結構130的厚度，結果在薄化模塑料層200的期間，第一晶片150並未被薄化。根據本發明一些實施例，在薄化模塑料層200的期間，同時對基底160進行薄化的步驟，能夠簡化製程及降低製造成本。
請參照第1F圖，在模塑料層200及第一晶片150的非主動面上形成一絕緣層210。在一些實施例中，絕緣層210可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。在一些實施例中，可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，形成絕緣層210。接著，可透過微影製程及蝕刻製程，在絕緣層210內形成多個開口215，開口215露出被模塑料層200環繞的導電結構130。
在一些實施例中，在進行上述薄化製程之後，第一晶片150、導電結構130及模塑料層200大致上共平面，且絕緣層210直接接觸第一晶片150的非主動面、導電結構130及模塑料層200。在一些其他實施例中，可能有一部分模塑料層200夾置於第一晶片150的非主動面與絕緣層210之間，將第一晶片150與絕緣層210分隔。
請參照第1G圖，在絕緣層210上形成圖案化的一重佈線層220(也稱為第二重佈線層)。重佈線層220填充絕緣層210的開口215，且經由開口215電性及物理性連接被模塑料層200環繞的導電結構130。在一些實施例中，一部分的重佈線層220重疊第一晶片150的感測區165。在一些實施例中，一部分的絕緣層210夾置於第一晶片150的非主動面與重佈線層220之間。
在一些實施例中，重佈線層220可包括鋁、銅、金、鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料(例如，氧化銦錫或氧化銦鋅)或其他適合的導電材料。在一些實施例中，可透過沉積製程(例如，塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，形成圖案化的重佈線層220。
請參照第1H圖，可透過沉積製程，在絕緣層210上形成一保護層230，以覆蓋重佈線層220。在一些實施例中，保護層230與絕緣層210直接接觸。在一些實施例中，保護層230可包括環氧樹脂、綠漆、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
接著，可透過微影製程及蝕刻製程，在保護層230內形成多個開口235及多個開口236，以露出一部分的重佈線層220。在一些實施例中，如第1H圖所示，開口235重疊於模塑料層200，而開口236重疊於第一晶片150。在一些實施例中，開口235的尺寸(例如，寬度)大於開口236的尺寸。
請參照第1I圖，在從開口235露出的重佈線層220上形成多個導電結構240，且導電結構240填滿開口235。導電結構240的底部被保護層230環繞，而導電結構240的頂部位於保護層230上方。導電結構240經由重佈線層220、導電結構130、重佈線層120及第一接合結構140電性連接到第一晶片150。
在一些實施例中，導電結構240為焊球、導電凸塊、導電柱或其他適合的導電結構。在一些實施例中，導電結構240可包括錫、鉛、銅、金、鎳、前述之組合或其他適合的導電材料。在一些實施例中，導電結構240及第一接合結構140可包括相同的材料，例如錫或其他適合的導電材料。在一些實施例中，可透過植球製程、網版印刷製程、電鍍製程或其他適合的製程，在重佈線層220上形成導電結構240，並進行回焊製程。
在形成導電結構240之後，將一第二晶片250接合於從開口236露出的重佈線層220上，使得第二晶片250堆疊在第一晶片150的非主動面上，如第1I圖所示。在一些實施例中，第二晶片250重疊於第一晶片150的感測區165。在一些實施例中，第二晶片250的厚度(或高度)小於導電結構240的厚度(或高度)，以利於導電結構240後續接合於其他元件(例如，電路板)上。
在一些實施例中，第一晶片150及第二晶片250皆為已知良好的晶片(known good die)。在一些實施例中，第一晶片150及第二晶片250具有不同的功能。在一些實施例中，第二晶片250不具有感測的功能，例如第二晶片250可包括特定應用積體電路(application-specific integrated circuit，ASIC)、訊號處理器(signal processor)或其他電子部件。
在一些實施例中，第二晶片250包括一基底260、一絕緣層270及多個導電墊280，如第1I圖所示。絕緣層270及導電墊280鄰近於第二晶片250的主動面，而第二晶片250的非主動面大致上等同於基底260的背表面。在一些實施例中，第二晶片250不包括感測區及光學部件。
在一些實施例中，基底260可為一矽基底或其他半導體基底。絕緣層270位於基底260的前表面上。一般而言，絕緣層270可由層間介電層、金屬間介電層及覆蓋之鈍化層組成。為簡化圖式，此處僅繪示出單層絕緣層270。在一些實施例中，絕緣層270可包括無機材料，例如氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合或其他適合的絕緣材料。
導電墊280位於絕緣層270內，且絕緣層270內的鈍化層具有露出導電墊280的開口。在一些實施例中，導電墊280可為單層導電層或具有多層之導電層結構。在一些實施例中，導電墊280電性連接至位於絕緣層170內的內連線結構(未繪示)。
如第1I圖所示，可透過多個第二接合結構290將第二晶片250接合於重佈線層220上，第二接合結構290填滿保護層230的開口236。在一些實施例中，第二接合結構290及導電結構240都位於重佈線層220上，因此第二接合結構290及導電結構240位於相同層位。第二接合結構290可以包括導電凸塊或其他適合的接合結構。在一些實施例中，第二接合結構290可包括錫、鉛、銅、金、鎳、前述之組合或其他適合的導電材料。在一些實施例中，可透過網版印刷製程、電鍍製程或其他適合的製程，形成第二接合結構290，並進行回焊製程。
請參照第1J圖，在一些實施例中，沿著切割道切割保護層230、絕緣層210、模塑料層200、間隔層110及蓋板100，以形成多個獨立的晶片封裝體300A。舉例來說，可使用切割刀具或雷射進行切割製程，其中使用雷射切割製程可以避免上下膜層發生位移。在一些其他實施例中，第一晶片150是電容式指紋感測晶片，且蓋板100僅為暫時性載板，因此形成的晶片封裝體300A不包括蓋板100及間隔層110。
在一些實施例中，每一個晶片封裝體300A包括不同功能的一個第一晶片150及一個第二晶片250，如第1J圖所示。然而，本發明實施例可以具有許多變化。在一些其他實施例中，多個第二晶片250堆疊於一個第一晶片150上。在一些其他實施例中，還有一個或一個以上的第三晶片255堆疊於一個第一晶片150上，其中第三晶片255的結構及設置方式可大致上相同或類似於第二晶片250的結構及設置方式。或者，第一晶片150、第二晶片250及第三晶片255可能各自具有不同的功能。
舉例來說，第2圖係繪示出根據本發明一些實施例之晶片封裝體的上視圖。為了清楚說明及簡化圖式，第2圖僅繪示出蓋板100、第一晶片150、感測區165、第二晶片250及第三晶片255。在一些實施例中，晶片封裝體包括一個第一晶片150，多個第二晶片250及多個第三晶片255堆疊於一個第一晶片150上，且第二晶片250及第三晶片255與第一晶片150的感測區165局部重疊。
在某些情況下，由於具有感測功能的晶片的感測面不能受到遮蔽，因此可能採用矽通孔電極(through-silicon via，TSV)的技術形成堆疊晶片之間的電性導通路徑。然而，矽通孔電極的技術涉及將矽基底接合在暫時性載板上，且對矽基底進行蝕刻製程，以在矽基底內形成露出導電結構的通孔。而且，矽通孔電極的技術也涉及在通孔內形成絕緣層，以將矽基底與後續形成的導電層電性隔離，且對絕緣層進行蝕刻製程，去除覆蓋住導電結構的絕緣層，使得後續形成的導電層能夠與露出的導電結構電性連接。之後，還需要移除暫時性載板。
根據本發明的上述實施例，可利用第一接合結構140、重佈線層120、模塑料層200中的導電結構130、重佈線層220及第二接合結構290，將第一晶片150及第二晶片250互相電性連接，而無須採用矽通孔電極的技術，特別是不需要對矽基底及通孔內的絕緣層進行蝕刻製程，也可以不需要接合暫時性載板及去除暫時性載板，因此能夠簡化製程步驟、減少製造時間且大幅降低製造成本。
第一晶片150與第二晶片250之間的電性導通路徑是經由第一晶片150外側的導電結構130，且導電結構130與第一晶片150之間具有厚度充足的模塑料層200，因此能夠減少或避免導電結構130與第一晶片150之間發生漏電流的問題。而且，模塑料層200包覆第一晶片150，能夠進一步增加晶片封裝體300A的結構強度。如此一來，在對晶片封裝體300A進行可靠度測試時，模塑料層200可保護第一晶片150。因此，晶片封裝體300A具有提升的裝置性能及可靠度。
再者，由於模塑料層200包覆第一晶片150，增加了結構強度，而不會產生破裂或其他結構上的問題，因此受到模塑料層200保護的第一晶片150的尺寸(例如，厚度)可以更進一步縮減。如此一來，晶片封裝體300A能夠具有更小的尺寸，後續接合的電路板及所形成的電子產品的尺寸也能夠進一步縮小。換句話說，可透過模塑料層200控制第一晶片150的尺寸，使得晶片封裝體300A的尺寸具有更高的設計彈性。
以下配合第3A至3J圖說明本發明一些實施例之晶片封裝體及其製造方法。第3A至3J圖係繪示出根據本發明一些實施例之晶片封裝體的製造方法的剖面示意圖，其中相同於第1A至1J圖中的部件係使用相同的標號並省略其說明。
請參照第3A圖，提供如第1A圖所示之結構，也就是說，在蓋板100上形成具有多個開口115的間隔層110。接著，透過與第1B圖相同或相似的步驟，在間隔層110上形成圖案化的重佈線層120，如第3B圖所示。然而，並未在第3B圖中的重佈線層120上形成第1B圖中的導電結構130。
請參照第3C圖，提供一晶圓310。晶圓310包括基底160、感測區165、絕緣層170、導電墊180及光學部件190，且基底160為半導體晶圓，以利進行晶圓級製程。接著，將多個第二晶片250接合至晶圓310上，如第3C圖所示。在一些實施例中，第二晶片250為已知良好的晶片。具體而言，第二晶片250的非主動面朝向晶圓310的非主動面，且可透過一黏著層320將第二晶片250的非主動面貼附至晶圓310的非主動面上，因此第3C圖中的第二晶片250與晶圓310並無電性連接。在一些實施例中，在接合第二晶片250之前，可對晶圓310進行薄化製程，例如從晶圓310的非主動面薄化基底160，以減少基底160的厚度。
在接合第二晶片250之後，可沿著切割道切割晶圓310的基底160及絕緣層170，以形成多個獨立的第一晶片150。每一個第一晶片150的非主動面上可堆疊一個或一個以上的第二晶片250，而第一晶片150與第二晶片250尚未電性連接。
請參照第3D圖，進行相同或相似於第1C圖的步驟，透過多個第一接合結構140，將堆疊的第二晶片250及第一晶片150接合於重佈線層120上。在一些實施例中，第一接合結構140夾置於重佈線層120與第一晶片150的導電墊180之間。在一些實施例中，第二晶片250的尺寸(例如，寬度)小於第一晶片150的尺寸，因此局部露出第一晶片150的非主動面，如第3D圖所示。
請參照第3E圖，進行相同或相似於第1D圖的步驟，在間隔層110及重佈線層120上形成模塑料層200。在一些實施例中，模塑料層200環繞第一晶片150、黏著層320及第二晶片250。在一些實施例中，模塑料層200覆蓋第二晶片250的主動面及鄰近主動面的導電墊280。在一些實施例中，模塑料層200直接接觸黏著層320及第一晶片150的非主動面。
請參照第3F圖，在模塑料層200內形成多個開口125(也稱為第一開口)，開口125局部露出重佈線層120。再者，在模塑料層200內形成局部露出第二晶片250的主動面的多個開口285(也稱為第二開口)，使得導電墊280從開口285露出。在一些實施例中，開口125的尺寸(例如，深度)大於開口285的尺寸。在一些實施例中，對模塑料層200進行雷射鑽孔製程，以形成開口125及開口285。開口125及開口285可在不同的雷射鑽孔製程中形成，且形成開口125及開口285的先後順序並無限定。
請參照第3G圖，在模塑料層200上形成圖案化的重佈線層220。重佈線層220從模塑料層200上延伸到模塑料層200的開口125內，且經由開口125電性及物理性連接重佈線層120。再者，重佈線層220延伸到模塑料層200的開口285內，且經由開口285電性及物理性連接第二晶片250的導電墊280。在一些實施例中，重佈線層220直接接觸模塑料層200。
請參照第3H圖，進行相同或相似於第1H圖的步驟，在模塑料層200上形成保護層230，以覆蓋重佈線層220。在一些實施例中，沒有絕緣層位於保護層230與模塑料層200之間，且保護層230與模塑料層200直接接觸。
在一些實施例中，重佈線層220及保護層230共同填滿開口285。在一些實施例中，保護層230僅局部填入開口125，使得重佈線層220及保護層230在開口125內圍繞出一孔洞126。如此一來，後續製程中遭遇熱循環(Thermal Cycle)時，孔洞126能夠作為保護層230與重佈線層220之間的緩衝，以降低由於熱膨脹係數不匹配所引發不必要的應力，且防止外界溫度或壓力劇烈變化時保護層230會過度拉扯重佈線層220，進而可避免重佈線層220剝離甚至斷路的問題。
接著，進行相同或相似於第1H圖的步驟，在保護層230內形成多個開口235，以露出一部分的重佈線層220，如第3H圖所示。之後，進行相同或相似於第1I圖的步驟，在開口235內及露出的重佈線層220上形成多個導電結構240，如第3I圖所示。導電結構240經由重佈線層220、重佈線層120及第一接合結構140電性連接到第一晶片150。
請參照第3J圖，進行相同或相似於第1J圖的步驟，沿著切割道切割保護層230、模塑料層200、間隔層110及蓋板100，以形成多個獨立的晶片封裝體300B。在一些其他實施例中，第一晶片150是指紋感測晶片，且蓋板100僅為暫時性載板，因此形成的晶片封裝體300B可不包括蓋板100及間隔層110。
晶片封裝體300B類似於晶片封裝體300A，每一個晶片封裝體300B包括不同功能的一個第一晶片150及一個第二晶片250，如第3J圖所示。然而，本發明實施例可以具有許多變化，晶片封裝體300B可包括不同功能的一個第一晶片150及多個第二晶片250。
第4A至4I圖係繪示出根據本發明一些實施例之晶片封裝體及其製造方法，其中第4A至4I圖係繪示出根據本發明的一些實施例之晶片封裝體製造方法剖面示意圖。其中，相同於第1A至1J圖或第3A至3J圖中的部件係使用相同的標號並省略其說明。
請參照第4A圖，提供一蓋板100。之後，在一些實施例中，在蓋板100上形成圖案化重佈線層（RDL）120（其也稱作第一重佈線層）。之後，在一些實施例中，在重佈線層120上形成第一接合結構140a。在一些實施例中，第一接合結構140a與重佈線層120直接接觸，並且重佈線層120的一部分夾設於第一接合結構140a與蓋板100之間。在一些實施例中，第一接合結構140a可相同或相似於第1B圖所示的導電結構130。舉例來說，第一接合結構140a包括柱體、凸塊或其他合適的導電結構。在一些實施例中，第一接合結構140a包括銅、銅合金、鈦、鈦合金，其組合或其他合適的材料。可使用相同或相似於形成第1B圖所示的導電結構130的方法在重佈線層120上形成第一接合結構140a。
之後，在一些實施例中，使用相同或相似於第1A圖的步驟在蓋板100上形成具有開口115的間隔層（或圍堰）110， 如第4B圖所示，使第一接合結構140a圍繞間隔層110。如第4B圖所示的間隔層110未如第1B圖所示形成在重佈線層120上。在一些實施例中，間隔層110與重佈線層120位於相同的層位。
請參照第4C圖，透過第一接合結構140a將第一晶片150接合至重佈線層120上，並透過間隔層110接合至蓋板100上。在一些實施例中，第一晶片150使用相同或相似於第1C圖的步驟將第一晶片150接合至重佈線層120及蓋板100上。在將第一晶片150接合至重佈線層120之後，在每個第一晶片150的主動表面與蓋板100之間形成一空腔155，且空腔155被對應的第一晶片150下方的間隔層110所圍繞。空腔155也對應於每個第一晶片150的感測區165，使得光學部件190位於對應的空腔155內且由蓋板100保護。
請參照第4D圖，使用相同或相似於第1D圖的步驟在蓋板100上形成模塑料層200。在一些實施例中，模塑料層200圍繞重佈線層120及第一晶片150。在一些實施例中，模塑料層200與間隔層110、重佈線層120、第一接合結構140a及第一晶片150直接接觸。 在一些實施例中，模塑料層200覆蓋每個第一晶片150的非主動表面（即，基底160的背表面）。
請參照第4E圖，透過相同或相似於第3F圖4的步驟在模塑料層200內形成開口125，其中開口125局部露出重佈線層120。之後，在一些實施例中，圖案化的重佈線層220（也稱作第二重佈線層）透過相同或相似於第3G圖所示的方式形成在模塑料層200上，如第4F圖所示。模塑料層200上的重佈線層220延伸至模塑料層200的開口125內，並透過開口125電性連接及物理連接至重佈線層120。在一些實施例中，重佈線層220與模塑料層200直接接觸。
請參照第4G圖，在模塑料層200上形成一保護層230，以覆蓋重佈線層220。接著，在保護層230內形成開口235及開口236，以露出部分的重佈線層220。在一些實施例中，使用相同或相似於第1H圖的步驟形成保護層230與開口235及開口236。如第4G圖所示，從上視角度來看，開口235可與模塑料層200重疊，且開口236可與第一晶片150重疊。在一些實施例中，開口235的尺寸（例如，寬度）大於開口236的尺寸（例如，寬度）。在一些實施例中，在保護層230及模塑料層200之間沒有絕緣層，且保護層230與模塑料層200直接接觸。
在一些實施例中，保護層230局部地填入開口125，而形成孔洞126，每個開口125內的重佈線層220及保護層230圍繞孔洞126，如第4G圖所示。
請參照第4H圖，進行相同或相似於第1I圖的步驟，使得第二晶片250透過第二接合結構290（其完全填滿開口236）接合至重佈線層220，且導電結構240形成在開口235內露出的重佈線層220上。
請參照第4I圖，使用相同或相似於第1J圖的步驟沿著切割道切割模塑料層200及蓋板100，以形成多個獨立的晶片封裝體300C。在一些其他實施例中，第一晶片150為指紋感測晶片，且蓋板100僅為暫時性載板。因此，形成的晶片封裝體300C不包括蓋板100及間隔層110。
晶片封裝體300C相似於晶片封裝體300A及300B，每一個晶片封裝體300C包括不同功能的一個第一晶片150及一個第二晶片250，如第4I圖所示。然而，本發明實施例可以具有許多變化，晶片封裝體300C可包括不同功能的一個第一晶片150及多個第二晶片250。
第5A至5H圖係繪示出根據本發明一些實施例之晶片封裝體及其製造方法，其中第5A至5H圖係繪示出根據本發明的一些實施例之晶片封裝體製造方法剖面示意圖。其中，相同於第1A至1J圖、第3A至3J圖、或第4A至4I圖中的部件係使用相同的標號並省略其說明。
請參照第5A圖，提供如第4C圖所示之結構。亦 即，在蓋板100上形成具有第一接合結構140a位於上方的圖案化重佈線層（RDL）120（其也稱作第一重佈線層）、具有多個開口115的間隔層110。接著，第一晶片150透過第一接合結構140接合至重佈線層120上，且透過間隔層110接合至蓋板100上。
請參照第5B圖，使用相同或相似於第3D圖的步驟，透過一黏著層320將第二晶片250a對應地接合到第一晶片150上。如此一來，每個第二晶片250a的非主動表面面向對應的第一晶片150的非主動表面，因此第二晶片250a並未電性連接晶圓310。第二晶片250a相似於第3C圖所示的第二晶片250。具體地，第二晶片250a包括一基底260、一絕緣層270及多個導電墊280。不同於第3C圖所示的第二晶片250，第二晶片250a還包括形成在對應的導電墊280上的至少一個第二接合結構290。在一些實施例中，第二接合結構290相同或相似於第一接合結構140a。或者，第二接合結構290相同或相似於第1C圖所示的第一接合結構140。
一或多個第二晶片250a可堆疊在每個第一晶片150的非主動表面上，其中第一晶片150尚未電性連接至第二晶片250a。 在一些實施例中，第二晶片250a的尺寸（例如，寬度）小於第一晶片150的尺寸（例如，寬度），因此露出局部的第一晶片150的非主動表面。
請參照第5C圖，使用相同或相似於第3E圖的步驟在蓋板100上形成一模塑料層200。在一些實施例中，模塑料層200圍繞第一晶片150、黏著層320及第二晶片250a。在一些實施例中，模塑料層200覆蓋第二晶片250a的主動表面及與主動表面相鄰的多個導電墊280。在一些實施例中，模塑料層200與黏著層320及每個第一晶片150的非主動表面（即，基板160的背表面）直接接觸。 在一些實施例中，模塑料層200與間隔層110、重佈線層120及第一接合結構140a直接接觸。
請參照第5D圖，在模塑料層200上進行一薄化製程，直至露出第二接合結構290。薄化製程可包括研磨製程、磨削製程、銑削製程或其他適用的製程。之後，使用相同或相似於第3F圖的步驟在模塑料層200內形成多個開口125，其中開口125局部露出重佈線層120。
之後，在一些實施例中，使用相同或相似於第3G圖的步驟在模塑料層200上形成一圖案化的重佈線層220，如第5E圖所示。模塑料層200上的重佈線層220延伸至模塑料層200內的開口125中，並透過開口125電性連接及物理連接至重佈線層120。在一些實施例中，重佈線層220直接接觸模塑料層200層及露出的第二接合結構290，使得重佈線層220電性連接至第二晶片250。
請參照第5F圖，在模塑料層200上形成一保護層230，以覆蓋重佈線層220。接著，在保護層230內形成多個開口235，以露出多個部分的重佈線層220。在一些實施例中，透過相同或相似於第1H圖的步驟形成保護層230及開口235。在一些實施例中，在保護層230與模塑料層200之間沒有絕緣層，且保護層230直接接觸模塑料層200。
在一些實施例中，保護層230局部填入開口125而形成孔洞126，孔洞126被每個開口125內的重佈線層220及保護層230圍繞，如第5F圖所示。之後，在一些實施例中，進行相同或相似於第1I圖的步驟，使得導電結構240形成在開口235內的露出的重佈線層220上，如第5G圖所示。導電結構240透過重佈線層220、重佈線層120及第一接合結構140a電性連接至第一晶片150。
請參照第5H圖，透過相同或相似於第1J圖的步驟沿著切割道切割保護層230、模塑料層200及蓋板100，以形成多個獨立的晶片封裝體300D。在一些其他實施例中，第一晶片150為指紋感測晶片，且蓋板100僅為暫時性載板。因此，形成的晶片封裝體300D不包括蓋板100及間隔層110。
晶片封裝體300D相似於晶片封裝體300A、300B及300C，每一個晶片封裝體300D包括不同功能的一個第一晶片150及一個第二晶片250，如第5H圖所示。然而，本發明實施例可以具有許多變化，晶片封裝體300D可包括不同功能的一個第一晶片150及多個第二晶片250。
晶片封裝體300B、300C及300D具有相同或類似於晶片封裝體300A的優點。詳細而言，可利用第一接合結構140、重佈線層120、形成於模塑料層200中及模塑料層200上的重佈線層220，將第一晶片150及第二晶片250互相電性連接，而無須採用矽通孔電極的技術，因此能夠簡化製程步驟、減少製造時間且大幅降低製造成本。
第一晶片150與第二晶片250之間的電性導通路徑是經由第一晶片150外側的重佈線層220，且重佈線層220與第一晶片150之間具有厚度充足的模塑料層200，因此能夠減少或避免漏電流。
而且，模塑料層200包覆第一晶片150及第二晶片250，能夠進一步增加晶片封裝體300B或300D的結構強度。如此一來，在對晶片封裝體300B進行可靠度測試時，模塑料層200可保護第一晶片150及第二晶片250。因此，晶片封裝體300B具有提升的裝置性能及可靠度。再者，由於透過模塑料層200包覆晶片封裝體300B或300D內的第一晶片150及第二晶片250，增加了結構強度，因此不會發生破裂或其他結構性問題。因此，受到模塑料層200保護的第一晶片150及第二晶片250的尺寸(例如，厚度)可以更進一步縮減。如此一來，晶片封裝體300B或300D能夠具有更小的尺寸，後續接合的電路板及所形成的電子產品的尺寸也能夠進一步縮小。換句話說，可透過模塑料層200控制第一晶片150及第二晶片250的尺寸，使得晶片封裝體300B或300D的尺寸具有更高的設計彈性。
另外，本發明實施例的晶片封裝體300A、晶片封裝體300B、晶片封裝體300C及晶片封裝體300D皆能夠根據實際需求封裝不同功能的晶片，且晶片的數量並無限制，可以配合所需的晶片數量及晶片尺寸適當選擇蓋板100的尺寸，以利於進行晶圓級的封裝製程，進而提升製造效率。
綜上所述，本發明的各種實施例採用晶片堆疊的技術製作具有多功能且小尺寸的感測晶片封裝體，並解決了採用矽通孔電極技術產生的問題，特別是能夠簡化製程及降低製造成本，更提升系統級封裝的晶片封裝體的裝置性能及可靠度。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施例。
100‧‧‧蓋板110‧‧‧間隔層115‧‧‧開口120‧‧‧重佈線層125‧‧‧開口126‧‧‧孔洞130‧‧‧導電結構140、140a‧‧‧第一接合結構150‧‧‧第一晶片155‧‧‧空腔160‧‧‧基底165‧‧‧感測區170‧‧‧絕緣層180‧‧‧導電墊190‧‧‧光學部件200‧‧‧模塑料層210‧‧‧絕緣層215‧‧‧開口220‧‧‧重佈線層230‧‧‧保護層235‧‧‧開口236‧‧‧開口240‧‧‧導電結構250、250a‧‧‧第二晶片255‧‧‧第三晶片260‧‧‧基底270‧‧‧絕緣層280‧‧‧導電墊285‧‧‧開口290‧‧‧第二接合結構300A、300B、300C、300D‧‧‧晶片封裝體310‧‧‧晶圓320‧‧‧黏著層
第1A至1J圖係繪示出根據本發明一些實施例之晶片封裝體的製造方法的剖面示意圖。 第2圖係繪示出根據本發明一些實施例之晶片封裝體的上視圖。 第3A至3J圖係繪示出根據本發明一些實施例之晶片封裝體的製造方法的剖面示意圖。 第4A至4I圖係繪示出根據本發明一些實施例之晶片封裝體的製造方法的剖面示意圖。 第5A至5H圖係繪示出根據本發明一些實施例之晶片封裝體的製造方法的剖面示意圖。
100‧‧‧蓋板
110‧‧‧間隔層
120‧‧‧重佈線層
130‧‧‧導電結構
140‧‧‧第一接合結構
150‧‧‧第一晶片
155‧‧‧空腔
160‧‧‧基底
165‧‧‧感測區
170‧‧‧絕緣層
180‧‧‧導電墊
190‧‧‧光學部件
200‧‧‧模塑料層
210‧‧‧絕緣層
220‧‧‧重佈線層
230‧‧‧保護層
240‧‧‧導電結構
250‧‧‧第二晶片
260‧‧‧基底
270‧‧‧絕緣層
280‧‧‧導電墊
290‧‧‧第二接合結構
300A‧‧‧晶片封裝體

Claims (38)

  1. 一種晶片封裝體，包括：一第一重佈線層；一第一接合結構，其中該第一接合結構位於該第一重佈線層上；一第一晶片，其中該第一晶片包括鄰近一主動面的一感測區及一導電墊，且其中該第一晶片透過該第一接合結構接合於該第一重佈線層上，且該第一接合結構位於該導電墊與該第一重佈線層之間；一模塑料層，其中該模塑料層覆蓋該第一重佈線層且環繞該第一晶片；一第二重佈線層，其中該第二重佈線層位於該模塑料層及該第一晶片上，且該第二重佈線層電性連接至該第一重佈線層；一第二晶片，其中該第二晶片堆疊於該第一晶片的一非主動面上，且該第二晶片透過該第二重佈線層、該第一重佈線層及該第一接合結構電性連接至該第一晶片；以及一導電結構，其中該導電結構位於該第一重佈線層上且被該模塑料層環繞，且其中位於該模塑料層上的該第二重佈線層透過該導電結構電性連接至被該模塑料層覆蓋的該第一重佈線層，且該導電結構與該第一接合結構包括不同的材料。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該第一晶片具有感測影像或生物特徵的功能，且該第二晶片不具有感測的功能。
  3. 如申請專利範圍第1項所述之晶片封裝體，更包括：一蓋板，其中該蓋板包括一透光材料，且其中該第一晶片的該主 動面朝向該蓋板，且該第一重佈線層及該第一接合結構位於該蓋板與該第一晶片的該主動面之間。
  4. 如申請專利範圍第3項所述之晶片封裝體，更包括：一間隔層，其中該間隔層位於該蓋板與該第一重佈線層之間，且該間隔層在該第一晶片的該主動面與該蓋板之間圍繞出對應於該感測區的一空腔，且其中該第一晶片更包括位於該主動面的一光學部件，且該光學部件對應於該空腔。
  5. 如申請專利範圍第3項所述之晶片封裝體，更包括：一間隔層，其中該第一重佈線層位於該間隔層與該第一接合結構之間，且該間隔層接觸該蓋板、該模塑料層及該第一重佈線層。
  6. 如申請專利範圍第3項所述之晶片封裝體，更包括：一間隔層，其中該間隔層位於該蓋板上及該第一晶片下方，且被該第一接合結構圍繞，該間隔層在該第一晶片的該主動面與該蓋板之間圍繞出對應於該感測區的一空腔，且其中該第一晶片更包括位於該主動面的一光學部件，且該光學部件對應於該空腔。
  7. 如申請專利範圍第1項所述之晶片封裝體，更包括：一保護層，其中該保護層位於該模塑料層及該第一晶片的該非主動面上，且該保護層覆蓋該第二重佈線層；以及複數導電結構，其中該等導電結構位於該第二重佈線層上，且該保護層局部環繞該等導電結構。
  8. 如申請專利範圍第7項所述之晶片封裝體，更包括：一第二接合結構，其中該第二晶片透過該第二接合結構接合於該第二重佈線層上，且其中該保護層環繞該第二接合結構及該等導電結構。
  9. 如申請專利範圍第8項所述之晶片封裝體，其中該第二接合結構與該等導電結構位於相同層位，且其中該第二晶片的厚度小於該等導電結構的厚度。
  10. 如申請專利範圍第7項所述之晶片封裝體，其中該第二晶片包括一第二接合結構，其中該第二晶片透過該第二接合結構電性連接於該第二重佈線層上，且其中該模塑料層圍繞該第二接合結構，而該保護層圍繞該等導電結構。
  11. 如申請專利範圍第7項所述之晶片封裝體，其中該模塑料層環繞該第一晶片及該第二晶片，且其中該保護層及該等導電結構位於該模塑料層、該第一晶片及該第二晶片上。
  12. 如申請專利範圍第7項所述之晶片封裝體，其中該保護層及該第二重佈線層從該模塑料層上延伸至該模塑料層中，且其中該保護層及該第二重佈線層在該模塑料層內圍繞出一孔洞。
  13. 如申請專利範圍第1項所述之晶片封裝體，其中該第二晶片的寬度小於該第一晶片的寬度。
  14. 如申請專利範圍第1項所述之晶片封裝體，更包括：一絕緣層，其中該絕緣層位於該模塑料層上及該第一晶片與該第二晶片之間，且其中該絕緣層夾置於該第一晶片的該非主動面與該第二重佈線層之間。
  15. 如申請專利範圍第1項所述之晶片封裝體，更包括：一黏著層，其中該黏著層將該第二晶片貼附於該第一晶片的該非主動面，且其中該模塑料層還環繞該第二晶片及該黏著層。
  16. 如申請專利範圍第1項所述之晶片封裝體，更包括：一第三晶片，其中該第二晶片及該第三晶片堆疊於該第一晶片的 該非主動面上且重疊該第一晶片的該感測區。
  17. 一種晶片封裝體的製造方法，包括：形成一第一重佈線層；在該第一重佈線層上形成一第一接合結構；透過該第一接合結構將一第一晶片接合於該第一重佈線層上，其中該第一晶片包括鄰近一主動面的一感測區及一導電墊，且該第一接合結構位於該導電墊與該第一重佈線層之間；形成一模塑料層，以覆蓋該第一重佈線層且環繞該第一晶片；在該模塑料層及該第一晶片上形成一第二重佈線層，其中該第二重佈線層電性連接至該第一重佈線層；堆疊一第二晶片，其中該第二晶片位於該第一晶片的一非主動面上，且該第二晶片透過該第二重佈線層、該第一重佈線層及該第一接合結構電性連接至該第一晶片；形成一保護層，其中該保護層位於該模塑料層及該第一晶片的該非主動面上，且該保護層覆蓋該第二重佈線層；以及形成複數導電結構，其中該等導電結構位於該第二重佈線層上，且該保護層局部環繞該等導電結構。
  18. 如申請專利範圍第17項所述之晶片封裝體的製造方法，更包括：提供一蓋板；以及在該蓋板上形成一間隔層，其中在接合該第一晶片之前，在該間隔層上形成該第一重佈線層。
  19. 如申請專利範圍第18項所述之晶片封裝體的製造方法，其中在接合該第一晶片之前，在該間隔層上形成該第一重佈線 層。
  20. 如申請專利範圍第18項所述之晶片封裝體的製造方法，其中該第一接合結構圍繞該間隔層。
  21. 如申請專利範圍第18項所述之晶片封裝體的製造方法，更包括：形成露出該第二重佈線層的複數開口於該保護層，其中該等導電結構係形成於該保護層的該等開口內，且該等導電結構電性連接至該第二重佈線層；以及切割該保護層、該模塑料層、該間隔層及該蓋板，以形成該晶片封裝體。
  22. 如申請專利範圍第21項所述之晶片封裝體的製造方法，其中在形成該等導電結構之後，進行一回焊製程，以透過一第二接合結構將該第二晶片接合於該第二重佈線層上。
  23. 如申請專利範圍第21項所述之晶片封裝體的製造方法，其中該第二晶片包括一第二接合結構，其中透過該第二接合結構將該第二晶片電性連接於該第二重佈線層。
  24. 如申請專利範圍第23項所述之晶片封裝體的製造方法，更包括：在該模塑料層內形成露出該第一重佈線層的一第一開口。
  25. 如申請專利範圍第24項所述之晶片封裝體的製造方法，其中對該模塑料層進行一雷射鑽孔製程，以形成該第一開口。
  26. 如申請專利範圍第24項所述之晶片封裝體的製造方法，其中該第二重佈線層接觸該模塑料層及該第一重佈線層。
  27. 如申請專利範圍第24項所述之晶片封裝體的製造方 法，更包括：在該模塑料層、該第二晶片及該第一晶片上形成一保護層，以覆蓋該第二重佈線層，其中該保護層從該模塑料層上延伸至該第一開口內，且該保護層與該第二重佈線層在該第一開口內圍繞出一孔洞。
  28. 如申請專利範圍第17項所述之晶片封裝體的製造方法，其中在形成該模塑料層之前，對該第一接合結構進行一回焊製程，將該第一晶片接合於該第一重佈線層上。
  29. 如申請專利範圍第17項所述之晶片封裝體的製造方法，更包括：在接合該第一晶片及形成該模塑料層之前，在該第一重佈線層上形成一導電結構，使得在接合該第一晶片及形成該模塑料層之後，該模塑料層環繞該導電結構及該第一晶片；以及薄化該模塑料層，直到露出該導電結構。
  30. 如申請專利範圍第29項所述之晶片封裝體的製造方法，其中該導電結構的厚度小於該第一晶片的厚度且大於該第一接合結構的厚度，且其中在薄化該模塑料層的期間，從該非主動面薄化該第一晶片。
  31. 如申請專利範圍第29項所述之晶片封裝體的製造方法，更包括：在堆疊該第二晶片之前，在該模塑料層及該第一晶片的該非主動面上形成一絕緣層，其中該絕緣層具有露出該導電結構的一開口，且其中該第二重佈線層形成於該絕緣層上且延伸至該開口內，以透過該導電結構電性連接至該第一重佈線層。
  32. 如申請專利範圍第17項所述之晶片封裝體的製造方法，更包括：提供一晶圓，其中該第二晶片堆疊於該晶圓上；以及將該晶圓切割成該第一晶片，其中在形成該模塑料層之前，該第二晶片堆疊於該第一晶片的該非主動面上。
  33. 如申請專利範圍第32項所述之晶片封裝體的製造方法，其中該第二晶片透過一黏著層貼附於該晶圓上，且其中該模塑料層環繞該黏著層、該第一晶片及該第二晶片。
  34. 如申請專利範圍第33項所述之晶片封裝體的製造方法，更包括：在該模塑料層內形成露出該第一重佈線層的一第一開口；以及在該模塑料層內形成露出該第二晶片的一第二開口，其中該第二重佈線層從該模塑料層上延伸至該第一開口及該第二開口內，以電性連接該第一重佈線層及該第二晶片。
  35. 如申請專利範圍第34項所述之晶片封裝體的製造方法，其中對該模塑料層進行一雷射鑽孔製程，以形成該第一開口及該第二開口。
  36. 如申請專利範圍第34項所述之晶片封裝體的製造方法，其中該第二重佈線層接觸該模塑料層及該第一重佈線層。
  37. 如申請專利範圍第34項所述之晶片封裝體的製造方法，更包括：在該模塑料層、該第二晶片及該第一晶片上形成一保護層，以覆蓋該第二重佈線層，其中該保護層從該模塑料層上延伸至該第一開口及該第二開口內，且該保護層與該第二重佈線層在該第一開口內 圍繞出一孔洞，且其中該保護層與該第二重佈線層共同填滿該第二開口。
  38. 如申請專利範圍第32項所述之晶片封裝體的製造方法，其中該第二晶片的一非主動面朝向該第一晶片的該非主動面，且其中該模塑料層覆蓋該第二晶片的一主動面。
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