TW200847418A - CMOS image sensor chip scale package with die receiving opening and method of the same - Google Patents

CMOS image sensor chip scale package with die receiving opening and method of the same Download PDF

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Publication number
TW200847418A
TW200847418A TW097119577A TW97119577A TW200847418A TW 200847418 A TW200847418 A TW 200847418A TW 097119577 A TW097119577 A TW 097119577A TW 97119577 A TW97119577 A TW 97119577A TW 200847418 A TW200847418 A TW 200847418A
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TW
Taiwan
Prior art keywords
die
image sensor
substrate
contact
pad
Prior art date
Application number
TW097119577A
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English (en)
Inventor
Wen-Kun Yang
Jui-Hsien Chang
Hsien-Wen Hsu
Diann-Fang Lin
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Advanced Chip Eng Tech Inc
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Publication date
Application filed by Advanced Chip Eng Tech Inc filed Critical Advanced Chip Eng Tech Inc
Publication of TW200847418A publication Critical patent/TW200847418A/zh

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)

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200847418 九、發明說明： 【發明:斤屬之技術領域】 特別係 ί :::板級封裝(Panel leVel Pack— ; PLP)， 利於面板級封I。開孔之基板以容置影像感測器晶粒以 【先前技術】 小化技Γ快速發展’且半導體晶粒密度提昇以及微 r二=:!：因此對於如此高密度之封裝之封裝技術及 中，錫球陣列形成 /之狀怨。傳統之覆晶結構 傳欲之圖案。封裝功能包含散熱、訊號 荆罨，原刀配、保護等，者曰Η ®石〜a, 如導線架封裝、軟切壯w ㈣，傳統之封裝 尺寸晶片之需求。剛性封裝、無法滿足高密度小 再者，由於一般封裝技術必須 f 粒封裝技術與積體電路之發展右兹+ ^ :上技術對於電子元件之尺寸要求越來越； 、上述之理由，現今之封裝技 土 封一、覆晶球開陣列封裝、晶片尺寸向::用球：車列 :裝之技術。應可理解「晶圓級 指：：級 有封裝及交互連接結構，如同其他f程牛驟:曰曰圓上所 個別晶粒之前進行。一般而言，在:二古於切割為 裳製程之後’由具有複數半導體晶:之晶圓以 5 200847418 體封裝分離。上述晶圓級封裝具有極小之尺寸及良好之電 性。 乂晶圓級封裴（WLP)技術係為高級封裝技術，藉其晶粒 係於ΒΘ圓上加以製造及測試，且接著藉切割而分離以用於 在表面黏著生產線中組裝。因晶圓級封裝技術利用整個晶 圓作為目標’而非利用單一晶片或晶粒，因此於進行分離 私序之剷，封裝及測試皆已完成。此外，晶圓級封裝（WLp) 係如此之高級技術，因此線接合、晶粒黏著及底部填充之 程序可予以省略。藉利用晶圓級封裝技術，可減少成本及 製造時間且晶圓級封裝之最後結構尺寸可相當於晶粒大 小，故此技術可滿足電子裝置之微型化需求。 雖晶圓級封褒技術具有上述優點，然而仍存在一 級封裝技術之接受度之問題。例如，雖利用晶圓級 I#: =術可減少積體電路與互連基板間之熱膨脹係數 )不匹配，然而t元件尺寸縮小，晶 材料間之熱膨脹係數差昱變為另Μ + 4展、，，。構之 之_素。再者，於此 :==_塾係透過牵涉到重分舰 屬塾。焊錫球係直接炫接於金屬塾上，而金屬== 佈程序以區域陣列形式 糸用重刀 八蚀思产 式开/成。一般而s，所有經堆疊之重 刀佈層係形成於晶粒上之增層上。因此，封 加。討能與縮小晶片尺寸之需求相牴觸。、曰增 是以’本發明提出一種F0_WLP結構無須採上述之堆 6 200847418 疊增層以及RDL以降彻曰η +ώ ^ 牛低曰曰片之厗度，克服上述封裝問題以 及提供較佳性能、熱循環可靠度測試。 【發明内容】 r υ 本發明提供之封裝包含具有晶粒接收穿孔以及接觸穿 孔之基板，其中終端接觸墊形成於接觸穿孔之下，以及 觸塾形成於基板上表面。具微透鏡區域之晶粒係藉由黏膠 材料配置於晶粒接收穿孔内。厚介電層形成於上述晶粒主 動表面以及除微透鏡區域外之基板上表面。輸出入焊塾形 成於晶粒與基板上’用以電性連接之連接線係輕合至晶粒 之接合墊及基板之接㈣。核心、材質（e⑽ρ_)填充進入 晶粒邊緣、晶粒背部、穿孔側壁間之縫隙。透明罩利用黏 膠置於晶粒與介電層之上產生一空隙介於透鏡與透明罩之 間。導電凸塊選擇性耦合到終端墊。 本發明揭露一種製作影像感測器之方法，包含：提供 一基材，該基板具有晶粒穿孔以及接觸穿孔形成於豆中， 終端塾形成於該接觸穿孔之下側以及接觸塾配置於該基板 ，使用為對位檢放系統重分佈已知良好感測器晶 粒於了製具上；填充核心材質於該晶粒、晶粒穿孔側壁之 間’以及該晶粒背面；形成介電層於該晶粒以及該基板之 上’除該微透鏡區域、接合塾區域以及接觸墊區域；形成 接合導線於該晶粒與該基板之上，用以輕合該晶粒以及接 觸塾；接合透明罩於—面板上，其位於該介電層之上；自 終端金屬側切割該面板；延著切割道分離該透明罩以形成 封裝單體。其中更包製作保護層於該微透鏡區域以保護微 7 200847418 以及回流 透鏡以防粒子污染。更包含印刷錫膏於該終端塾 該錫膏以形成導電凸塊。 -種影像感測器模組’包含：軟性電路板，具有電路、 接觸墊、連接器形成其中；錫膏接合該連接墊以及基板終 端墊，其中該基板，具有晶粒穿孔以及接觸穿孔形成於其 中，終端塾形成於該接觸穿孔之下側以及接觸塾配置於該 基板之上表面；影像感測器晶粒，置於該晶粒穿孔中，其 「中該影像感測器晶粒具有微透鏡區域；介電層，形成於該 、晶粒以及該基板之上，除該微透鏡區域、接合塾區域以及 接觸墊區域；接合導線，形成於該晶粒與該基板之上，用 以耦合該晶粒以及接觸墊；核心材質，填充於該晶粒、晶 粒穿孔側壁之間，以及該晶粒背面；透明罩，配置於該晶 粒以及孩"電層之上，且產生一間隙位於該透明罩與該微 透鏡之間，及透鏡支樓架，固定於該軟性電路板上，使光 得以穿過該微透鏡。其中更包含被動元件焊於該軟性電路 I;板上。 其中更包含保護層形成於該微透鏡以避免 微粒污染。保護層材質包含二氧化矽、三氧化二 鋁或Π u 0 r 0 - Ρ 〇 1 y m e r，保護層具有防水、防油 特性。且最好具有01至〇·3微米之厚度及接近1 (空氣 反射係數）之反射係數。可以利用旋塗玻璃（SOG)技術予以 制作’且可以矽晶圓形式或面板形式進行。保護層之材料 可為二氧化矽、三氧化二鋁或氟聚合物。 基板材質包含環氧樹脂型FR5、FR4、ΒΤ、PCB、坡 8 200847418 璃、矽、陶莞、合金或金屬。Fe_Ni合金包含42%的沁 與58%的Fe。Fe_Ni_c〇合金包含以谓（2則％、、 54%Fe) 〇 保護層材質包含矽高分子為基礎之材質、高分子 (polyimide)為基礎之材質、矽膠、環氧樹脂、彈性材質或 感光材質。 ' 【實施方式】 ( 本發明某些類似之實施例將不詳細描述其細節。然 而，應理解者為本發明中所有之較佳實施例僅為例示之 用，亚非用以限制，因此除文中之較佳實施例外，本發明 亦可廣泛地應用在其他實施例中。不同元件之構成間並不 特別描述其尺寸，放大某些相關元件之維度並省略無意義 部分，以明白敘述並強調本發明之内容。 本發明揭露一種PLP採用具有預設晶粒穿孔以及接觸 (内連接）穿孔於基板，接觸金屬墊位於基板上方，終端接 觸墊位於基板下方，透過穿孔内金屬連接兩者。複數穿孔 穿過基板。接合導線連接連接形成影像感測器晶粒上之墊 以及預設之接觸金屬墊。 如第一圖所示為本發明CIS-CSP(CMOS Image Sensor-Chip Scale Package)截面圖。PLP封裝結構包含基 板2,其具有形成於其内之晶粒接收穿孔1〇以接收晶粒以 及接觸（内連）穿孔6。晶粒為影像感測晶粒。複數接觸穿孔 6自基板上側穿透至下側形成，其中接觸穿孔形成於四 周。V電材貝填充於上述接觸穿孔$中，以利於電性連絡。 9 200847418 於基板下方，且與接觸穿孔金屬連接， 其?於基板上側，且與接觸穿孔連接。⑽ 传連接底側’以利於與外部裝置接合。接合導線24 妾於金，及接合塾20之間，且因此透過接合墊 ϊ:曰二：電Ϊ連接。厚介電層38例如石夕高分子基礎材 夕卜=:除接合導線區域、微透鏡、接觸墊區域 曰卜：於r透明罩。核心材質―帅〇填充進入 脒署於曰η人間之縫隙。透明罩利用黏 =置於⑽與介電層之上產生—空隙介於透鏡與透明罩之 ^。=貫】施例中，介電層38包切高分子型、p_imide 環氧樹脂型、彈性材質、感光材質。具感光 s θ 8可藉由塗佈、印刷方法製作。 晶粒置於晶粒接收穿孔10内，以核心 re 卿Z Μ，最為保護日日日粒背部之材質。核心材質（撕e υ ::二可為化合物、環氧樹脂、石夕膠。晶粒穿孔之尺寸 /為 裰未。接觸墊20由電鍍方 核心材f 5G為彈性材質、感光材料、 衣乳树月曰、石夕膠填充進入晶粒邊緣、晶粒背部、穿孔側壁 =:?、阻障層32利用電鍍方式製作於= 核心材# 5〇 °金屬接合線24形成於晶粒16 接占過1/〇墊2〇、接觸塾22與晶粒16維持電性 =二形成内連接結構與終端墊8接觸。介電層％位於 、邛猎由微影製程以產生預設圖案(第三圖虛線所 不）。”可允許打開！ / 〇墊2 Q、接觸塾2 2以利於接合線以 200847418 及微透鏡區域。第三圖所示為本發明ClS_CSp之俯視圖， 透明遮罩36黏於介電層38以形成間隙與透明罩36與微透 鏡區域42之間。上述構成LGA(接觸墊位於封裝周邊）型 裝。 須注意，開孔46形成於晶粒16與保護層4〇之間，用 以曝露晶粒微透鏡區域42，以利於CMOS_CIS。保護声40 可以形成於微透鏡區域42之微透鏡上。保護層4〇係形成 於微透鏡上，微透鏡則係配置於晶粒16方。保護層4〇具 有防水防油特性以防止微透鏡受到粒子汙染，且最好具有 〇·1至〇·3微米之厚度及接近丨（空氣反射係數）之反射係 數。可以利用旋塗玻璃（S0G)技術予以制作，且可以矽晶 圓幵》式或面板形式進行。保護層4〇之材料可為二氧化石夕、 三氧化二銘或氟聚合物。 最後，具有IR過濾膜之透明罩36形成於微透鏡區域 42上用以保護微透鏡，其材質可為玻璃、石英等等。 另一實施利可參閱第二圖，導電凸塊3〇製作於接觸墊 8下方，此型式稱為BGA，以内連接接觸穿孔6，以半球 形位於切割道區域穿過基板。亦可形成於内連穿孔側壁區 域，其餘部分與第一圖相仿。因此，不再贅述。接觸穿孔 6位於切割道區域，因此切割後，每一個封裝具有半個接 觸穿孔6此可以提升錫接合品質以及減少所佔面積加 print)基板材貝可為具有預設開孔或導線之fm、 FR4、BT、PCB基板。具有高玻璃轉換溫度之基板如環氧 樹脂型FR5、BT。金屬合金基材之材質包含Fe_Ni合金包 11 200847418 含42卿與58%的Fe。μ。。 %、17%Co、54%Fe) ( 數可以被絲最為基板。基於低熱膨脹係 如第形如面板形式尺寸適合於導線接合機。 22以及、’接合線由晶粒向外扇出，與接觸墊 二：：曰連繫。與f知技術不同，習知技術具有 二二“二粒之上’也因此增加了封I之厚度。相反 η:1:Γ墊8位於晶粒墊相反之表面，訊號傳遞之 路徑係穿透基板藉由内連結構引導至終端# 8。因此可以 =著縮小本發明封裝之厚度。本發明之縣可以遠薄於先 則技術。此外，本發明基板暫封裝之前預先備置。晶粒穿 孔10以及接觸穿孔6預先㈣乍。因此，產能將大幅提升， 本發明揭露—種無堆疊積層位於接合線上之PLP。 製作面板式之CIS之步驟包含塗佈具有防水防油保護 Ο 曰，厚度約為G.1-G.3微米。然、後固化該保護層。保護層以 電聚（plasmaH虫刻或澄敍刻，以穿孔罩幕作為遮罩以形成 接合墊區域。晶圓隨後薄化’並分離晶粒，如藉由於切割 道上切割基板’以形成複數獨立單元。切割道位於定義於 每一待分離單元之間。 隨後，所欲之CIS晶粒以撿放裝置將晶粒挑選並置於 具有黏膠圖案之製具上。具有晶粒、接觸穿孔之基板隨後 黏合於製具之上。晶粒黏著材質如核心黏膠配置於介於晶 粒與穿孔側壁間縫隙，及晶粒背面。最後，“面板，，自製^ 上刀離。然後清理CIS晶片封裝之主動面。 12 200847418 佈妒：m厚介電層38形成於面板表面藉由印刷或塗 汽透：二二最佳為光感式以產生一區域用以曝露出 域。需注意者’厚介電層38環繞微透鏡區域用以 :路^透鏡區域46、接合塾20區域以及接觸塾22區 或 透明罩36可以保護微透鏡防止污染。 人接二—e H CIS封裝之步驟流程。本發明步驟包 2=工具(晶綱工具)91，其具有定位圖案位於 "”，W，®案膠（弹性黏著材質）印刷（塗佈）於製具91 上（用來黏合晶粒主動表面，未圖示）。隨後採用撿放微對
Lj 2工具具有接合功能时佈良好晶粒，具㈣當間距位於 衣具91上。圖案膠會將晶粒黏著於製具％上，隨後，且 有晶粒穿孔、接觸穿孔及接觸塾位於基板上側、終端塾ς 於基板下側之基板置於製具91上，如第四圖a。導電材質 填充於穿，以利電性聯繫。之後，具有微透鏡之晶粒％ 如：-、第二圖之晶粒隨後以圖案膠黏著於基板之晶粒接 收穿孔之上。核心材質95形成於晶粒與側壁間，盥晶粒背 =隨後將其固化，之後分離製具與面板。隨後步驟為清 潔晶粒表面與面板表面。以及熱接合於支撐載具卯上，如 第四圖b 後’塗佈厚介電層38以及使用曝光顯影製程 以開啟微透鏡區域46、接合區域20、以及接觸墊區域22， 參第三以及第四圖b。接合線然後形成以連接晶粒墊以及 基板之接觸塾，如第四圖c所示。CIS封裝之晶粒主動表 面隨後被清潔，之後，與面板尺寸相當具有切割道之玻璃 100接合於具有介電層38之面板，藉由對位與真空接合技 13 200847418 術。切割道以鑽石切割器切割。厚介電層38隨後固化以粘 合玻璃與面板。面板支撐載具以真空固化技術後自面板分 離0 自置放導電凸塊或錫膏塗佈於終端墊之後，執行回流 私序以回流基板侧以形成導体球（BG A形式），之後執行測 試。面板式最終測試採用垂直探針方式測試。測試後，面 板將備置於藍帶（blue tape)上並自終端金屬側切割面板， f 其只切割自基板底部切割基板。然後，自切割道將玻璃以 外力折裂以分離獨立單體，如第四圖e所示。然後，封裝 各自被撿放於托盤或捲帶上。 芩閱第五圖，所示為CIS封裝單體，以CIS-CSP製程 製作。晶粒包含CMOS或CCD影像感測器，其終端墊3〇 連藉由連接器124接至（表面黏著技術）軟性電路板12〇之 連接墊，以聯繫母板。CIS-CSP116為第一、第二圖之單體。 然後，透鏡12 8置於透明罩上使得光可以穿透。同時，微 1/透益兄可以形成於微透鏡區域，間隙形成於晶粒16與透明罩 36之間。透鏡支撐器126固定於印刷電路板12〇之上，以 支撐透鏡128。濾片130如IR濾光片固定於支撐器126之 上。同理，濾片可以為濾膜、形成於透明罩之上側或下側。 IR濾片包含二氧化鈦或光CATALYZER組成。透明罩％ 可以防止微透鏡污染。使用者可以採用液態或氣態去除污 染微粒而不傷及微透鏡。此外，被動元件122可以置於印 刷電路板120之上。 ' 本發明之優點包含： 14 200847418 基板預設穿孔以及電路’以利於形成超薄封裝，厚度 小於200微米（自感測器表面）。可作為應力釋放緩衝區域， 藉由填入矽膠、或液態化合材料以降低熱應力，其因介於 矽（CTE 2.3)與基板0尺5/；6丁一^丁£-16)間熱膨脹係數不匹 配所產生之問題。基於採用簡易製程，封裝產能得以提升·· 晶粒接合、導線接合、保護層以及切割。基於影像感測器 較少之接腳數。終端墊置於與主動面之反側，晶粒配置方 (法與目鈿製耘相谷，製程過程中無污染，基於具有一玻璃 罩配置於晶圓上。晶粒與基板之表面均等，本封裝可被清 潔，基於具有玻璃罩位於透鏡上。晶片尺寸尺寸約為每邊 Ο」^米，封裝之信賴度較傳統佳。特別是可以做板級溫 度循環測試，主要基於基板與PCB母板熱膨漲係數相當， 不會導致應力施加於球體。成本低廉且製程簡易。全程可 採自動化製程且採表面黏著技術。易製作混式封裝。[Μ 形式具有邊緣終端塾以利表面黏著。其具有高良率以及無 〇微粒污染、製程簡易以及全自動化製程。 對熟悉此領域技藝者，本發明雖以較佳實例闡明如 上’然其並非用以限定本發明之精神。在不脫離本發明之 精神與範圍内所作之修改與類似的配置，均應包含在下述 =申請專利範圍内’此範圍應覆蓋所有類似修改與類似結 構’且應做最寬廣的詮釋。 【圖式簡單說明】 為CIS-CSP影像感測器 第一圖根據本發明之實施例 之示意圖。 15 200847418 第二圖根據本發明之實施例’為CIS-CSP影像感測器 之不意圖。 第二圖根據本發明之實施例，為，為CIS-CSP影像感 測器之示意圖。 第四a至第四e圖根據本發明之實施例，為面板級封 裝製造方法之概要示意圖。 第五圖根據本發明之實施例，為CIS模組之示意圖。 【主要元件符號說明】 、f板2 ;接觸（内連）穿孔6 ;終端墊8 ;晶粒接收穿孔1〇 ; 曰曰粒16，接合墊20 ;接觸墊22 ;接合導線24 ;導電凸塊 3〇 ^阻卩早層32 ;透明遮罩36 ;介電層38 ;保護層40 ;微 透銳區域42 ;開孔46 ;核心材質50 ;支撐載具90 ;晶片 刀工具91 ;核心材質95 ;晶粒98 ;核心材質95 ;玻璃 1〇0 ’幸人性電路板120 ;連接器124 ;透鏡支撐器126 ;透 鏡 128 ;濾 >；13〇。 16

Claims (1)

  1. 200847418 十、申請專利範圍： 1 · 一種影像感測器，包含： 基材，具有晶粒穿孔以及接觸穿孔形成於其中，終端墊 形成於該接觸穿孔之下側以及接觸墊配置於該基板之 上表面；影像感測器晶粒，置於該晶粒穿孔中，其中該 影像感測器晶粒具有微透鏡區域；介電層，形成於該晶 粒以及該基板之上，並露出該微透鏡區域、接合墊區域 『 以及接觸塾區域，接合導線，形成於該晶粒與該基板之 上，用以耦合該晶粒以及接觸墊；核心材質，填充於該 晶粒與該晶粒穿孔側壁之間，以及該晶粒背面；及透明 罩，配置於該晶粒以及該介電層之上，且產生一間隙位 於該透明罩與該微透鏡之間。 2·如請求項第1項之影像感測器，其中更包含導電凸塊耦 合該終端墊。 U 3 ·如明求項第1項之影像感測器，其中該核心材質包含化 合物、環氧樹脂、或矽膠。 4·如請求項第1項之影像感測器，其中所述之介電層包含 夕南刀子為基礎之材質、高分子（P〇lyimide)為基礎之材 貝石夕膠、環氧樹脂、彈性材質或感光材質。 5·如明求項第1項之影像感測器，其中更包含阻障層形成 17 200847418 於該晶粒穿孔之側壁。 6.如請求項第5項之影像感測器，其中該阻障層包含金屬 層。 7·如請求項第1項之影像感測器，其中所述之接觸穿孔包 含半球形位於切割道之上或晶粒穿孔側壁區域。 8. 如請求項第1項之影像感測器，其中該基板材質包含環 氧樹脂型FR5、FR4。 9. 如請求項第1項之影像感測器，其中該基板材質包含 BT。 10. 如請求項第1項之影像感測器，其中該基板材質包含 PCB。 11·如請求項第1項之影像感測器，其中該基板材質包含玻 璃、矽或陶瓷。 12·如請求項第1項之影像感測器，其中該基板材質包含合 金或金屬。 13.如請求項第1項之影像感測器，其中更包含保護層形成 200847418 於該微透鏡區域以避免微粒污染。 14·^請求項第13項之影像感測器，其中該保護層材質包 含一氧化矽、三氧化二鋁或flu〇r〇_p〇lymer。 15·如請求項第13項之影像感測器，其中該保護層旦有防 水、防油特性。 … 16· —種製作影像感測器之方法，包含·· ,、土材置於一製具上，該基板具有晶粒穿孔以及接 觸穿孔形成於其中，終端墊形成於該接觸穿孔之下側以 2觸墊配置於該基板之上表面；使用為對位檢放系統 ：已知良好感測器晶粒於該製具上;填充核心材質 日日粒/日日粒牙孔側壁之間，以及該晶粒背面並分離 二:形成’丨電層於該晶粒以及該基板之上，並露出 ^區域、接合墊區域以及接觸墊區域；形成接合 藝·垃^粒與該基板之上，用以輕合該晶粒以及接觸 自終端：ϊ明罩Γ—面板上，其位於該介電層之上； 形成封ί單Γ相該面板；延著切割道分離該透明罩以 17·如請求項第16項 製作保護層於該捣、感測器之以^ 染。 、χ Λ透叙區域以保護微透鏡以防粒子污 19 200847418 18·如請求項第16項之形成影像感測器之方法，其中更包 έ印刷錫Τ於该終端墊以及加熱該錫膏以形成導電凸 塊0 19· 一種影像感測器模組，包含： 权f生電路板，具有電路、接觸墊、連接器形成其中； 錫膏接合該連接墊以及基板終端墊；其中該基板，具有 [日曰日：穿孔以及接觸穿孔形成於其中，終端墊形成於該接 觸穿孔之下侧以及接觸墊配置於該基板之上表面；影像 感測器晶粒，置於該晶粒穿孔中，其中該影像感測器晶 粒具有微透鏡區域；介電層，形成於該晶粒以及該基板 之上，亚露出該微透鏡區域、接合墊區域以及接觸墊區 域；接合導線，形成於該晶粒與該基板之上，用以麵合 f晶粒以及接觸墊；核心材質，填充於該晶粒與該錄 牙孔側壁之間’以及該晶粒背面；透明罩’配置於 ι粒以及該介電層之上，且產生_間隙位於該透明罩二; 微透鏡之間；及透鏡支撐架，固定於該軟性電路板上， 使光得以穿過該微透鏡。 其中更包含被動 2〇·如請求項第19項之影像感測器模組 元件焊於該軟性電路板上。 20
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US20080191335A1 (en) 2008-08-14
SG148133A1 (en) 2008-12-31

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