KR100248678B1 - 스택가능한 반도체 다중 칩 모듈 및 그 제조방법 - Google Patents

스택가능한 반도체 다중 칩 모듈 및 그 제조방법 Download PDF

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Publication number
KR100248678B1
KR100248678B1 KR1019930002486A KR930002486A KR100248678B1 KR 100248678 B1 KR100248678 B1 KR 100248678B1 KR 1019930002486 A KR1019930002486 A KR 1019930002486A KR 930002486 A KR930002486 A KR 930002486A KR 100248678 B1 KR100248678 B1 KR 100248678B1
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South Korea
Prior art keywords
carrying substrate
chip carrying
solder
substrate
semiconductor die
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KR1019930002486A
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English (en)
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KR930020616A (ko
Inventor
파울티.린
Original Assignee
비센트 비.인그라시아
모토로라 인코포레이티드
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Publication of KR930020616A publication Critical patent/KR930020616A/ko
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Publication of KR100248678B1 publication Critical patent/KR100248678B1/ko

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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Abstract

하나의 칩 운반체(42)를 땜납 접합부(29)로서 다른 칩 운반체(48)에 상호 접속시키는 스택가능한 3차원 다중 칩 모듈(MCM)(59)이 제조될 수 있다. 최상부 칩 운반체(42)는 기판(46)의 하부 표면에 땜납 콜(23)을 갖는다. 하부 칩 운반체(48)는 기판(52)의 최상부 표면상에 땜납 볼(16)을 그리고 하부 표면상에 땜납 볼(15)을 갖는다. 뚜껑(60)은 디바이스(50)를 밀봉하는데 사용될 수 있으며, 뚜껑 높이는 운반체 레벨간에 자연적인 양극 격리애자로서의 역할을 하여 접합부와 피로생명을 극대화시키는 낭고형 모양의 땜납 접합부(29)를 만든다. MCM의 열방출을 더욱 증가시키기 위한 열싱크는 스택에 의한 접근으로 용이하게 구현될 수 있다. 더군다나, 각각의 긴판이 다중 칩들을 운반할 수 있기 때문에 모듈은 3차원 성장과 동시에 2차원 칩 밀도의 설장을 일체화한다.

Description

스택가능한 반도체 다중 칩 모듈 및 그 제조 방법
제1도는 본 발명에 따라 납땜을 다시 유입(solder reflow)시키기전에 스택된 3차원 반도체 다중 칩 모듈(MCM)에 대한 단면도.
제2도는 본 발명의 실시예를 예시하는 것으로, 열싱크(heat sink)를 갖는 스택된 3차원 반도체 MCM에 대한 단면도.
제3도는 본 발명에 따른 3차원 반도체 MCM의 조립단계를 예시한 것으로, 기판의 하부표면에 납땜 범프를 구비하는 칩 운반용 기판상에 마운트된 반도체 디바이스의 단면도.
제4도는 본 발명에 따라 3차원 반도체 MCM의 조립 단계를 예시하는 것으로, 하부와 상부 기판표면모두에 납땜 범프를 구비하는 칩 운반용 기판상에 마운트된 반도체 디바이스의 단면도.
제5도는 본 발명의 실시예를 예시하는 스택된 3차원 반도체 MCM의 단면도.
제6도는 본 발명의 실시예를 예시하는 것으로, 하부의 반도체 디바이스에 걸쳐 뚜껑(a 11d)을 구비하는 스택된 3차원 반도체 다중 칩 모듈의 단면도.
* 도면의 주요부분에 대한 상세한 설명
25,8 : 스택가능한 반도체 다중 칩 모듈 10,18 : 반도체 다이
15 : 땜납 범프 16 : 땜납 패드
12,26,52 : 하부 칩 운반용 기판 60,28 : 뚜껑
20,30,46 : 상부 칩 운반용 기판 29 : 땜납 접합부
58 : 땜납 접합부 열
본 발명의 총체적으로 반도체 디바이스, 특히 스택 가능한(stackable) 3차원 반도체 다중칩 모듈에 관한 것이다.
현재 대부분의 대규모 집적 회로(IC)는 인쇄 회로(PC)기판에 납땜하거나 혹은 소켓(socket)에 삽입하기 위해 금속리드가 연장된 플라스틱 혹은 세라믹 패키지내에 패키지된다. 전형적으로, 상기 IC 패키지는 이중의 인 라인(dua1-in-1ine)또는 사중의 편평한(quad-flat) 패키지로서 구성된다. 대부분의 예에서, 비록 패키지안에 다중 칩이 포함되어 있을지라도, 단지 한개의 IC만이 패키지안에 포함된다. 세라믹 또는 플라스틱 패키지는 마운팅 표면, 특히 소켓이 사용된다면 보통 인쇄 회로기판의 비교적 넓은 영역을 차지하기 때문에, 상기 패키지화 기술의 결과로 인한 회로밀도는 그렇게 높지 않다.
더군다나, 어느 전자 분야에서와 같이 인쇄회로기판은 점점 작아지고, 보다 빨라지며 더욱 밀도가 높아져 가고 있다. 마운팅 영역이 한정되어 있거나 또는 속도를 고려할 때 회로소자들이 가까이 위치되어 있을 경우에 보다 조밀한 패키지 기술이 필요하다. 상기와 같은 한가지 기술은 동시에 소결되는 (cofired)세라믹 기판을 사용하여, 패키지되지 않은 채 IC가 세라믹 마운팅 표면에 직접 부착되어, 마운팅 표면위의 전도영역에 와이어 접착(wire bonded)되거나 또는, 예를 납땜 범프(a solder-bump)기술을 사용하여 세라믹 마운팅 표면위의 금속화 영역에 뒤집혀서(inverted) 직접 접속된다. 그러나, 상기와 같은 다중 칩 모듈(multiple chip module)(MCM)기술은 몇 가지 한계성이 있다. 다수의 ICI를 하나의 세라믹 다운팅 표면위에 상호 접속시키려면 크로스-오버(cross-overs)를 바람직하게 회피하는 패턴으로 금속 재료를 침전시키는 것을 필요로한다. 더군다나, 극히 미세한 금속전도체를 많은 표면위에 침전시키는 것은 어렵다. 다수의 층으로 된 상호 접속도 가능하지만, 때때로 비용이 매우 비싸며 공기냉각하에서는 열 방출이 제한된다. 직접 칩을 부착시키게 되면, 모듈을 조립하기 전에 소결(burn-in)력이 없는 부가적인 한계가 있으며, 기판을 마운팅한 후 복구하기가 어렵다.
게다가, 만약 회로에 능동이거나 혹은 수동인 구성소자가 필요하다면, 크기와 마운팅 기법이라는 문제가 수반되는 단속적인 구성 소자가 반드시 사용되어야 한다.
그럼에도 불구하고, MCM을 사용함으로서 IC를 패키지하는 데 두드러진 장점이 있는데, 그것은 칩 사이의 시간지연이 감소되고, 전기적 노이즈와 혼선이 줄어들었으며 크기가 감소하였다. 사용된 칩은 보다커지고, 다수의 칩 모듈마다 I/O리드 카운트(lead counts)가 크게 증가되고 있다. 그러나, 상기와 같은 여러가지 장점에도 불구하고, 현재의 MCM은 그 나름의 문제점이 있다. 즉, 열을 관리하는 문제가 커지게 된다. 다수의 디바이스로부터 발생된 열은 반드시 제거되어야만 한다. 게이트가 칩위에 한층 조밀하게 밀집해있을 수록 다이로부터 다이부착(die-attach), 기판 내지 열 싱크(heat sink)에 이르는 모든 열의 통로가 고려되어야만 한다. 단결정 실리콘 및 알루미늄 질화물과 실리콘 카바이드(silicon carbide)의 같이 높은 열의 전도성을 갖는 세라믹과 인홰회로기판재료보다 우수한 열전달력과 열 평준화 능력을 갖고 있다. 또한 온도의 단계적 변화(gradations)는 답땜, 와이어 본드 및 전기적 접속의 신뢰성에 큰 영향을 끼친다. 실제로, 바람직하게 MCM을 설계하기 위해서, 독립적으로 가장 효율적인 열전도성을 갖는 재료와 열 팽창계수가 비슷한 족(a group)과 같은 재료사이에 반드시 균형이 이루어져야 한다.
종래부터, 조립하기전에 모든 다이스가 개별적으로 검사되는 한편, 다음에 시스템이 고장날 위험을 최소화시키기 위해 가속된 노화상태(under accelerated aging conditions)에서 중요한 유니트(critical units)가 소결된다. 소결(Burn-in)은 취약한 디바이스들을 선별해내기 위해 수행되며, 몇개안되는 칩보다는 보통 패키지된 디바이스들이 소결된다. 소결을 하는데 있어서 발생하는 대부분의 실패는 약한 게이트 산화물로 인해 관련된 디바이스 또는 다이이다. MCM에 소결을 적용하려면, 상기 공정은 패키지된 모듈레벨에서 수행되어야만 한다. 모듈 레벨에서의 소결이 갖는 단점은, 모듈내 다이의 비율이 떨어지며, 적절한 제거절차로서 다른 우수한 다이로 교체가 이루어져야만 한다는 것이다.
MCM을 이용한 다른 해결책은, X-Y면이 아니라 Z-축을 따라 몇개안되는 칩을 상호 접속시키는 것이다. 3차원으로 패키지함으로서 2차원(planar)인 다수 칩 기판모다 높은 메모리 밀도와 보다 상호 접속밀도를 제공한다. 결과적으로, MCM, 개별소자 및 수동소자(discretes and passives)를 접속시키는 접속 시스템은 기판에 수직인 Z 방향으로 성장하게 될 것이다.
IC를 3차원으로 패키지함으로서 여러분야에서 장점이 있다. 예를들어, 속도와 조밀화가 중요시되는 슈퍼컴퓨터 메모리 또는 액세스 시간과 조밀화가 중요시되는 대규모 캐쉬 메모리에 유용할 수 있다.
몇개 안되는 칩을 상호 접속시키는 한가지 방법은 스택된 칩(stacked chips)의 입방체를 형성하는 것이다. 칩은, 입방체로 만들기전에 금선(gold wire)을 사용하여 TAB막과 동일한 박막위에 개별적으로 상호 접속된다. 전기적 시험과 소결을 거친후, 다음에 TAB막을 갖는 다른 박막의 최상부에 칩이 접착된다. 이렇게 구성함으로서 초래되는 중요한 단점은 열방출이 제한된다는 것이다. 더군다나, 일단 상기 칩의 입방체가 형성되어 기판위에 마운트되면, 다음에 일어나는 칩의 실패(chip failure)에 대해 재작업을 하는 것이 매우 힘들기 때문에 전반적으로 모듈의 비용을 상승시키는 스택안에 나머지 칩들이 포함된다.
극히 조밀한 MCM은 3차원의 접근법으로서 2차원의 다중칩 모듈을 이상적으로 일체화시킨다. MCM을 형성하기 위한 핀 그리드 어레이(Pin Gred Arrays)(PGA)의 스택이 20년 동안 사용되고 있다. 기저기판에는 종래와 같이 동핀(copper pins)이 제공된다. 다음에 반도체 다이스가 칩 운반용 기판에 플립플롭으로 마운트(flip-flop mounted)된다. 삽입체(interposer)는 상호 접속부를 납땜 접합시킴으로서 칩 운반용 기판(a chip carrier substrate)을 다른 칩 운반체 또는 기저기판에 물리적으로 그리고 전기적으로 결합시킨다. 상기 상호 접속부는, 칩 구성을 바람직하게 한정함으로서, 칩 밀도를 각 레벨에 한정하는 각 기판의 주변 근처에 위치된다. PGA의 동핀과 삽입제는, 서로 붕괴되지 못하도록 운반체사이에 격리애자(the stand-off)를 제공한다.
그리하여, MCM을 성공적으로 설계하는데 있어서, 검사, 연소 및 재작업은 물론 전력분산, 열 방출 그리고 온도 모두가 고려되어야만 된다. MCM을 설계하는 데 있어서 문제점은 전기적, 기계적 및 열적 특성을 적당히 갖춘 재료를 구하고 조립하는 것이다. 매사 절충이 필요하며, 이것은 통상적으로 응용하는 것에 따라 다를 수 있다. 상기 설계기준 모두를 충족시킴은 물론 비용에 있어서도 효율적인 용이하게 제조할 수 있는 극히 조밀한 MCM의 필요성이 존재한다.
본 발명에 따라, 하부의 칩 운반용 기판, 상부의 칩 운반용 기판 그리고 반도체 다이스를 구비하는 스택하는 반도체 다중 칩 모듈이 제공된다. 하부의 칩 운반체는 열 전도 재료의 일종이며, 최상부와 기저표면 모두에 복수개의 납땜범프를 갖는다. 또한 상부의 칩 운반용 기판도 열전도재료의 일종이며, 그 기저표면에 복수개의 납땜범프를 갖는다. 하부 및 상부 칩 운반용 기판에 전기적 그리고 물리적으로 기판마다 적어도 한개의 반도체 다이스가 부착되어 있다. 상기 및 다른 특장점은, 첨부하는 도면과 결합하여 고려할 때 다음의 상세한 설명으로부터 보다 명확히 이해될 수 있을 것이다. 유의 하여야할 점은, 예시도는 반드시 척도에 맞게 도시된 것이 아닐 수 있으며, 상세하게 예시되지 않은 본 발명의 다른 실시예가 존재할 수 있다는 것이다.
본 발명에 의해, X-Y면의 기판공간을 희생시키지 않고 반도체 디바이스를 조밀하게 패키지하기 위해 상술된 소정의 3차원 다중 칩 모듈 특성을 충족시키는 것이 가능하다. 본 발명은 다중 칩 모듈을 Z방향으로 스택시키는 것을 가능케한다. 게다가, 본 발명은 상기와 같은 모듈을 제조하기 위한 방법을 제공한다. 본 발명에 따르면 납땜을 다시 유입시키기 전에 스택하는 다중칩 모듈(8)의 단면도는 제1도에 예시되어 있다. 반도체 다이(10)는 하부의 칩 운반용 기판(12)에 마운트된다. 반도체 다이(10)와 하부의 칩 운반용 기판(12)간의 전기적 접속은 종래와 같이 접착된 와이어(13)에 의해 이루어진다. 더군다나, 반도체 다이(10)는 캡슐제(14)에 의해 캡슐화되는데, 이것은 몰드 화합물 또는 글롭 톱(glob top)과 같은 종래의 캡슐재료 종류이거나 혹은 다른 임의의 적절한 재료일 수 있다.
하부의 칩 운반용 기판(12)은 알루미늄 질화물 또는 실리콘과 같은 열전도재료로부터 바람직하게 형성된다. 또한 FR-4와 같은 인쇄회로기판재료가 사용될 수도 있지만, 이것은 세라믹 또는 실리콘만큼 그렇게 열전도성을 가지고 있지않다. 또한 PC 기판재료를 선택할 때 열팽창 부정합이 큰 것이 고려되어야만 한다. 하지만, 그 비용이 낮기 때문에 사용자가 충분히 받아들일수 있을 것이다.
추가적으로 제1도에 도시된 것과 같이, 하부의 칩 운반용 기판(12)은 기판의 기저 표면상에 복수개의 납땜 펌프(15)를 갖는다. 상기 납땜 펌프(15)는 하부의 칩 운반용 기판(12)을 도시되어 있지않은 실제 PC기판에 마운트하는데 사용된다. 게다가, 하부의 칩 운반용 기판(12)도 역시 기판의 최상부 표면에 복수개의 납땜패드 또는 범프(16)를 갖는다. 납땜 패스(16)(solder pads)는, 하부의 칩 운반용 기판(12)을 그 위에 마운트될 다른 칩 운반체에 연결시키는 역할을 한다.
또한 제1도에 도시되어 있는 것은 상부의 칩 운반용 기판(20)상에 마운트된 다른 반도체 다이(18)이다. 반도체 다이(18)와 상부의 칩 운반용 기판(20)간의 전기적 접속은 기판에 TAB결속된 와이어(21)에 의해 이루어진다. 게다가, 반도체 다이(18)은 캡슐제(22)에 의해 캡슐화되는데, 이것은 몰드화합물 또는 글롭톱(glob top)과 같은 종래의 임의의 캡슐재료이거나 또는 다른 임의의 적당한 재료일 수 있다. 또한 상부의 칩 운반용 기판(20)은 그 기저 표면에 복수개의 납땜 범프(solder bumps)(23)를 갖는다. 하부의 칩 운반용 기판(12)과 상부의 칩 운반용 기판(30)이 납때결속되기 위해 알맞게 정렬된 다음, 납땜 범프(16과 23)는 미세한 피치를 갖는 납땜열(fine pitch solder columns)을 형성하기 위해 결합된다.
상기 실시예에서, 하부의 칩 운반용 기판(12)과 상부의 칩 운반용 기판 (20)은, 서로 그리고 다른 기판을 전기적으로 접속시키기 위해 관통구멍 바이어스(through-hole vias)(24)를 갖는다. 그런, 다른 기판을 전기적으로 접속시키기 위한 동일한 목적을 위해서 다중 칩 운반용 기판도 역시 사용될 수 있다.
제2도에 도시되어 있는 것은 스택하는 다중 칩 모듈(25)의 단면도이다. 상기 실시예의 많은 특성들은 상기 제1도에 논의된 것과 동일하며, 따라서 같은 번호가 사용될 것이다. 상기 예에서, 하부의 칩 운반용 기판(26)은 그 위에 마운트된 하나의 반도체 디바이스(27)를 갖는다. 전도성 뚜껑(28)은 반도체 디바이스(27)를 덮고있다. 뚜껑(28)은 장고형 모양의 납땜 접합부(hour glass shapped solder joints)(29)를 만들기 위해 양극 격리애자로서의 역할을 할 수 있다. 상기 장로형 모양은 피로강도로 인해 납땜 접합부(29)가 실패할 시간을 극대화시킨다. 제1도에 상술한 납땜범프 또는 패드(16과 23)의 크기는 납땜 접합부(29)를 장고형 모양으로 만들기 위해 뚜껑 높이에 따라 최적화시킬 필요가 있다. 뚜껑을 정위치에 위치시키지 않으면, 한개의 보다 큰 납땜 범프를 만들기 위한 납땜 재유입공정동안 최상부와 기저의 납땜 버프가 무너질 것이다. 비록 이와 같은 모양은 받아들일 수 있지만, 피로 생명동안에는 장고형 모양이 더 바람직하다. 상부의 칩 운반용 기판(30)은 교차로 구성되어 그 위에 마운트되 두개의 반도체 디바이스(32 와 34)를 갖는다. 열 싱크(40)는, 전도성 상부의 칩 운반용 기판(30)과 뚜껑(28)을 거쳐서 하부의 반도체 디바이스(27)로부터 나오는 열을 방출시키는 상부의 칩 운반용 기판(30)에 부착되어 있다. 만약 제3레벨의 칩 운반체가 사용된다면, 이때 또한 다음의 상부레벨 반도체 디바이스도, 부착될 열싱크가 하부 레벨의 반도체 디바이스로부터 나오는 열을 방출할 수 있도록 반드시 교차되어야 한다는 것에 유의 하여야 한다. 냉각 핀을 스택으로 구성하기 위해 열싱크(40)위에 제2의 열싱크(41)가 마운트된다. MCM이 마운트될 PC기판상에서 이용 가능한 체적에만 그 제약이 있는 MCM의 열 방출 레벨을 증가시키기 위해 열 싱크(41)위에 추가저긴 열싱크를 부가시키는 것이 가능하다.
또한, 본 발명은 3차원 MCM을 만들기 위해 칩 운반체를 스택하는 방법에 관한 것이다. 제3도에 예시되어 있는 것은 부분적으로 밀집되어 있는 칩 운반체(42)의 단면도이다. 제3도에 예시된 것과 같이, 반도체 디바이스(44)는 칩 운반용 기판(46)상에 마운트된다. 칩 운반용 기판(46)은 여러층을 갖는 것으로 예시되어 있다. 임의의 실시예에서 칩 운반용 기판은, 여러층일 수 있거나 혹은 디바이스를 기판에 전기적으로 접속시키는 관통구멍 반도체(through-hole vias)를 가질 수 있다는 것에 유의하여야 한다. 다음에 특수한 땜납 조성을 갖는 복수개의 땜납범프 또는 볼(balls)(23)이 칩 운반용 기판(46)의 기저 표면상에 침전된다. 예를들어, 상기 땜납은 80/20 Pb/Sn 조성이거나 또는 다른 임의의 땜납 합금 조성일 수 있다. 다층 상호접속부(47)를 거쳐 반도체 디바이스(44)와 땜납펌프(23)사이에 전기적 접속이 이루어진다. 칩 운반체(42)는, 땜납펌프(23)의 침전이전 또는 이후중 어느 하나에서 검사되어 소결될 수 있다.
완전한 칩 운반체(48)의 단면도가 제4도에 도시되어 있다. 반도체 디바이스(50)는 칩 운반용 기판(52)에 마운트된다. 제4도에 도시된 바와 같이, 반도체 디바이스(50)는 C4기법의 땜납범프(53)를 구비한 기판(52)위에 마운트된 패드 어레이 운반체(a pad Array Carrier(CAC))로서 도시되어 있으나, 임의의 다른 마운팅 방법도 또한 사용될 수 있다.
가급적 땜납 범프(23)이외의 다른 조성으로 된 복수개의 땜납 범프 또는 볼(16)이 칩 운반용 기판(52)의 최상부 표면상에 침전된다. 땜납 범프(16)의 조성은 60/40 Pb/Sn 합금 또는 다른 비율을 가질 수 있다. 각각의 칩 운반용 기판상에 다른 합금 조성의 땜납을 사용하는 이유는, 재작업을 용이하게 하며 다음의 땜납 재유입 공정에서 땜납 접합부가 다시 용해되는 것을 방지하기 위한 것이다.
있을 수 있는 다음의 재유입 단계의 한예는 제3의 운반체를 다중칩 모듈상에 스택시키는 것이다. 또한 땜납 접합부를 제거하는 데 촛점이 맞추어진 비임이 사용되기 때문에 재작업(Rework)이 보다 용이하게 이루어진다. 그리하여, 땜납의 재용해(the remelting)동안 땜납과 기판의 다른 접속부를 흐트러트리지 않는 것이 바람직하다. 칩 운반용 기판(52)의 상부에 놓여있는 땜납 범프(16)이외에, 또한 복수개의 땜납 범프(15)가 기판(52)의 기저 표면상에 침전된다. 이와 같은 땜납 펌프(16)는 도시되어 있지 않은 PC 기판상에 완전한 MCM을 마운트 시키는데 사용될 수 있다. 다시, 이와 같은 땜납 범프는 가급적 상술된 이유 때문에 땜납 펌프(23) 또는 땜납 범프(16)중 어느 한가지 이외의 다른 조성이어야 한다.
각각의 칩 운반체(42와 48)는, 스택된 MCM을 조립하기 전에 개별적으로 검사되어 소결될 수 있다. 본 발명의 실시예인 스택된 3차원 MCM(49)은 제5도에 도시되어 있다. 스택 공정에서, 두개의 칩 운반용 기판(46과 52) 그리고 특히 땜납 범프(16과 23)의 어레이는 땜납을 재유입시키기 전에 서로에 대해 알맞게 정렬되어야만 한다. 알맞게 정렬한 예는 제1도에 도시되어 있다. 땜납을 재유입시키는 공정에서, 땜납 범프(16과 23)가 결합하여 제5도에 예시된 것과 같은 한개의 땜납 접합부 열(single solder jiont columns)(58)을 형성할 수 있다. 이와 같은 구성은, 동핀의 경우와 같이 접합부에 취약점(a weak point)을 만들지 않고 하나의 상호 접속부를 형성하기 위해 최상부 및 기저의 땜납 범프가 함깨 용해하기 때문에 두개의 동핀을 함께 결합시키는 땜납보다 더 신뢰성이 있을 것이다.
본 발명의 다른 실시예가 제6도에 도시되어 있다.
도시되어 있는 것은 스택된 MCM(59)의 단면도이다. 열 전도성 뚜껑(60)은 스택구성(the stacking configuration)에 부가되어 땜납 접합부(29)를 위한 격리애자를 형성한다. 뚜껑(60)에 의해서 가해진 물리적인 제약 때문에, 땜납 접합부(29)는 장고형 모양을 띄며, 이것은 접합부의 가장자리에 집중된 강도가 감소되기 때문에 접합부에 대한 피로생명을 증가시킨다.
스택된 MCM 제조공정의 주요 장점은, 모듈을 조립하기 전에 칩 운반체의 각 레벨이 조립, 검사 및 소결될 수 있다는 것이다. 그리하여, 가격이 상승되는 것을 피할 수 있거나 여분의 칩 세트 사용을 피할 수 있다. 게다가, 본 발명의 재작업이 용이하게 수행될 수 있다. 각각의 땜납 접합부 또는 땜납 열은 극소화 핫 에어(hot air)기법으로서 제거되어 재결합될 수 있다.
상기 설명과 예시는 본 발명과 관련된 많은 장점들을 증명한다. 더군다나, 상기 3차원 MCM의 구성은 열을 효율적으로 방출시키는 유니트라는 것을 알 수 있다. 땜납 열의 어레이는, 모듈 바깥으로 자염적으로 열을 환기시키는 냉각핀의 역할을 한다. 그리하여, 본 발명과 관련, 상기 요구관련과 장점들을 완전히 충족시키는 스택가능한 3차원 다중 칩 모듈이 제공되고 있다는 것이 명확하다. 비록 본 발명이 그것의 특정한 실시예와 관련하여 서술되고 예시되었지만, 본 발명의 단지 이와 같은 예시적인 실시예에 한정되도록 의도된 것이 아니다. 본 발명의 정신으로부터 벗어나지 않고 다양한 변형과 변화가 있을 수 있다는 것을 기술분야에 숙달된 사람들은 알수 있을 것이다. 예를들어, 스택된 3차원 MCM의 전기적 특성 또는 스택구성의 X-Y면에서 공간을 절약하는 장점에 영향을 끼치지 않고 하부의 칩 운반체를 기계적으로 지지하기 위해 더미형(dummy) 땜납범프도 또한 사용될 수 있다. 또한 본 발명이 스택하는 패드 어레이 운반체에 결코 한정되어 있지 않다는 것을 유의하여야 한다. 패키지된 반도체 디바이스를 기판의 스택을 가능케하는 칩 운반용 기판에 마운트하고 전기적으로 결합시키는 임의의 적절한 방법이 사용될 수도 있다. 그리하여, 본 발명은 이와 같은 모든 변화와 변형을 첨부된 청구범위에 포함하도록 의도되었다.

Claims (5)

  1. 반도체 다중 칩 모듈에 있어서, 자신의 최상부와 기저면상에 복수의 땜납 범프를 가지고 있는, 열전도성 재료로 된 하부 칩 운반용 기판; 상기 하부 칩 운반용 기판에 전기적으로 그리고 물리적으로 부착되어 있는 제1반도체 다이; 상기 제1반도체 다이를 보호하기 위해 상기 제1반도체 다이를 수용하고 있는 캡슐제; 최상부와 기저면을 가지고 있는, 열전도성 재료로 된 상부 칩 운반용 기판; 상기 상부 칩 운반용 기판이 기저면상에 있는 복수의 땜납, 범프; 및 상기 상부 칩 운반용 기판에 장착 및 전기 접속되어 있는 제2반도체 다이를 구비하고 있고, 상기 하부 칩 운반용 기판과 상기 상부 칩 운반용 기판은 상기 땜납 범프의 결합에 의해 서로 전기 접속되어 있고, 상기 캡슐제는 상기 하부 칩 운반용 기판과 상기 상부 칩 운반용 기판 사이에서 격리애자의 역할을 하는 것을 특징으로 하는 반도체 다중 칩 모듈.
  2. 반도체 다중 칩 모듈에 있어서, 자신의 최상부와 기저면상에 복수개의 땜납 범프를 가지고 있는, 열전도성 재료로 된 하부 칩 운반용 기판;
    상기 하부 칩 운반용 기판에 전기적으로 그리고 물리적으로 부착되어 있는 제1반도체 다이;
    최상부와 기저면을 가지고 있는, 열전도성 재료로 된 상부 칩 운반용 기판;
    상기 상부 칩 운반용 기판이 기저면상에 있는 복수의 땜납, 범프;
    상기 상부 칩 운반용 기판에 장착 및 전기 접속되어 있는 제2반도체 다이로서, 상기 하부 칩 운반용 기판과 상기 상부 칩 운반용 기판이 땜납 접합부에 의해 서로 전기 접속되어 있는 제2반도체 다이; 및
    상기 제1반도체 다이를 덮고 있고, 그리고 상부 칩 운반용 기판과 하부 칩 운반용 기판 사이에 장고형 땜납 접합부를 만들기 위해 양극 격리 애자의 역할을 하는 뚜껑을 구비하는 있는 것을 특징으로 하는 반도체 다중 칩 모듈.
  3. 제2항에 있어서, 상기 땜납 접합부는 장고형인 것을 특징으로 하는 반도체 다중 칩 모듈.
  4. 반도체 다중 칩 모듈 제조 방법에 있어서, 열전도성 재료로 된 하부 칩 운반용 기판을 제공하는 단계;
    상기 하부 칩 운반용 기판의 최상부 및 기저면상에 복수의 땜납 범프를 증착하는 단계;
    제1반도체 다이를 상기 하부 칩 운반용 기판에 장착하고 전기 접속하는 단계;
    양극 격리 애자의 역할을 하도록 상기 제1반도체 다이 전체에 뚜껑을 배치하는 단계;
    최상부와 기저면을 가지고 있는, 열전도성 재료로 된 상부 칩 운반용 기판을 제공하는 단계;
    상기 상부 칩 운반용 기판의 기저면상에 복수의 땜납 범프를 증착하는 단계;
    제2반도체 다이를 상기 상부 칩 운반용 기판에 장착하고 전기 접속하는 단계;
    상기 땜납 범프의 배치에 의해 상기 하부 칩 운반용 기판에 상기 상부 칩 운반용 기판을 정렬시키는 단계; 및
    물리적 및 전기적 접속을 달성하기 위해 상기 땜납 범프들을 함께 재유입시키는 단계를 포함하고 있는 것을 특징으로 하는 반도체 다중 칩 모듈 제조 방법.
  5. 제4항에 있어서, 재유입시키는 상기 단계는 상기 물리적 및 전기적 접속이 장고형이 되도록 수행되는 것을 특징으로 하는 반도체 다중 칩 모듈 제조 방법.
KR1019930002486A 1992-03-02 1993-02-23 스택가능한 반도체 다중 칩 모듈 및 그 제조방법 KR100248678B1 (ko)

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US07/844,075 US5222014A (en) 1992-03-02 1992-03-02 Three-dimensional multi-chip pad array carrier

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101075169B1 (ko) * 2003-08-27 2011-10-19 페어차일드코리아반도체 주식회사 파워 모듈 플립 칩 패키지

Families Citing this family (480)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010030370A1 (en) * 1990-09-24 2001-10-18 Khandros Igor Y. Microelectronic assembly having encapsulated wire bonding leads
US5679977A (en) * 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148266A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US7198969B1 (en) * 1990-09-24 2007-04-03 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
IT1247304B (it) * 1991-04-30 1994-12-12 Sgs Thomson Microelectronics Complesso circuitale di potenza a struttura modulare ad elevata compattezza e ad alta efficienza di dissipazione termica
US5241454A (en) * 1992-01-22 1993-08-31 International Business Machines Corporation Mutlilayered flexible circuit package
US5359768A (en) * 1992-07-30 1994-11-01 Intel Corporation Method for mounting very small integrated circuit package on PCB
US5854534A (en) 1992-08-05 1998-12-29 Fujitsu Limited Controlled impedence interposer substrate
KR100280762B1 (ko) * 1992-11-03 2001-03-02 비센트 비.인그라시아 노출 후부를 갖는 열적 강화된 반도체 장치 및 그 제조방법
US5495397A (en) * 1993-04-27 1996-02-27 International Business Machines Corporation Three dimensional package and architecture for high performance computer
DE4329696C2 (de) * 1993-09-02 1995-07-06 Siemens Ag Auf Leiterplatten oberflächenmontierbares Multichip-Modul mit SMD-fähigen Anschlußelementen
US5397921A (en) * 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
US5367435A (en) * 1993-11-16 1994-11-22 International Business Machines Corporation Electronic package structure and method of making same
US5991156A (en) * 1993-12-20 1999-11-23 Stmicroelectronics, Inc. Ball grid array integrated circuit package with high thermal conductivity
US5642261A (en) * 1993-12-20 1997-06-24 Sgs-Thomson Microelectronics, Inc. Ball-grid-array integrated circuit package with solder-connected thermal conductor
US5385291A (en) * 1994-01-10 1995-01-31 Micron Custom Manufacturing Services, Inc. Method employing an elevating of atmospheric pressure during the heating and/or cooling phases of ball grid array (BGA) soldering of an IC device to a PCB
DE59501667D1 (de) * 1994-01-11 1998-04-30 Siemens Ag Testverfahren für Halbleiterschaltungsebenen
US5506756A (en) * 1994-01-25 1996-04-09 Intel Corporation Tape BGA package die-up/die down
US5400950A (en) * 1994-02-22 1995-03-28 Delco Electronics Corporation Method for controlling solder bump height for flip chip integrated circuit devices
US5891761A (en) * 1994-06-23 1999-04-06 Cubic Memory, Inc. Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform
US6080596A (en) * 1994-06-23 2000-06-27 Cubic Memory Inc. Method for forming vertical interconnect process for silicon segments with dielectric isolation
US5698895A (en) * 1994-06-23 1997-12-16 Cubic Memory, Inc. Silicon segment programming method and apparatus
US5657206A (en) * 1994-06-23 1997-08-12 Cubic Memory, Inc. Conductive epoxy flip-chip package and method
US6486528B1 (en) 1994-06-23 2002-11-26 Vertical Circuits, Inc. Silicon segment programming apparatus and three terminal fuse configuration
US6124633A (en) * 1994-06-23 2000-09-26 Cubic Memory Vertical interconnect process for silicon segments with thermally conductive epoxy preform
US5675180A (en) * 1994-06-23 1997-10-07 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US6255726B1 (en) 1994-06-23 2001-07-03 Cubic Memory, Inc. Vertical interconnect process for silicon segments with dielectric isolation
US5506754A (en) * 1994-06-29 1996-04-09 Thin Film Technology Corp. Thermally matched electronic components
CN1037134C (zh) * 1994-07-04 1998-01-21 松下电器产业株式会社 集成电路装置
US5434745A (en) * 1994-07-26 1995-07-18 White Microelectronics Div. Of Bowmar Instrument Corp. Stacked silicon die carrier assembly
US5666272A (en) * 1994-11-29 1997-09-09 Sgs-Thomson Microelectronics, Inc. Detachable module/ball grid array package
US5642265A (en) * 1994-11-29 1997-06-24 Sgs-Thomson Microelectronics, Inc. Ball grid array package with detachable module
JPH08236586A (ja) * 1994-12-29 1996-09-13 Nitto Denko Corp 半導体装置及びその製造方法
US5715144A (en) * 1994-12-30 1998-02-03 International Business Machines Corporation Multi-layer, multi-chip pyramid and circuit board structure
GB9502178D0 (en) * 1995-02-03 1995-03-22 Plessey Semiconductors Ltd MCM-D Assemblies
JPH08222689A (ja) * 1995-02-15 1996-08-30 Mitsubishi Electric Corp 半導体装置とその製造方法
JP2944449B2 (ja) * 1995-02-24 1999-09-06 日本電気株式会社 半導体パッケージとその製造方法
US5783870A (en) * 1995-03-16 1998-07-21 National Semiconductor Corporation Method for connecting packages of a stacked ball grid array structure
US5514907A (en) * 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
US5657208A (en) * 1995-07-28 1997-08-12 Hewlett-Packard Company Surface mount attachments of daughterboards to motherboards
JPH0969587A (ja) * 1995-08-30 1997-03-11 Nec Kyushu Ltd Ｂｇａ型半導体装置及びｂｇａモジュール
US5861666A (en) * 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
US5623160A (en) * 1995-09-14 1997-04-22 Liberkowski; Janusz B. Signal-routing or interconnect substrate, structure and apparatus
JP2914242B2 (ja) * 1995-09-18 1999-06-28 日本電気株式会社 マルチチップモジュール及びその製造方法
DE19541039B4 (de) * 1995-11-03 2006-03-16 Assa Abloy Identification Technology Group Ab Chip-Modul sowie Verfahren zu dessen Herstellung
US5838060A (en) * 1995-12-12 1998-11-17 Comer; Alan E. Stacked assemblies of semiconductor packages containing programmable interconnect
US5719440A (en) 1995-12-19 1998-02-17 Micron Technology, Inc. Flip chip adaptor package for bare die
US6861290B1 (en) * 1995-12-19 2005-03-01 Micron Technology, Inc. Flip-chip adaptor package for bare die
US5805427A (en) * 1996-02-14 1998-09-08 Olin Corporation Ball grid array electronic package standoff design
US5808875A (en) * 1996-03-29 1998-09-15 Intel Corporation Integrated circuit solder-rack interconnect module
US5907903A (en) * 1996-05-24 1999-06-01 International Business Machines Corporation Multi-layer-multi-chip pyramid and circuit board structure and method of forming same
US5713690A (en) * 1996-05-28 1998-02-03 International Business Machines Corporation Apparatus for attaching heatsinks
US5748452A (en) * 1996-07-23 1998-05-05 International Business Machines Corporation Multi-electronic device package
US6395991B1 (en) 1996-07-29 2002-05-28 International Business Machines Corporation Column grid array substrate attachment with heat sink stress relief
KR100544033B1 (ko) * 1996-09-30 2006-01-23 지멘스 악티엔게젤샤프트 샌드위치 구조의 마이크로 전자 부품
US5791911A (en) * 1996-10-25 1998-08-11 International Business Machines Corporation Coaxial interconnect devices and methods of making the same
US5825633A (en) * 1996-11-05 1998-10-20 Motorola, Inc. Multi-board electronic assembly including spacer for multiple electrical interconnections
US5796169A (en) * 1996-11-19 1998-08-18 International Business Machines Corporation Structurally reinforced ball grid array semiconductor package and systems
US5909633A (en) * 1996-11-29 1999-06-01 Matsushita Electric Industrial Co., Ltd. Method of manufacturing an electronic component
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US7149095B2 (en) * 1996-12-13 2006-12-12 Tessera, Inc. Stacked microelectronic assemblies
US6225688B1 (en) 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6121676A (en) * 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
EP0849800A1 (en) * 1996-12-20 1998-06-24 BULL HN INFORMATION SYSTEMS ITALIA S.p.A. Multichip module with differently packaged integrated circuits and method of manufacturing it
JP3793628B2 (ja) * 1997-01-20 2006-07-05 沖電気工業株式会社 樹脂封止型半導体装置
US5856915A (en) * 1997-02-26 1999-01-05 Pacesetter, Inc. Vertically stacked circuit module using a platform having a slot for establishing multi-level connectivity
US5994166A (en) 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
JP2964983B2 (ja) * 1997-04-02 1999-10-18 日本電気株式会社 三次元メモリモジュール及びそれを用いた半導体装置
US5790384A (en) * 1997-06-26 1998-08-04 International Business Machines Corporation Bare die multiple dies for direct attach
US5831832A (en) * 1997-08-11 1998-11-03 Motorola, Inc. Molded plastic ball grid array package
US5968670A (en) * 1997-08-12 1999-10-19 International Business Machines Corporation Enhanced ceramic ball grid array using in-situ solder stretch with spring
JPH11102985A (ja) 1997-09-26 1999-04-13 Mitsubishi Electric Corp 半導体集積回路装置
CA2218307C (en) * 1997-10-10 2006-01-03 Gennum Corporation Three dimensional packaging configuration for multi-chip module assembly
US5956606A (en) * 1997-10-31 1999-09-21 Motorola, Inc. Method for bumping and packaging semiconductor die
JPH11219984A (ja) * 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
US5901041A (en) * 1997-12-02 1999-05-04 Northern Telecom Limited Flexible integrated circuit package
US5869895A (en) 1997-12-15 1999-02-09 Micron Technology, Inc. Embedded memory assembly
US6833613B1 (en) * 1997-12-18 2004-12-21 Micron Technology, Inc. Stacked semiconductor package having laser machined contacts
KR100487135B1 (ko) * 1997-12-31 2005-08-10 매그나칩 반도체 유한회사 볼그리드어레이패키지
US6053394A (en) * 1998-01-13 2000-04-25 International Business Machines Corporation Column grid array substrate attachment with heat sink stress relief
US6117382A (en) 1998-02-05 2000-09-12 Micron Technology, Inc. Method for encasing array packages
US6121679A (en) * 1998-03-10 2000-09-19 Luvara; John J. Structure for printed circuit design
US6310303B1 (en) 1998-03-10 2001-10-30 John J. Luvara Structure for printed circuit design
US6177722B1 (en) * 1998-04-21 2001-01-23 Atmel Corporation Leadless array package
USRE43112E1 (en) 1998-05-04 2012-01-17 Round Rock Research, Llc Stackable ball grid array package
US5939783A (en) * 1998-05-05 1999-08-17 International Business Machines Corporation Electronic package
US6297960B1 (en) * 1998-06-30 2001-10-02 Micron Technology, Inc. Heat sink with alignment and retaining features
US5897341A (en) * 1998-07-02 1999-04-27 Fujitsu Limited Diffusion bonded interconnect
US6137693A (en) * 1998-07-31 2000-10-24 Agilent Technologies Inc. High-frequency electronic package with arbitrarily-shaped interconnects and integral shielding
US6313522B1 (en) 1998-08-28 2001-11-06 Micron Technology, Inc. Semiconductor structure having stacked semiconductor devices
US6515355B1 (en) 1998-09-02 2003-02-04 Micron Technology, Inc. Passivation layer for packaged integrated circuits
SG88741A1 (en) * 1998-09-16 2002-05-21 Texas Instr Singapore Pte Ltd Multichip assembly semiconductor
US6707680B2 (en) 1998-10-22 2004-03-16 Board Of Trustees Of The University Of Arkansas Surface applied passives
FR2785722A1 (fr) * 1998-11-06 2000-05-12 Bull Sa Structure d'interconnexion tridimensionnelle de plusieurs circuits pour former un boitier multicomposants
US6310398B1 (en) 1998-12-03 2001-10-30 Walter M. Katz Routable high-density interfaces for integrated circuit devices
CA2358463A1 (en) * 1999-01-08 2000-07-13 Virginia Commonwealth University Polymeric delivery agents and delivery agent compounds
US6324428B1 (en) 1999-03-30 2001-11-27 Pacesetter, Inc. Implantable medical device having an improved electronic assembly for increasing packaging density and enhancing component protection
US6323060B1 (en) 1999-05-05 2001-11-27 Dense-Pac Microsystems, Inc. Stackable flex circuit IC package and method of making same
WO2000074134A1 (de) 1999-05-27 2000-12-07 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur vertikalen integration von elektrischen bauelementen mittels rückseitenkontaktierung
JP2001007472A (ja) * 1999-06-17 2001-01-12 Sony Corp 電子回路装置およびその製造方法
US6278181B1 (en) 1999-06-28 2001-08-21 Advanced Micro Devices, Inc. Stacked multi-chip modules using C4 interconnect technology having improved thermal management
US6249136B1 (en) 1999-06-28 2001-06-19 Advanced Micro Devices, Inc. Bottom side C4 bumps for integrated circuits
DE19930308B4 (de) * 1999-07-01 2006-01-12 Infineon Technologies Ag Multichipmodul mit Silicium-Trägersubstrat
US6442033B1 (en) * 1999-09-24 2002-08-27 Virginia Tech Intellectual Properties, Inc. Low-cost 3D flip-chip packaging technology for integrated power electronics modules
US6392428B1 (en) * 1999-11-16 2002-05-21 Eaglestone Partners I, Llc Wafer level interposer
US6627864B1 (en) 1999-11-22 2003-09-30 Amkor Technology, Inc. Thin image sensor package
KR100592785B1 (ko) * 2000-01-06 2006-06-26 삼성전자주식회사 칩 스케일 패키지를 적층한 적층 패키지
US6262895B1 (en) 2000-01-13 2001-07-17 John A. Forthun Stackable chip package with flex carrier
US6437448B1 (en) * 2000-01-14 2002-08-20 I-Ming Chen Semiconductor device adapted for mounting on a substrate
US6335491B1 (en) * 2000-02-08 2002-01-01 Lsi Logic Corporation Interposer for semiconductor package assembly
JP3752949B2 (ja) * 2000-02-28 2006-03-08 日立化成工業株式会社 配線基板及び半導体装置
JP2001250907A (ja) * 2000-03-08 2001-09-14 Toshiba Corp 半導体装置及びその製造方法
US7102892B2 (en) * 2000-03-13 2006-09-05 Legacy Electronics, Inc. Modular integrated circuit chip carrier
US6571466B1 (en) 2000-03-27 2003-06-03 Amkor Technology, Inc. Flip chip image sensor package fabrication method
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6778404B1 (en) * 2000-06-02 2004-08-17 Micron Technology Inc Stackable ball grid array
US6552910B1 (en) 2000-06-28 2003-04-22 Micron Technology, Inc. Stacked-die assemblies with a plurality of microelectronic devices and methods of manufacture
US6822469B1 (en) 2000-07-31 2004-11-23 Eaglestone Partners I, Llc Method for testing multiple semiconductor wafers
US6812048B1 (en) * 2000-07-31 2004-11-02 Eaglestone Partners I, Llc Method for manufacturing a wafer-interposer assembly
US7298031B1 (en) * 2000-08-09 2007-11-20 Micron Technology, Inc. Multiple substrate microelectronic devices and methods of manufacture
US6607937B1 (en) * 2000-08-23 2003-08-19 Micron Technology, Inc. Stacked microelectronic dies and methods for stacking microelectronic dies
JP3722209B2 (ja) * 2000-09-05 2005-11-30 セイコーエプソン株式会社 半導体装置
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US6437984B1 (en) * 2000-09-07 2002-08-20 Stmicroelectronics, Inc. Thermally enhanced chip scale package
TW569403B (en) * 2001-04-12 2004-01-01 Siliconware Precision Industries Co Ltd Multi-chip module and its manufacturing method
US6608763B1 (en) 2000-09-15 2003-08-19 Staktek Group L.P. Stacking system and method
US6686657B1 (en) * 2000-11-07 2004-02-03 Eaglestone Partners I, Llc Interposer for improved handling of semiconductor wafers and method of use of same
US6665194B1 (en) * 2000-11-09 2003-12-16 International Business Machines Corporation Chip package having connectors on at least two sides
US6342406B1 (en) 2000-11-15 2002-01-29 Amkor Technology, Inc. Flip chip on glass image sensor package fabrication method
US6849916B1 (en) 2000-11-15 2005-02-01 Amkor Technology, Inc. Flip chip on glass sensor package
JP4521984B2 (ja) * 2000-11-29 2010-08-11 京セラ株式会社 積層型半導体装置および実装基板
US6414384B1 (en) * 2000-12-22 2002-07-02 Silicon Precision Industries Co., Ltd. Package structure stacking chips on front surface and back surface of substrate
US6885106B1 (en) 2001-01-11 2005-04-26 Tessera, Inc. Stacked microelectronic assemblies and methods of making same
JP2002231885A (ja) * 2001-02-06 2002-08-16 Mitsubishi Electric Corp 半導体装置
DE10110203B4 (de) * 2001-03-02 2006-12-14 Infineon Technologies Ag Elektronisches Bauteil mit gestapelten Halbleiterchips und Verfahren zu seiner Herstellung
US6386890B1 (en) 2001-03-12 2002-05-14 International Business Machines Corporation Printed circuit board to module mounting and interconnecting structure and method
US6479321B2 (en) 2001-03-23 2002-11-12 Industrial Technology Research Institute One-step semiconductor stack packaging method
US6462408B1 (en) * 2001-03-27 2002-10-08 Staktek Group, L.P. Contact member stacking system and method
US6762487B2 (en) 2001-04-19 2004-07-13 Simpletech, Inc. Stack arrangements of chips and interconnecting members
KR100380107B1 (ko) * 2001-04-30 2003-04-11 삼성전자주식회사 발열체를 갖는 회로 기판과 기밀 밀봉부를 갖는 멀티 칩패키지
US20030040166A1 (en) * 2001-05-25 2003-02-27 Mark Moshayedi Apparatus and method for stacking integrated circuits
US20030067082A1 (en) * 2001-05-25 2003-04-10 Mark Moshayedi Apparatus and methods for stacking integrated circuit devices with interconnected stacking structure
US6695623B2 (en) 2001-05-31 2004-02-24 International Business Machines Corporation Enhanced electrical/mechanical connection for electronic devices
US6586826B1 (en) * 2001-06-13 2003-07-01 Amkor Technology, Inc. Integrated circuit package having posts for connection to other packages and substrates
JP3925615B2 (ja) * 2001-07-04 2007-06-06 ソニー株式会社 半導体モジュール
US6458626B1 (en) * 2001-08-03 2002-10-01 Siliconware Precision Industries Co., Ltd. Fabricating method for semiconductor package
US6692979B2 (en) 2001-08-13 2004-02-17 Optoic Technology, Inc. Methods of fabricating optoelectronic IC modules
US6674948B2 (en) 2001-08-13 2004-01-06 Optoic Technology, Inc. Optoelectronic IC module
US7218527B1 (en) * 2001-08-17 2007-05-15 Alien Technology Corporation Apparatuses and methods for forming smart labels
US6617680B2 (en) * 2001-08-22 2003-09-09 Siliconware Precision Industries Co., Ltd. Chip carrier, semiconductor package and fabricating method thereof
US20030048624A1 (en) * 2001-08-22 2003-03-13 Tessera, Inc. Low-height multi-component assemblies
US20040173894A1 (en) * 2001-09-27 2004-09-09 Amkor Technology, Inc. Integrated circuit package including interconnection posts for multiple electrical connections
US7335995B2 (en) * 2001-10-09 2008-02-26 Tessera, Inc. Microelectronic assembly having array including passive elements and interconnects
DE10297316T5 (de) * 2001-10-09 2004-12-09 Tessera, Inc., San Jose Gestapelte Baugruppen
US6977440B2 (en) * 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
US20050051859A1 (en) * 2001-10-25 2005-03-10 Amkor Technology, Inc. Look down image sensor package
US7371609B2 (en) * 2001-10-26 2008-05-13 Staktek Group L.P. Stacked module systems and methods
US7053478B2 (en) 2001-10-26 2006-05-30 Staktek Group L.P. Pitch change and chip scale stacking system
US7202555B2 (en) 2001-10-26 2007-04-10 Staktek Group L.P. Pitch change and chip scale stacking system and method
US6914324B2 (en) 2001-10-26 2005-07-05 Staktek Group L.P. Memory expansion and chip scale stacking system and method
US6576992B1 (en) 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
US20060255446A1 (en) 2001-10-26 2006-11-16 Staktek Group, L.P. Stacked modules and method
US6940729B2 (en) * 2001-10-26 2005-09-06 Staktek Group L.P. Integrated circuit stacking system and method
US7656678B2 (en) 2001-10-26 2010-02-02 Entorian Technologies, Lp Stacked module systems
US7310458B2 (en) 2001-10-26 2007-12-18 Staktek Group L.P. Stacked module systems and methods
US7485951B2 (en) 2001-10-26 2009-02-03 Entorian Technologies, Lp Modularized die stacking system and method
US6956284B2 (en) * 2001-10-26 2005-10-18 Staktek Group L.P. Integrated circuit stacking system and method
US7026708B2 (en) * 2001-10-26 2006-04-11 Staktek Group L.P. Low profile chip scale stacking system and method
US20030234443A1 (en) 2001-10-26 2003-12-25 Staktek Group, L.P. Low profile stacking system and method
US20030089977A1 (en) * 2001-11-09 2003-05-15 Xilinx, Inc. Package enclosing multiple packaged chips
US6710264B2 (en) * 2001-11-16 2004-03-23 Hewlett-Packard Development Company, L.P. Method and apparatus for supporting a circuit component having solder column interconnects using external support
US6813162B2 (en) * 2001-11-16 2004-11-02 Hewlett-Packard Development Company, L.P. Method and apparatus for supporting circuit component having solder column array interconnects using interposed support shims
US6809937B2 (en) 2001-11-16 2004-10-26 Hewlett-Packard Development Company, L.P. Method and apparatus for shock and vibration isolation of a circuit component
US6541710B1 (en) * 2001-11-16 2003-04-01 Hewlett-Packard Company Method and apparatus of supporting circuit component having a solder column array using interspersed rigid columns
US6657134B2 (en) * 2001-11-30 2003-12-02 Honeywell International Inc. Stacked ball grid array
US7081373B2 (en) * 2001-12-14 2006-07-25 Staktek Group, L.P. CSP chip stack with flex circuit
US6958533B2 (en) * 2002-01-22 2005-10-25 Honeywell International Inc. High density 3-D integrated circuit package
US6791035B2 (en) * 2002-02-21 2004-09-14 Intel Corporation Interposer to couple a microelectronic device package to a circuit board
DE10209204B4 (de) * 2002-03-04 2009-05-14 Infineon Technologies Ag Elektronisches Bauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben
US20030178719A1 (en) * 2002-03-22 2003-09-25 Combs Edward G. Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package
US6600661B1 (en) 2002-04-08 2003-07-29 Hewlett-Packard Development Company, L.P. Method and apparatus for supporting a circuit component
AU2003223783A1 (en) * 2002-04-29 2003-11-17 Silicon Pipe, Inc. Direct-connect signaling system
US7750446B2 (en) 2002-04-29 2010-07-06 Interconnect Portfolio Llc IC package structures having separate circuit interconnection structures and assemblies constructed thereof
KR20030085868A (ko) * 2002-05-02 2003-11-07 삼성전기주식회사 부품 다층 실장 소자의 제조방법 및 이에 의해 제조된 소자
US6952047B2 (en) * 2002-07-01 2005-10-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
KR100639203B1 (ko) * 2002-07-08 2006-10-30 주식회사 하이닉스반도체 플라스틱 패키지를 갖는 반도체 장치와 비지에이 패키지를갖는 반도체 장치를 적층하는 방법
US6661100B1 (en) 2002-07-30 2003-12-09 International Business Machines Corporation Low impedance power distribution structure for a semiconductor chip package
US6891272B1 (en) 2002-07-31 2005-05-10 Silicon Pipe, Inc. Multi-path via interconnection structures and methods for manufacturing the same
US6765288B2 (en) * 2002-08-05 2004-07-20 Tessera, Inc. Microelectronic adaptors, assemblies and methods
US20050167817A1 (en) * 2002-08-05 2005-08-04 Tessera, Inc. Microelectronic adaptors, assemblies and methods
US20040105244A1 (en) * 2002-08-06 2004-06-03 Ilyas Mohammed Lead assemblies with offset portions and microelectronic assemblies with leads having offset portions
WO2004017399A1 (en) * 2002-08-16 2004-02-26 Tessera, Inc. Microelectronic packages with self-aligning features
US7294928B2 (en) * 2002-09-06 2007-11-13 Tessera, Inc. Components, methods and assemblies for stacked packages
US7071547B2 (en) * 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US20040061213A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
JP4800625B2 (ja) * 2002-09-17 2011-10-26 スタッツ・チップパック・インコーポレイテッド 積み重ねられたパッケージ間のワイヤボンド相互接続を有する半導体マルチパッケージモジュール及びその形成方法
US7064426B2 (en) * 2002-09-17 2006-06-20 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
US7205647B2 (en) * 2002-09-17 2007-04-17 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US7053476B2 (en) * 2002-09-17 2006-05-30 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
JP2004111656A (ja) * 2002-09-18 2004-04-08 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
US7057269B2 (en) * 2002-10-08 2006-06-06 Chippac, Inc. Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package
US7034387B2 (en) * 2003-04-04 2006-04-25 Chippac, Inc. Semiconductor multipackage module including processor and memory package assemblies
AU2003279215A1 (en) * 2002-10-11 2004-05-04 Tessera, Inc. Components, methods and assemblies for multi-chip packages
KR100618812B1 (ko) * 2002-11-18 2006-09-05 삼성전자주식회사 향상된 신뢰성을 가지는 적층형 멀티 칩 패키지
KR100608327B1 (ko) * 2002-12-26 2006-08-04 매그나칩 반도체 유한회사 비지에이 패키지의 적층 방법
KR100498470B1 (ko) * 2002-12-26 2005-07-01 삼성전자주식회사 적층형 반도체 패키지 및 그 제조방법
US7014472B2 (en) * 2003-01-13 2006-03-21 Siliconpipe, Inc. System for making high-speed connections to board-mounted modules
JP3891123B2 (ja) * 2003-02-06 2007-03-14 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、及び半導体装置の製造方法
JP4110992B2 (ja) * 2003-02-07 2008-07-02 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
US6879028B2 (en) * 2003-02-21 2005-04-12 Freescale Semiconductor, Inc. Multi-die semiconductor package
JP2004259886A (ja) * 2003-02-25 2004-09-16 Seiko Epson Corp 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
US6815254B2 (en) * 2003-03-10 2004-11-09 Freescale Semiconductor, Inc. Semiconductor package with multiple sides having package contacts
JP2004281818A (ja) * 2003-03-17 2004-10-07 Seiko Epson Corp 半導体装置、電子デバイス、電子機器、キャリア基板の製造方法、半導体装置の製造方法および電子デバイスの製造方法
JP2004281920A (ja) * 2003-03-18 2004-10-07 Seiko Epson Corp 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP2004281919A (ja) * 2003-03-18 2004-10-07 Seiko Epson Corp 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP4096774B2 (ja) * 2003-03-24 2008-06-04 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法
JP2004349495A (ja) * 2003-03-25 2004-12-09 Seiko Epson Corp 半導体装置、電子デバイス、電子機器および半導体装置の製造方法
US6841029B2 (en) * 2003-03-27 2005-01-11 Advanced Cardiovascular Systems, Inc. Surface modification of expanded ultra high molecular weight polyethylene (eUHMWPE) for improved bondability
WO2004107441A1 (en) * 2003-05-28 2004-12-09 Infineon Technologies Ag An integrated circuit package employing a flexible substrate
US20040262728A1 (en) * 2003-06-30 2004-12-30 Sterrett Terry L. Modular device assemblies
US7303109B2 (en) * 2003-07-01 2007-12-04 Asm Technology Singapore Pte Ltd. Stud bumping apparatus
DE10334575B4 (de) * 2003-07-28 2007-10-04 Infineon Technologies Ag Elektronisches Bauteil und Nutzen sowie Verfahren zur Herstellung derselben
US7180165B2 (en) 2003-09-05 2007-02-20 Sanmina, Sci Corporation Stackable electronic assembly
US7542304B2 (en) * 2003-09-15 2009-06-02 Entorian Technologies, Lp Memory expansion and integrated circuit stacking system and method
JP4324773B2 (ja) * 2003-09-24 2009-09-02 セイコーエプソン株式会社 半導体装置の製造方法
US7495179B2 (en) 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
US8641913B2 (en) * 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
JP3867796B2 (ja) * 2003-10-09 2007-01-10 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP2005123463A (ja) * 2003-10-17 2005-05-12 Seiko Epson Corp 半導体装置及びその製造方法、半導体装置モジュール、回路基板並びに電子機器
US7098542B1 (en) 2003-11-07 2006-08-29 Xilinx, Inc. Multi-chip configuration to connect flip-chips to flip-chips
US7061121B2 (en) 2003-11-12 2006-06-13 Tessera, Inc. Stacked microelectronic assemblies with central contacts
JP5197961B2 (ja) * 2003-12-17 2013-05-15 スタッツ・チップパック・インコーポレイテッド マルチチップパッケージモジュールおよびその製造方法
US7709968B2 (en) * 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
TW200536089A (en) * 2004-03-03 2005-11-01 United Test & Assembly Ct Ltd Multiple stacked die window csp package and method of manufacture
US7245021B2 (en) * 2004-04-13 2007-07-17 Vertical Circuits, Inc. Micropede stacked die component assembly
US7215018B2 (en) * 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
US7705432B2 (en) * 2004-04-13 2010-04-27 Vertical Circuits, Inc. Three dimensional six surface conformal die coating
US20050242425A1 (en) * 2004-04-30 2005-11-03 Leal George R Semiconductor device with a protected active die region and method therefor
US7368695B2 (en) * 2004-05-03 2008-05-06 Tessera, Inc. Image sensor package and fabrication method
DE112004002858T5 (de) 2004-05-11 2007-04-19 Spansion Llc, Sunnyvale Träger für eine Stapel-Halbleitervorrichtung und Verfahren zum Herstellen derselben
CN1998077B (zh) 2004-05-20 2010-06-16 斯班逊有限公司 半导体装置的制造方法及半导体装置
US20050258527A1 (en) * 2004-05-24 2005-11-24 Chippac, Inc. Adhesive/spacer island structure for multiple die package
US20050269692A1 (en) * 2004-05-24 2005-12-08 Chippac, Inc Stacked semiconductor package having adhesive/spacer structure and insulation
US8552551B2 (en) * 2004-05-24 2013-10-08 Chippac, Inc. Adhesive/spacer island structure for stacking over wire bonded die
JP4051570B2 (ja) 2004-05-26 2008-02-27 セイコーエプソン株式会社 半導体装置の製造方法
JP4561969B2 (ja) * 2004-05-26 2010-10-13 セイコーエプソン株式会社 半導体装置
JP2005340449A (ja) 2004-05-26 2005-12-08 Seiko Epson Corp 半導体装置の製造方法
US7253511B2 (en) * 2004-07-13 2007-08-07 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US7468893B2 (en) 2004-09-03 2008-12-23 Entorian Technologies, Lp Thin module system and method
US20060050492A1 (en) 2004-09-03 2006-03-09 Staktek Group, L.P. Thin module system and method
US7616452B2 (en) 2004-09-03 2009-11-10 Entorian Technologies, Lp Flex circuit constructions for high capacity circuit module systems and methods
US7511968B2 (en) 2004-09-03 2009-03-31 Entorian Technologies, Lp Buffered thin module system and method
US7606049B2 (en) 2004-09-03 2009-10-20 Entorian Technologies, Lp Module thermal management system and method
US7542297B2 (en) 2004-09-03 2009-06-02 Entorian Technologies, Lp Optimized mounting area circuit module system and method
US7443023B2 (en) 2004-09-03 2008-10-28 Entorian Technologies, Lp High capacity thin module system
US7606040B2 (en) 2004-09-03 2009-10-20 Entorian Technologies, Lp Memory module system and method
US7522421B2 (en) * 2004-09-03 2009-04-21 Entorian Technologies, Lp Split core circuit module
US7446410B2 (en) 2004-09-03 2008-11-04 Entorian Technologies, Lp Circuit module with thermal casing systems
US7606050B2 (en) 2004-09-03 2009-10-20 Entorian Technologies, Lp Compact module system and method
US7760513B2 (en) 2004-09-03 2010-07-20 Entorian Technologies Lp Modified core for circuit module system and method
US7423885B2 (en) 2004-09-03 2008-09-09 Entorian Technologies, Lp Die module system
US7289327B2 (en) 2006-02-27 2007-10-30 Stakick Group L.P. Active cooling methods and apparatus for modules
US7579687B2 (en) 2004-09-03 2009-08-25 Entorian Technologies, Lp Circuit module turbulence enhancement systems and methods
US7324352B2 (en) 2004-09-03 2008-01-29 Staktek Group L.P. High capacity thin module system and method
WO2006035528A1 (ja) * 2004-09-29 2006-04-06 Murata Manufacturing Co., Ltd. スタックモジュール及びその製造方法
TWI255023B (en) * 2004-10-05 2006-05-11 Via Tech Inc Cavity down stacked multi-chip package
TW200614448A (en) * 2004-10-28 2006-05-01 Advanced Semiconductor Eng Method for stacking bga packages and structure from the same
CN101053079A (zh) * 2004-11-03 2007-10-10 德塞拉股份有限公司 堆叠式封装的改进
CN101300913B (zh) * 2004-11-12 2012-01-25 阿纳洛格装置公司 带间隔、带凸块部件结构
US7309914B2 (en) 2005-01-20 2007-12-18 Staktek Group L.P. Inverted CSP stacking system and method
TWI255536B (en) * 2005-02-02 2006-05-21 Siliconware Precision Industries Co Ltd Chip-stacked semiconductor package and fabrication method thereof
TWI257135B (en) * 2005-03-29 2006-06-21 Advanced Semiconductor Eng Thermally enhanced three dimension package and method for manufacturing the same
TWI423401B (zh) * 2005-03-31 2014-01-11 Stats Chippac Ltd 在上側及下側具有暴露基底表面之半導體推疊封裝組件
US7364945B2 (en) 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
TWI442520B (zh) * 2005-03-31 2014-06-21 Stats Chippac Ltd 具有晶片尺寸型封裝及第二基底及在上側與下側包含暴露基底表面之半導體組件
US7545031B2 (en) * 2005-04-11 2009-06-09 Stats Chippac Ltd. Multipackage module having stacked packages with asymmetrically arranged die and molding
US7354800B2 (en) 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
US7429786B2 (en) * 2005-04-29 2008-09-30 Stats Chippac Ltd. Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US7582960B2 (en) * 2005-05-05 2009-09-01 Stats Chippac Ltd. Multiple chip package module including die stacked over encapsulated package
US7033861B1 (en) 2005-05-18 2006-04-25 Staktek Group L.P. Stacked module systems and method
US7394148B2 (en) * 2005-06-20 2008-07-01 Stats Chippac Ltd. Module having stacked chip scale semiconductor packages
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8619452B2 (en) 2005-09-02 2013-12-31 Google Inc. Methods and apparatus of stacking DRAMs
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8169233B2 (en) 2009-06-09 2012-05-01 Google Inc. Programming of DIMM termination resistance values
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US7609567B2 (en) * 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
KR100631991B1 (ko) * 2005-07-14 2006-10-09 삼성전기주식회사 Ｉｃ 칩 적층 구조를 갖는 전자 기기용 모듈
US7829989B2 (en) * 2005-09-07 2010-11-09 Alpha & Omega Semiconductor, Ltd. Vertical packaged IC device modules with interconnected 3D laminates directly contacts wafer backside
US8476591B2 (en) * 2005-09-21 2013-07-02 Analog Devices, Inc. Radiation sensor device and method
KR100722634B1 (ko) * 2005-10-06 2007-05-28 삼성전기주식회사 고밀도 반도체 패키지 및 그 제조 방법
DE102005051414B3 (de) * 2005-10-25 2007-04-12 Infineon Technologies Ag Halbleiterbauteil mit Verdrahtungssubstrat und Lotkugeln sowie Verfahren zur Herstellung des Halbleiterbauteils
US7262615B2 (en) * 2005-10-31 2007-08-28 Freescale Semiconductor, Inc. Method and apparatus for testing a semiconductor structure having top-side and bottom-side connections
US7576995B2 (en) 2005-11-04 2009-08-18 Entorian Technologies, Lp Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area
DE102005055487B3 (de) * 2005-11-18 2007-05-16 Infineon Technologies Ag Elektronische Struktur mit über lötbare Verbindungselemente verbundenen Komponenten sowie Verfahren zu seiner Herstellung
US20070141751A1 (en) * 2005-12-16 2007-06-21 Mistry Addi B Stackable molded packages and methods of making the same
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US8067267B2 (en) * 2005-12-23 2011-11-29 Tessera, Inc. Microelectronic assemblies having very fine pitch stacking
US7456088B2 (en) * 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7768125B2 (en) * 2006-01-04 2010-08-03 Stats Chippac Ltd. Multi-chip package system
US7508069B2 (en) 2006-01-11 2009-03-24 Entorian Technologies, Lp Managed memory component
US7608920B2 (en) 2006-01-11 2009-10-27 Entorian Technologies, Lp Memory card and method for devising
US7605454B2 (en) 2006-01-11 2009-10-20 Entorian Technologies, Lp Memory card and method for devising
KR100749141B1 (ko) * 2006-01-11 2007-08-14 삼성전기주식회사 패키지 온 패키지 기판 및 그 제조방법
US7304382B2 (en) 2006-01-11 2007-12-04 Staktek Group L.P. Managed memory component
US7508058B2 (en) 2006-01-11 2009-03-24 Entorian Technologies, Lp Stacked integrated circuit module
US7511969B2 (en) 2006-02-02 2009-03-31 Entorian Technologies, Lp Composite core circuit module system and method
TWI292617B (en) * 2006-02-03 2008-01-11 Siliconware Precision Industries Co Ltd Stacked semiconductor structure and fabrication method thereof
US7750482B2 (en) * 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US8704349B2 (en) * 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US7652361B1 (en) * 2006-03-03 2010-01-26 Amkor Technology, Inc. Land patterns for a semiconductor stacking structure and method therefor
US7986043B2 (en) * 2006-03-08 2011-07-26 Stats Chippac Ltd. Integrated circuit package on package system
US7981702B2 (en) * 2006-03-08 2011-07-19 Stats Chippac Ltd. Integrated circuit package in package system
US20070210433A1 (en) * 2006-03-08 2007-09-13 Rajesh Subraya Integrated device having a plurality of chip arrangements and method for producing the same
TWI294654B (en) * 2006-04-24 2008-03-11 Siliconware Precision Industries Co Ltd Stack structure for semiconductor package and method for fabricating the same
CN100464400C (zh) * 2006-05-08 2009-02-25 矽品精密工业股份有限公司 半导体封装件堆栈结构及其制法
US7550680B2 (en) * 2006-06-14 2009-06-23 Stats Chippac Ltd. Package-on-package system
TWI311788B (en) * 2006-06-30 2009-07-01 Advanced Semiconductor Eng A systematical package and a method are disclosed for preventing a pad from being polluted
TWI314774B (en) * 2006-07-11 2009-09-11 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
TWI315574B (en) * 2006-07-28 2009-10-01 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
US7638868B2 (en) * 2006-08-16 2009-12-29 Tessera, Inc. Microelectronic package
US7545029B2 (en) * 2006-08-18 2009-06-09 Tessera, Inc. Stack microelectronic assemblies
US7378733B1 (en) * 2006-08-29 2008-05-27 Xilinx, Inc. Composite flip-chip package with encased components and method of fabricating same
TWI312569B (en) * 2006-10-12 2009-07-21 Siliconware Precision Industries Co Ltd Semiconductor package on which a semiconductor device is stacked and production method thereof
JP5016892B2 (ja) * 2006-10-17 2012-09-05 東京エレクトロン株式会社 検査装置及び検査方法
CN101165886B (zh) * 2006-10-20 2010-11-10 矽品精密工业股份有限公司 可供半导体器件堆栈其上的半导体封装件及其制法
US7468553B2 (en) 2006-10-20 2008-12-23 Entorian Technologies, Lp Stackable micropackages and stacked modules
US7417310B2 (en) 2006-11-02 2008-08-26 Entorian Technologies, Lp Circuit module having force resistant construction
US7683468B2 (en) * 2006-12-21 2010-03-23 Tessera, Inc. Enabling uniformity of stacking process through bumpers
TWI335070B (en) * 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
US8409920B2 (en) * 2007-04-23 2013-04-02 Stats Chippac Ltd. Integrated circuit package system for package stacking and method of manufacture therefor
TW200847304A (en) * 2007-05-18 2008-12-01 Siliconware Precision Industries Co Ltd Stackable package structure and fabrication method thereof
JP5179787B2 (ja) * 2007-06-22 2013-04-10 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7884457B2 (en) * 2007-06-26 2011-02-08 Stats Chippac Ltd. Integrated circuit package system with dual side connection
US7763983B2 (en) * 2007-07-02 2010-07-27 Tessera, Inc. Stackable microelectronic device carriers, stacked device carriers and methods of making the same
JP4823161B2 (ja) * 2007-07-20 2011-11-24 日本テキサス・インスツルメンツ株式会社 半導体装置
US8299626B2 (en) 2007-08-16 2012-10-30 Tessera, Inc. Microelectronic package
US8558379B2 (en) 2007-09-28 2013-10-15 Tessera, Inc. Flip chip interconnection with double post
US20090151992A1 (en) * 2007-12-18 2009-06-18 Broadcom Corporation Formation and integration of passive structures using silicon and package substrate
US7605460B1 (en) 2008-02-08 2009-10-20 Xilinx, Inc. Method and apparatus for a power distribution system
US7875967B2 (en) * 2008-03-10 2011-01-25 Stats Chippac Ltd. Integrated circuit with step molded inner stacking module package in package system
TWI473553B (zh) * 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
US8004093B2 (en) * 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
US8270176B2 (en) 2008-08-08 2012-09-18 Stats Chippac Ltd. Exposed interconnect for a package on package system
US8461693B2 (en) * 2008-08-26 2013-06-11 Siemens Medical Instruments Pte. Ltd. Substrate arrangement
TWI499024B (zh) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
US20100171206A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Chu Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same
US8012797B2 (en) * 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
JP5193898B2 (ja) * 2009-02-12 2013-05-08 新光電気工業株式会社 半導体装置及び電子装置
JP5535494B2 (ja) * 2009-02-23 2014-07-02 新光電気工業株式会社 半導体装置
JP5106460B2 (ja) 2009-03-26 2012-12-26 新光電気工業株式会社 半導体装置及びその製造方法、並びに電子装置
JP5340789B2 (ja) * 2009-04-06 2013-11-13 新光電気工業株式会社 電子装置及びその製造方法
JP5330065B2 (ja) 2009-04-13 2013-10-30 新光電気工業株式会社 電子装置及びその製造方法
US8716868B2 (en) 2009-05-20 2014-05-06 Panasonic Corporation Semiconductor module for stacking and stacked semiconductor module
TWI469283B (zh) * 2009-08-31 2015-01-11 Advanced Semiconductor Eng 封裝結構以及封裝製程
US8198131B2 (en) * 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
TWI409922B (zh) * 2009-12-08 2013-09-21 Powertech Technology Inc 以垂直銲柱機械補強之半導體封裝堆疊結構
US8884422B2 (en) * 2009-12-31 2014-11-11 Stmicroelectronics Pte Ltd. Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture
US8502394B2 (en) * 2009-12-31 2013-08-06 Stmicroelectronics Pte Ltd. Multi-stacked semiconductor dice scale package structure and method of manufacturing same
US20110156240A1 (en) * 2009-12-31 2011-06-30 Stmicroelectronics Asia Pacific Pte. Ltd. Reliable large die fan-out wafer level package and method of manufacture
US8436255B2 (en) * 2009-12-31 2013-05-07 Stmicroelectronics Pte Ltd. Fan-out wafer level package with polymeric layer for high reliability
US8466997B2 (en) * 2009-12-31 2013-06-18 Stmicroelectronics Pte Ltd. Fan-out wafer level package for an optical sensor and method of manufacture thereof
TWI408785B (zh) * 2009-12-31 2013-09-11 Advanced Semiconductor Eng 半導體封裝結構
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
KR20110085481A (ko) * 2010-01-20 2011-07-27 삼성전자주식회사 적층 반도체 패키지
TWI419283B (zh) * 2010-02-10 2013-12-11 Advanced Semiconductor Eng 封裝結構
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8304296B2 (en) 2010-06-23 2012-11-06 Stats Chippac Ltd. Semiconductor packaging system with multipart conductive pillars and method of manufacture thereof
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8304880B2 (en) * 2010-09-14 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8378477B2 (en) * 2010-09-14 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with film encapsulation and method of manufacture thereof
US8553420B2 (en) 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
TWI451546B (zh) 2010-10-29 2014-09-01 Advanced Semiconductor Eng 堆疊式封裝結構、其封裝結構及封裝結構之製造方法
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
TWI445155B (zh) 2011-01-06 2014-07-11 Advanced Semiconductor Eng 堆疊式封裝結構及其製造方法
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
JP2012204631A (ja) 2011-03-25 2012-10-22 Fujitsu Semiconductor Ltd 半導体装置、半導体装置の製造方法及び電子装置
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
KR101740483B1 (ko) * 2011-05-02 2017-06-08 삼성전자 주식회사 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
TWI439192B (zh) * 2011-05-12 2014-05-21 Fujikura Ltd 貫通配線基板、電子元件封裝體、及電子零件（一）
KR20130005465A (ko) * 2011-07-06 2013-01-16 삼성전자주식회사 반도체 스택 패키지 장치
EP2745317A4 (en) 2011-08-16 2015-08-12 Intel Corp OFFSET INTERPOSTERS FOR LARGE BOTTOM HOUSINGS AND LARGE CHIP STRUCTURES HOUSING ON HOUSING
US8872318B2 (en) 2011-08-24 2014-10-28 Tessera, Inc. Through interposer wire bond using low CTE interposer with coarse slot apertures
US9013037B2 (en) 2011-09-14 2015-04-21 Stmicroelectronics Pte Ltd. Semiconductor package with improved pillar bump process and structure
JP6091053B2 (ja) * 2011-09-14 2017-03-08 キヤノン株式会社 半導体装置、プリント回路板及び電子製品
US20130093073A1 (en) * 2011-10-17 2013-04-18 Mediatek Inc. High thermal performance 3d package on package structure
CN103050455A (zh) * 2011-10-17 2013-04-17 联发科技股份有限公司 堆叠封装结构
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8916481B2 (en) 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US8779601B2 (en) 2011-11-02 2014-07-15 Stmicroelectronics Pte Ltd Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US20130140688A1 (en) * 2011-12-02 2013-06-06 Chun-Hung Chen Through Silicon Via and Method of Manufacturing the Same
US8867231B2 (en) * 2012-01-13 2014-10-21 Tyco Electronics Corporation Electronic module packages and assemblies for electrical systems
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9475145B2 (en) 2012-02-27 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Solder bump joint in a device including lamellar structures
US9842817B2 (en) 2012-02-27 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Solder bump stretching method and device for performing the same
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9406596B2 (en) * 2013-02-21 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Molding compound structure
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
KR102126977B1 (ko) 2013-08-21 2020-06-25 삼성전자주식회사 반도체 패키지
KR102184989B1 (ko) 2013-09-11 2020-12-01 삼성전자주식회사 반도체 패키지 및 그 제조방법
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US20150340308A1 (en) * 2014-05-21 2015-11-26 Broadcom Corporation Reconstituted interposer semiconductor package
US9691686B2 (en) 2014-05-28 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Contact pad for semiconductor device
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9190367B1 (en) * 2014-10-22 2015-11-17 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
JPWO2017037828A1 (ja) 2015-08-31 2018-06-14 オリンパス株式会社 内視鏡、電子ユニットおよび電子ユニットの製造方法
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
CN109478516B (zh) * 2016-04-29 2023-06-13 库利克和索夫工业公司 将电子组件连接至基板
WO2018009168A1 (en) * 2016-07-02 2018-01-11 Intel Corporation Electronic device package on package (pop)
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
KR20180095371A (ko) * 2017-02-17 2018-08-27 엘지전자 주식회사 이동 단말기 및 인쇄 회로 기판
EP3866893B1 (en) 2018-10-19 2022-06-15 West Pharmaceutical Services, Inc. Electronic plunger assembly
DE102019106562A1 (de) * 2019-03-14 2020-09-17 Sick Ag Leiterplatteneinheit
US11721657B2 (en) 2019-06-14 2023-08-08 Stmicroelectronics Pte Ltd Wafer level chip scale package having varying thicknesses
US11830746B2 (en) * 2021-01-05 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892230A (ja) * 1981-11-27 1983-06-01 Mitsubishi Electric Corp 半導体装置
JPS60194548A (ja) 1984-03-16 1985-10-03 Nec Corp チツプキヤリヤ
US4672421A (en) * 1984-04-02 1987-06-09 Motorola, Inc. Semiconductor packaging and method
US4878611A (en) * 1986-05-30 1989-11-07 American Telephone And Telegraph Company, At&T Bell Laboratories Process for controlling solder joint geometry when surface mounting a leadless integrated circuit package on a substrate
US5036431A (en) * 1988-03-03 1991-07-30 Ibiden Co., Ltd. Package for surface mounted components
JP2612045B2 (ja) * 1988-07-29 1997-05-21 マツダ株式会社 自動車のスリップ制御装置
JPH02174255A (ja) * 1988-12-27 1990-07-05 Mitsubishi Electric Corp 半導体集積回路装置
US5060844A (en) * 1990-07-18 1991-10-29 International Business Machines Corporation Interconnection structure and test method
US5011066A (en) * 1990-07-27 1991-04-30 Motorola, Inc. Enhanced collapse solder interconnection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101075169B1 (ko) * 2003-08-27 2011-10-19 페어차일드코리아반도체 주식회사 파워 모듈 플립 칩 패키지

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