CN105895624A - 多芯片堆叠封装结构及其制造方法 - Google Patents

多芯片堆叠封装结构及其制造方法 Download PDF

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CN105895624A
CN105895624A CN201610037319.0A CN201610037319A CN105895624A CN 105895624 A CN105895624 A CN 105895624A CN 201610037319 A CN201610037319 A CN 201610037319A CN 105895624 A CN105895624 A CN 105895624A
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chip
weld pad
distance piece
multichip stacking
relative
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CN105895624B (zh
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林殿方
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King Yuan Electronics Co Ltd
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Dawning Leading Technology Inc
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Abstract

本发明是有关于一种多芯片堆叠封装结构及其制造方法，该多芯片封装结构包括：一基板，包括多个电性连接垫；一第一芯片，其一下表面黏贴于该基板上；一第二芯片，是以交叉错位方式黏贴于该第一芯片的一上表面上；一间隔件，是以与该第二芯片交叉错位方式设置于第二芯片的一上表面上；以及一第三芯片，是以与该间隔件交叉错位方式设置于该间隔件的一上表面上，使得该第三芯片的一端与该间隔件的一端形成一第一间距。由此，改变打线受力点的位置，以降低打线时芯片断裂的风险。

Description

多芯片堆叠封装结构及其制造方法
技术领域
本发明是关于一种半导体芯片封装结构及其制造方法，尤指一种适用于多芯片堆叠封装结构及其制造方法。
背景技术
多芯片封装结构(Multi-chip package，MCP)是将多个半导体芯片整合在单一封装结构中，可提高电子元件的密度，缩短电子元件间的电性连接路径，此种封装体不仅可减少多个芯片使用上所占用的体积，更可提高整体的性能。
已知多芯片封装结构是将多个芯片垂直对齐堆叠、交叉错位堆叠或阶梯状堆叠，接着通过打线与基板电性连接。多个半导体芯片堆叠封装技术中，多个相同尺寸芯片的堆叠封装技术是常见的封装技术。
在已知技术中，请参阅图1是已知的堆叠式多芯片封装结构的剖面示意图，其第一芯片13的下表面黏贴于基板11上，第二芯片14的下表面则以交叉错位方式黏贴于第一芯片13的上表面上；第三芯片15的下表面以交叉错位方式黏贴于第二芯片14上，而第四芯片16的下表面则以交叉错位方式黏贴于第三芯片15的上表面上。此外，每一芯片的上表面上的焊垫皆有多条导线分别对应电连接于基板10上的多个电性连接垫12。此外，所述芯片相互间皆是通过一黏晶胶17黏贴。由于该第三芯片15与第二芯片14的堆叠处产生了一空间，因此，在打线时由于芯片支撑力不够，而产生芯片破裂的问题。因此，为了满足打线所需受力，需增厚第三芯片15的厚度以避免芯片受损。
另一已知技术中，如中国台湾专利公开号第201222737A1号，是揭示一种半导体晶粒封装，该半导体封装的一实例包含与一第二半导体晶粒群组穿插的一第一半导体晶粒群组。来自该第一及第二群组的晶粒沿一第一轴线彼此偏移，且沿与该第一轴线正交的一第二轴线相对于彼此交错。该半导体封装的一第二实例包含一形状不规则的边缘及一自该封装中的最下部半导体晶粒上方的一半导体晶粒至该基板的线接合。
然而，如图1所示，此种堆叠式多芯片封装结构1需增加芯片厚度以避免芯片受损，然而，在增加芯片厚度时，亦增加材料制备的复杂度，因而产生不易掌握芯片的厚度的问题。此外，在另一已知技术中，通过打线方式将芯片电性连接于基板，但经由打线方式来电性连接容易造成芯片破裂。因此，目前亟需要一种多芯片堆叠封装结构及其制造方法，通过改变打线位置以提供较佳支撑，以及提供不经打线之间隔件，以避免芯片受损，以及提供相同厚度的芯片以简化工艺步骤并控制制造成本。
发明内容
本发明的主要目的是在提供一种堆叠式多芯片封装结构，能利用芯片与间隔件交叉错位的堆叠方式，通过改变打线位置，因而，可降低打线时芯片断裂的风险，并且达到轻薄短小的需求。
为达成上述目的，本发明提供一种多芯片堆叠封装结构，包括：一基板，可包括多个电性连接垫；一第一芯片，包括有一第一焊垫的一上表面及相对的一下表面，该第一芯片的该下表面黏贴于该基板上；一第二芯片，包括有一第二焊垫的一上表面及相对的一下表面，该第二芯片的该下表面可以交叉错位方式黏贴于该第一芯片的该上表面；一间隔件，包括有一上表面及相对的一下表面，并且可以与该第二芯片交叉错位方式设置于该第二芯片上表面上；以及一第三芯片，包括有一第三焊垫的一上表面及相对的一下表面，并且可以与该间隔件交叉错位方式设置于该间隔件的上表面上，使得该第三芯片的一端与该间隔件的一端可形成一第一间距。
于本发明的多芯片堆叠封装结构中，可还包括一第四芯片，该第四芯片可包括有一第四焊垫的一上表面及相对的一下表面，该第四芯片可以交叉错位方式黏贴于该第三芯片的该上表面上。此外，于本发明的多芯片堆叠封装结构中，该第三焊垫可紧邻于该第四芯片而设置以提供最佳的支撑，进而避免芯片破裂。
于本发明的多芯片堆叠封装结构中，可还包括多条导线，用于将所述电性连接垫与该第一焊垫、第二焊垫、第三焊垫及第四焊垫电性连接，或将所述焊垫彼此电性连接，以输入或输出信号。于本发明的多芯片堆叠封装结构中，该间隔件不与导线链接，因此该间隔件不会因为打线而破裂。
于本发明的多芯片堆叠封装结构中，该第四芯片的一端与该间隔件的一端可形成一第二间距；其中，该第二间距的距离与第一间距的距离可依据使用者需求而任意变化，在本发明一态样中，该第二间距的距离可为该第一间距的距离的两倍，但本发明并未局限于此。于本发明的多芯片堆叠封装结构中，将该第一间距的距离、第二间距的距离与该芯片的宽度相加所获得的数值需小于该基板的长度，以利于封装该多芯片堆叠封装结构。
于本发明的多芯片堆叠封装结构中，所堆叠的芯片数量及间隔件的数量可依据使用者需求而任意变化，在本发明一态样中，所堆叠的芯片数量为4且间隔件数量为1，此外，该间隔件堆叠的位置较佳为所述芯片中间，以提供较佳的支撑避免芯片破裂。
于本发明的多芯片堆叠封装结构中，该第一芯片、该第二芯片、该第三芯片及该第四芯片可通过一黏胶层彼此黏贴，此外，该第一芯片的下表面可通过一黏晶胶黏贴于该基板上；本发明的该黏胶层或该黏晶胶可为一薄膜覆盖导线胶层(Film On Wier Tape)或其他等效结构的黏胶层；在本发明一态样中，该黏晶胶可为薄膜覆盖导线胶层。
除此之外，本发明另一目的是提供一种多芯片堆叠封装结构的制造方法，包括：提供一基板，该基板可具有多个电性连接垫；设置第一芯片于该基板上，该第一芯片可包括有一第一焊垫的一上表面及相对的一下表面，该第一芯片的该下表面黏贴于该基板；设置一第二芯片于该第一芯片上，该第二芯片可包括有一第二焊垫的一上表面及相对的一下表面，该第二芯片的该下表面可以交叉错位方式黏贴于该第一芯片的该上表面；设置一间隔件于该第二芯片上，该间隔件可包括有一上表面及相对的一下表面，并且以与该第二芯片交叉错位方式设置于该第二晶面的上表面上；以及设置一第三芯片于该间隔件上，该第三芯片可包括有一第三焊垫的一上表面及相对的一下表面，该第三芯片的该下表面设置于该间隔件的上表面上，使得该第三芯片的一端与该间隔件的一端形成一第一间距。
于本发明的多芯片堆叠封装结构的制造方法中，可还包括设置一第四芯片于该第三芯片上，该第四芯片可包括有一第四焊垫的一上表面及相对的一下表面，该第四芯片可以交叉错位方式黏贴于该第三芯片的该上表面上。于本发明的多芯片堆叠封装结构的制造方法中，该第三焊垫是紧邻于该第四芯片而设置以提供最佳的支撑，进而避免芯片破裂。。
于本发明的多芯片堆叠封装结构的制造方法中，可还包括形成多条导线，所述导线将所述电性连接垫与该第一焊垫、该第二焊垫、该第三焊垫及该第四焊垫电性连接，或将所述焊垫彼此电性连接。于本发明的多芯片堆叠封装结构的制造方法中，该间隔件不与导线链接，因此该间隔件不会因为打线而破裂。
于本发明的多芯片堆叠封装结构的制造方法中，该第四芯片的一端与该间隔件的一端可形成一第二间距；其中，该第二间距的距离与第一间距的距离可依据使用者需求而任意变化，在本发明一态样中，该第二间距的距离可为该第一间距的距离的两倍，但本发明并未局限于此。
于本发明的多芯片堆叠封装结构的制造方法中，该第一芯片、该第二芯片、该第三芯片及该第四芯片可通过一黏胶层彼此黏贴，此外，该第一芯片的下表面可通过一黏晶胶黏贴于该基板上。本发明的该黏胶层或该黏晶胶可为一薄膜覆盖导线胶层或其他等效结构的黏胶层；在本发明一态样中，该黏晶胶可为薄膜覆盖导线胶层。
是以，本发明的功效在于改变打线位置以提供较佳支撑，进而避免芯片破裂，并且提供相同厚度的芯片以简化芯片工艺。综上所述，本发明的特征为在多个芯片中具有至少一间隔件，可提供所述芯片较佳的支撑点，且该间隔件不具有导线链接，可避免因打线而造成芯片破裂。
附图说明
为进一步说明本发明的技术内容，以下结合实施例及附图详细说明如后，其中：
图1为已知的堆叠式多芯片封装结构的剖面示意图。
图2为本发明实施例1的堆叠式多芯片封装结构的剖面示意图。
图3为本发明实施例1的打线受力点与先前技术打线受力点的剖面示意图。
图4为本发明实施例2的多芯片堆叠封装结构的制造方法的流程图。
具体实施方式
以下是通过具体实施例说明本发明的实施方式，熟习此技术的人士可由本说明书所揭示的内容轻易地了解本发明的其他优点与功效。此外，本发明亦可通过其他不同具体实施例加以施行或应用，在不悖离本发明的精神下进行各种修饰与变更。
实施例1
请参照图2所示，是本发明实施例1的剖面示意图。于本发明的多芯片堆叠封装结构2中，包括：一基板10，包括多个电性连接垫101；一第一芯片20，包括有一第一焊垫201的一上表面及相对的一下表面，该第一芯片20的该下表面黏贴于该基板10上；一第二芯片30，包括有一第二焊垫301的一上表面及相对的一下表面，该第二芯片30的该下表面以交叉错位方式黏贴于该第一芯片20的该上表面；一间隔件40，包括有一上表面及相对的一下表面，并且以与该第二芯片30交叉错位方式设置于该第二芯片30的上表面上；以及一第三芯片50，包括有一第三焊垫501的一上表面及相对的一下表面，并且以与该间隔件40交叉错位方式设置于该间隔件40的上表面上，使得该第三芯片50的一端与该间隔件40的一端形成一第一间距。其次，本发明的多芯片堆叠封装结构2还包括一第四芯片60，该第四芯片60包括有一第四焊垫601的一上表面及相对的一下表面，该第四芯片60以交叉错位方式黏贴于该第三芯片50的该上表面上；此外，该第三焊垫501是紧邻于该第四芯片60而设置以提供较佳支撑点，以避免第三芯片50破裂。接着，通过导线70将所述电性连接垫101与该第一焊垫201、第二焊垫301、第三焊垫501及第四焊垫601电性连接，并将所述焊垫彼此电性连接，以输入或输出信号。再者，该第四芯片60的一端与该间隔件40的一端形成一第二间距；且该第二间距的距离为该第二间距的距离的两倍。
请参照图3所示，是本发明实施例1的打线受力点与先前技术打线受力点的剖面示意图。如图3所示，该第三芯片50的一端与该间隔件40的一端形成一第一间距(X)，以及该第四芯片60的一端与该间隔件40的一端形成一第二间距(2X)，此外，该第一芯片20的一端与该第二芯片30的一端形成该第二间距(2X)。在图3中，原打线受力点A与本发明的打线受力点B相比，本发明的受力点B较接近第三芯片50而受力点A较远离第三芯片50。由于原打线受力点A下方并无较好的支撑，因此在打线时，容易造成芯片破裂，因而需要较厚的芯片以满足打线所需受力，进而避免芯片受损，然而，制造出较厚的芯片在材料备制上将增加工艺的复杂度，因此，在理想厚度(即芯片及间隔件具有相同厚度)前提下，改变打线位置(如，受力点B)并增加间隔件的设置可提供较佳的支撑，进而避免芯片受损。请参照图3，受力点A与受力点B具有相同支点，然而由于受力点A与受力点B的施力点位置不同，因此会产生不同的力矩，由图3可知在受力点B具有较佳支撑，进而避免第三芯片50因打线而破裂。
实施例2
请参照图4所示，是本发明实施例2的多芯片堆叠封装结构的制造方法的流程图。首先，如步骤401所示，提供一基板，该基板可有多个电性连接垫。其次，如步骤402所示，设置第一芯片，将第一芯片设置于该基板上，该第一芯片包括有一第一焊垫的一上表面及相对的一下表面，该第一芯片的该下表面黏贴于该基板。再者，如步骤403所示，设置第二芯片，将该第二芯片设置于该第一芯片上，该第二芯片包括有一第二焊垫的一上表面及相对的一下表面，该第二芯片的该下表面以交叉错位方式黏贴于该第一芯片的该上表面。接着，如步骤404所示，设置间隔件，将该间隔件设置于该第二芯片上，该间隔件包括有一上表面及相对的一下表面，并且以与该第二芯片交叉错位方式设置于该第二芯片的该上表面上。接着，如步骤405所示，设置第三芯片，将第三芯片设置于该间隔件上，该第三芯片包括有一第三焊垫的一上表面及相对的一下表面，该第三芯片的该下表面设置于该间隔件上表面上，使得该第三芯片的一端与该间隔件的一端形成一第一间距。如步骤406所示，设置第四芯片，将第四芯片设置于该第三芯片上，该第四芯片包括有一第四焊垫的一上表面及相对的一下表面，该第四芯片以交叉错位方式黏贴于该第三芯片的该上表面上，且该第三焊垫是紧邻于该第四芯片而设置，以提供较佳支撑避免第三芯片破裂。在步骤401与步骤402之间，通过黏贴黏晶胶使第一芯片黏贴于基板上；在步骤402、步骤403、步骤404、步骤405以及步骤406之间，通过黏贴黏胶层使第一芯片、第二芯片、第三芯片以及第四芯片彼此黏贴。最后，如步骤407所示，提供导线，将所述电性连接垫与该第一焊垫、第二焊垫、第三焊垫及第四焊垫电性连接，并将所述焊垫彼此电性连接，以输入或输出信号。
在本发明的多芯片堆叠封装结构中，通过改变打线位置以提供较佳支撑，以及提供不经打线之间隔件以避免芯片受损，再者提供相同厚度的芯片以简化工艺步骤并控制制造成本。本发明可以堆叠复数芯片，可将不同功能的芯片整合在单一封装结构中，不仅可减少多个芯片使用上所占用的体积，更可提高整体的性能。
上述实施例仅是为了方便说明而举例而已，本发明所主张的权利范围自应以权利要求范围所述为准，而非仅限于上述实施例。

Claims (15)

1.一种多芯片堆叠封装结构，包括：
一基板，包括多个电性连接垫；
一第一芯片，包括有一第一焊垫的一上表面及相对的一下表面，该第一芯片的该下表面黏贴于该基板上；
一第二芯片，包括有一第二焊垫的一上表面及相对的一下表面，该第二芯片的该下表面以交叉错位方式黏贴于该第一芯片的该上表面；
一间隔件，包括有一上表面及相对的一下表面，并且以与该第二芯片交叉错位方式设置于其上；以及
一第三芯片，包括有一第三焊垫的一上表面及相对的一下表面，该第三芯片的该下表面设置于该间隔件上，使得该第三芯片的一端与该间隔件的一端形成一第一间距。
2.如权利要求1所述的多芯片堆叠封装结构，还包括一第四芯片，该第四芯片包括有一第四焊垫的一上表面及相对的一下表面，该第四芯片以交叉错位方式黏贴于该第三芯片的该上表面上。
3.如权利要求2所述的多芯片堆叠封装结构，其中，该第三焊垫紧邻于该第四芯片而设置。
4.如权利要求2所述的多芯片堆叠封装结构，还包括多条导线，用于将所述电性连接垫与该第一焊垫、该第二焊垫、该第三焊垫及该第四焊垫电性连接，或将所述焊垫彼此电性连接。
5.如权利要求2所述的多芯片堆叠封装结构，其中，该第四芯片的一端与该间隔件的一端形成一第二间距。
6.如权利要求5所述的多芯片堆叠封装结构，其中，该第二间距的距离为该第一间距的距离的两倍。
7.如权利要求2所述的多芯片堆叠封装结构，其中，该第一芯片、该第二芯片、该第三芯片及该第四芯片通过一黏胶层彼此黏贴。
8.一种多芯片堆叠封装结构的制造方法，包括：
提供一基板，该基板具有多个电性连接垫；
设置第一芯片于该基板上，该第一芯片包括有一第一焊垫的一上表面及相对的一下表面，该第一芯片的该下表面黏贴于该基板；
设置一第二芯片于该第一芯片上，该第二芯片包括有一第二焊垫的一上表面及相对的一下表面，该第二芯片的该下表面以交叉错位方式黏贴于该第一芯片的该上表面；
设置一间隔件于该第二芯片上，该间隔件包括有一上表面及相对的一下表面，并且以与该第二芯片交叉错位方式设置于其上；以及
设置一第三芯片于该间隔件上，该第三芯片包括有一第三焊垫的一上表面及相对的一下表面，该第三芯片的该下表面设置于该间隔件上，使得该第三芯片的一端与该间隔件的一端形成一第一间距。
9.如权利要求8所述的多芯片堆叠封装结构的制造方法，还包括设置一第四芯片于该第三芯片上，该第四芯片包括有一第四焊垫的一上表面及相对的一下表面，该第四芯片以交叉错位方式黏贴于该第三芯片的该上表面上。
10.如权利要求9所述的多芯片堆叠封装结构的制造方法，其中，该第三焊垫紧邻于该第四芯片而设置。
11.如权利要求9所述的多芯片堆叠封装结构的制造方法，还包括形成多条导线，所述导线将所述电性连接垫与该第一焊垫、该第二焊垫、该第三焊垫及该第四焊垫电性连接，或将所述焊垫彼此电性连接。
12.如权利要求9所述的多芯片堆叠封装结构的制造方法，其中，该第四芯片的一端与该间隔件的一端形成一第二间距。
13.如权利要求12所述的多芯片堆叠封装结构的制造方法，该第二间距的距离为该第一间距的距离的两倍。
14.如权利要求9所述的多芯片堆叠封装结构的制造方法，其中，该第一芯片、该第二芯片、该第三芯片及该第四芯片通过一黏胶层彼此黏贴。
15.如权利要求8所述的多芯片堆叠封装结构的制造方法，其中，该第一芯片的下表面通过一黏晶胶黏贴于该基板上。
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