CN101471330B - 半导体封装结构 - Google Patents

半导体封装结构 Download PDF

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CN101471330B
CN101471330B CN200710203519XA CN200710203519A CN101471330B CN 101471330 B CN101471330 B CN 101471330B CN 200710203519X A CN200710203519X A CN 200710203519XA CN 200710203519 A CN200710203519 A CN 200710203519A CN 101471330 B CN101471330 B CN 101471330B
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CN101471330A (zh
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魏史文
吴英政
余孟龙
罗世闵
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
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    • H05K2201/10507—Involving several components
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Abstract

一种半导体封装结构，其包括一基板模块和电连接在所述基板模块上的多个半导体元件。所述基板模块由一具有顶面和底面的整体基板切割而成。所述基板模块包括一外接面板和一承载面板，所述承载面板竖直放置、所述外接面板水平放置并与所述承载面板于所述外接面板的中轴线处相互连接。所述外接面板为一矩形平板，其用于实现基板模块与外界装置的电性连接，所述承载面板为一矩形平板，其用于承载非层叠地电连接在基板模块上的所述半导体元件。

Description

半导体封装结构
技术领域
本发明涉及一种半导体的封装结构，尤其是涉及一种充分利用空间的高密度半导体封装结构。
背景技术
随着科学技术的发展，电子产品的多功能，高密度及成本控制的需求日益增长，目前多晶片模块封装结构应用广泛，用于将不同功能的晶片，例如微处理器(Microprocessors)，内存(Memory)、逻辑元件(Logic)、光学集成电路(Optic ICs)及电容器(Capacitors)等集成到同一模块内，以取代单晶片封装技术。现有的多晶片模组封装结构主要采取叠晶封装的方法，即将多块晶片依次堆叠在基板上以充分利用三维空间减少封装结构所占面积较大的问题。
请参阅图1，其为现有的叠晶封装结构，其包括一第一基板2、一第一晶片4、复数个第一导线6、次封装结构8，复数个第三导线10、一第一封胶12及复数个焊球14。
所述第一基板2具有一上表面16及一下表面18。所述第一晶片4附着于所述第一基板2的上表面16且利用所述第一导线6与第一基板2电性连接，所述次封装结构8包括一第二基板20、一第二晶片22、复数个第二导线24及一第二封胶26。所述次封装结构8具有一顶面28及一底面30，该次封装结构8的底面30以一胶粘剂粘附于所述第一晶片4上。
在上述叠晶封装结构中，各个晶片之间通过胶材粘合，因不同晶片的物理特性不同，当外界环境变化时胶材内部会因为不同晶片的尺寸变化不同而产生的应力影响到叠晶封装结构的强度。此外，在叠晶的封装过程中，位于上层的晶片要等待下层晶片封装完成后才能进行封装，因此需要较长的制程时间，再之，叠晶封装必须在全部晶片都封装好后才能进行品质测试，而叠晶封装中任何一个不合格的子晶片都会导致整个叠晶封装结构成为次品，因此，良品率除了受到制程因素的影响外还会受到每个晶片质量的限制。
综上所述，叠晶封装结构存在着整体强度低、制程时间长和良品率低等问题。
发明内容
有鉴于此，有必要提供一种纵向堆叠的半导体封装结构，以解决上述叠晶封装结构所存在的问题。
一种半导体封装结构，包括一基板模块和电连接在所述基板模块上的多个半导体元件。所述基板模块包括一承载面板和至少一个外接面板，所述承载面板竖直放置，所述外接面板水平放置并与所述承载面板相互垂直连接为一整体。所述外接面板用于实现基板模块与外界装置的电性连接，所述承载面板用于承载非层叠地电连接在基板模块上的所述半导体元件。
与现有的叠晶封装结构相对比，首先，在本发明提供的半导体封装结构的制作过程中，每个半导体元件连接至承载面板之前可进行先行测试，从而确保了最后半导体封装结构的良品率。其次，本发明提供的半导体封装结构避免了半导体元件之间的直接胶合，解决了因胶体内应力所导致封装结构强度低的问题。再次，在本发明提供的半导体封装结构的制作过程中，将半导体元件连接至承载面板内的动作可同时进行，缩短了制程时间。
附图说明
图1为现有叠晶封装结构示意图。
图2为本发明第一实施方式提供的半导体封装结构示意图。
图3为本发明第二实施方式提供的半导体封装结构示意图。
图4A为本发明第一实施方式提供的半导体封装结构的基板模块切割示意图。
图4B为本发明第二实施方式提供的半导体封装结构的基板模块切割示意图。
具体实施方式
如图2所示，其为本发明第一实施方式提供的半导体封装结构示意图。从图中可知，半导体封装结构包括一基板模块32和电连接于所述基板模块32上的多个半导体元件34。所述基板模块32包括一外接面板36和一承载面板38，所述承载面板38和所述外接面板36均为一矩形，所述承载面板38与所述外接面板36于所述外接面板36的中轴线处相互垂直连接，因此，整个基板模块30的横截面为一倒置的“T”形。
所述基板模块32的外接面板36具有一上表面40及一下表面42，在所述外接面板36的下表面42有一电连接片35，所述基板模块32通过所述电连接片35与外界装置实现电性连接。所述承载面板38具有二个侧面44，在所述二个侧面44上分别有电连接片45和电连接片47，所述半导体元件34可通过所述电连接片45和电连接片47与基板模块32建立电性连接。
在所述基板模块32内有一电连接片49将位于承载面板38侧面44上的电连接片45和电连接片47相连。在所述基板模块32内还有一电连接片51与所述电连接片49垂直相交并与所述位于外接面板36上的电连接片35相连，该电连接片49用于将连接在承载面板38上半导体元件34的信号导出。
如图3所示，其为本发明第二实施方式提供的半导体封装结构示意图。从图中可知，半导体封装结构包括一基板模块46和电连接于所述基板模块46上的多个半导体元件48。所述基板模块46包括一承载面板50、上外接面板52和下外接面板54，所述承载面板50、所述上外接面板52和下外接面板54均为一矩形，所述承载面板50垂直连接于所述上外接面板52和下外接面板54之间，在本实施方式中，所述承载面板50于所述上外接面板52和下外接面板54的中轴线处相连接。因此，所述基板模块46的横截面为一“工”形。
所述上外接面板52分别具有一上表面56及一下表面58，所述下外接面板54分别具有一顶面60及一底面62。所述上外接面板52的上表面56和所述下外接面板54的底面62上分别有一电连接片57、59，基板模块46通过所述电连接片57、59与外界装置实现电性连接。所述承载面板50具有二个侧面64，在所述二个侧面64上分别有一电连接片61、63，半导体元件48通过所述电连接片61、63与基板模块46之间建立电性连接。
在所述基板模块46内有一电连接片65将位于承载面板50侧面64上的电连接片61和电连接片63相连。在所述基板模块46内还有一电连接片67与所述电连接片65垂直相交并分别与位于上外接面板52上的电连接片57和下外接面板54上的电连接片59相连，所述电连接片67用于将连接在承载面板50上半导体元件48的信号导出。
所述基板模块32(46)的材料可为玻璃纤维，如：环氧树脂(Epoxy，俗称FR4)、聚酰亚胺(Polyimide，俗称FR5)、碳氢树脂(Teflon)；强化塑胶，如：杜劳特铬合金钢(Duruid)或陶瓷。
所述与基板模块32(46)电连接的半导体元件34(64)为已封装完成的晶片模块，其可为现有的半导体晶片模块，例如：薄四方扁平封装模组(ThinQuad Flat Package，TQFP)，薄型小尺寸封装(Thin Small Outline Package，TSOP)、小型方块平面封装模组(Quad Flat Package，QFP)、球栅阵列封装模组(Ball Grid Array Package，BGA)、微型球栖阵列封装模组(Micro Ball GridArray Package，MBGA)、倒装芯片模组(Flip chip)或芯片级封装模组(ChipScale Package，CSP)等。
所述基板模块32(64)与外界装置的电连接可通过表面组装技术(SurfaceMounted Technology，SMT)、异方向性导电胶(Anisotropic ConductiveAdhesives，ACA)或异方向性导电膜(Anisotropic Conductive Film，ACF)等方法来实现。
上述本发明第一实施方式和第二实施方式所提供之半导体封装结构可通过在内部已布线的整体基板上刻槽，封装元件后再切割的方法而制得。
如图4A和图4B所示，其分别为本发明第一实施方式和第二实施方式所提供的半导体封装结构的基板模块32(64)的切割示意图。所述整体基板68a(68b)具有一上表面72a(72b)和一下表面74a(74b)，其内部埋设有电连接片链条76a(76b)。分别在所述上表面72a(72b)和下表面74a(74b)的相应位置开设凹槽78a(78b)，凹槽78a(78b)位置根据所要切割成的基板模块32(64)的形状不同而不同。所述凹槽78a(78b)具有一底面80a(80b)和两个侧面82a(82b)，在所述凹槽底面80a(80b)的电连接片76a(76b)上封装半导体元件84，对封装好的整体基板68a(68b)进行测试以确保每个凹槽78a(78b)内的半导体元件84与整体基板68a(68b)正常连接，最后将测试合格的整体基板68a(68b)切割成独立的基板模块32(64)。横截面为倒置“T”形的基板模块32为沿着所述凹糟78a边缘所在的平面AA’切割而成，横截面为“工”形的基板模块64为沿着所述凹槽78b之间的连接部的中轴面BB’切割而成。
上述纵向堆叠的半导体封装结构利用所述基板模块上的承载面板将原来半导体晶片的水平层叠封装转变为在所述承载面板侧面上的纵向堆叠封装。相比于现有技术，本发明提供的半导体封装结构可令每个半导体元件的封装过程同时进行，有效地缩短了制程时间，其次纵向堆叠封装避免了各个半导体元件之间胶体的内应力而导致的半导体封装结构强度低的问题，同时也避免了因一个半导体元件损坏而使得整个封装结构报废的问题。
本技术领域的普通技术人员应当认识到，以上的实施方式仅是用来说明本发明，而并非用作为对本发明的限定，只要在本发明的实质精神范围之内，对以上实施方式所作的适当改变和变化都落在本发明要求保护的范围之内，

Claims (9)

1.一种半导体封装结构，其包括一基板模块和电连接在所述基板模块上的多个半导体元件，其特征在于：所述基板模块包括一承载面板和至少一个外接面板，所述承载面板竖直放置，所述外接面板水平放置并与所述承载面板相互垂直连接为一整体，所述外接面板用于实现基板模块与外界装置的电性连接，所述承载面板用于承载非层叠地电连接在基板模块上的所述半导体元件。
2.如权利要求1所述的半导体封装结构，其特征在于：所述承载面板和所述外接面板均为一矩形，所述承载面板于所述外接面板的中轴线处与所述外接面板相互垂直连接成一基板模块，所述基板模块的横截面为一倒置的“T ”形。
3.如权利要求1所述的半导体封装结构，其特征在于：所述承载面板和所述外接面板均为一矩形，所述承载面板垂直连接于二个所述外接面板之间构成一基板模块。
4.如权利要求1所述的半导体封装结构，其特征在于：所述承载面板的二个侧面上分别有一电连接片用于与半导体元件实现电连接。
5.如权利要求4所述的半导体封装结构，其特征在于：所述外接面板的端面上有一电连接片用于与外界装置实现电连接。
6.如权利要求5所述的半导体封装结构，其特征在于：所述基板模块内有二个相交的电连接片将所述承载面板上的电连接片与所述外接面板上的电连接片相互导通。
7.如权利要求1所述的半导体封装结构，其特征在于：所述半导体元件与所述承载面板之间通过表面封装技求、异方向性导电膜、异方向性导电胶或固晶打线的方式连接。
8.如权利要求1所述的半导体封装结构，其特征在于：所述半导体元件可为薄四方扁平封装模组，小型方块平面封装模组、微型球栅阵列封装模组、倒装芯片模组或芯片级封装模组。
9.如权利要求1所述的半导体封装结构，其特征在于：所述基板模块的材料可为玻璃纤维、强化塑胶或陶瓷。
CN200710203519XA 2007-12-28 2007-12-28 半导体封装结构 Expired - Fee Related CN101471330B (zh)

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