200933867 九、發明說明： 【發明所屬之技術領域】 尤其係涉及一種 本發明涉及一種半導體之封裝結 充分利用空間之高密度半導體封裝結構。 【先前技術】 隨著科學技術之發展，電子產σ 成本控制之需求日益增長。目功能、高密度及 ❹廣泛，用於將不同功能：：片模， r 、 月 例如微處理器 L Pr〇CeSS〇rS )、1己憶、體（Memory )、邏輯元件 =、光學積體電路(0ptic ICs )及電容器(Ca—_ ) 曰同一模組内，以取代單晶片封裳技術。先前之多 曰曰片模組封裝結構主要採取疊晶 片依次堆疊在基板上以充分；;將多塊晶 占面積較大之問題。 J用一維工間減少封裝結構所 ❹一美=閱圖^其為先前之疊晶封農結構，其包括-第 複數個第二導線10、-第一封膠12及複數個焊球Μ。 —所述第一基板2具有一上表自16及一下表面18。所 ^ 4附著於所述第—基板2之上表面16且利用所 導線6與第-基板2電性連接n欠封裝結構8 ^一结第—基板2G、—第二晶片22、複數個第二導線24 一弟二封膠26。所述次封裝結構8具有—頂面28及一 底面3〇,該次封裝結構8之底面3〇以一膠枯劑枯附於所 200933867 述第一晶片4上。 合，封裝結構中’各個晶片之間藉由膠材枯 内部會因為不同晶片之…7田外界㈣化時膠材 聶曰封"士娃 核化不同而產生之應力影響到 度。此外，在疊晶之封裝過程中，位於 故竹層晶成後核進行封震，是 長之難時間。再之，疊晶封裝必須在全部晶= β人林之；曰y 丁〇口質測喊，而疊晶封裝中任何一個不 均會導致整個疊晶封裝結構成為次品，是 品質除了受到制程因素之影響外還會受到每個晶片 、制程時 綜上所述，疊晶封裝結構存在著整體強度低 間長及良品率低等問題。 【發明内容】 有鑒於此’有必要提供一種縱向堆疊之半導體封裝結 ❹ 以解決上述疊晶封裝結構所存在之問題。 一種半導體封裝結構’包括—基板模組及電連接在所 二ς板核，1上之複數個半導體元件。所述基板模組包括一 、面板及至少-個外接面板’所述承載面板與所述外接 ^板相互垂直連接為—整體。所述外接面板用於實現基板 模組與外界裝置之電性連接，所述承載面板用於承載電連 接在基板模組上之所述半導體元件。 —與先前之疊晶封裝結構相對比，首先，在本發明提供 之半導體封裝結構之製作過程中，每個半導體元件連接至 200933867 承載面板之前可進行先行測試，從而確保了最後半導體封 .裝結構之良品率。其次’本發明提供之半導體封裝結構避 .^了半導體元件之間之直接膠合，解決了因膠體内應力所 導致封裝結構強度低之問題。再次，在本發明提供之半導 體封裝結構之製作過程中，將半導體元件連接至承載面板 内之動作可同時進行，縮短了制程時間。 【實施方式】 如圖2所不’其為本發明第一實施方式提供之半導體封 〇裝結構示意圖。從圖中可知，半導體封裝結構包括一基板 模組32及電連接於所述基板模組32上之複數個半導體元件 34。所述基板模组32包括一外接面板％及一承載面板％， 所述承載面板38及所述外接面板36均為一矩形，所述承載 面板38與所述外接面板36於所述外接面板^之中轴線處相 互垂直連接。是故，整個基板模組3〇之橫截 T，，形。 j直心 料基板模組32之外接面板36具有—上表面微一下 所料接：板％之下表面42有一底部電連接片 ，八土板杈組32藉由所述底部電連接片35與外界裝置 實現電性連接。所述承載面板38具有二個側面料，在所述 -個側面44上分別有侧面電連接片衫、47，所述半導體元 藉由所述側面電連接片45、47與基板模組32建立電 在所述基板模組32内有-橫向電連接片49將位於承載 ===上之側面電連接片45、47相連。在所述基板 拉組32内财—縱向電連接片51與所述橫向電連接片49垂 200933867 .直相交並與所述位於外接面板36上之底部電連接片35相 連，該橫向電連接片49用於將連接在承載面板38上半導體 元件34之信號導出。 * 如圖3所示，其為本發明第二實施方式提供之半導體封 裝結構示意圖。從圖中可知，半導體封裝結構包括一基板 模組46及電連接於所述基板模組46上之複數個半導體元件 48。所述基板模組46包括一承載面板50、上外接面板52及 下外接面板54，所述承載面板50、所述上外接面板52及下 Ο外接面板54均為一矩形，所述承載面板50垂直連接於所述 上外接面板52及下外接面板54之間，在本實施方式中，所 述承載面板50於所述上外接面板52及下外接面板54之中軸 線處相連接。是故，所述基板模組46之橫截面為一 “工” 形。 所述上外接面板52分別具有一上表面56及一下表面 58，所述下外接面板54分別具有一頂面60及一底面62。所 述上外接面板52之上表面56及所述下外接面板54之底面62 〇上分別有一頂部電連接片57和一底部電連接片59，基板模 組46藉由所述頂部電連接片57和底部電連接片59與外界裝 置實現電性連接。所述承載面板50具有二個側面64，在所 述二個側面64上分別有一側面電連接片61、63，半導體元 件48藉由所述側面電連接片61、63與基板模組46之間建立 電性連接。 在所述基板模組46内有一橫向電連接片65將位於承載 面板50側面64上之侧面電連接片61、63相連。在所述基板 模組46内還有一縱向電連接片67與所述橫向電連接片65垂 200933867 直相交並分別與位於上外接面板52上之頂部電連接片57及 下外接面板54上之底部電連接片59相連，所述縱向電連接 片67用於將連接在承載面板5〇上半導體元件48之信號導 出0 所述基板模組32 ( 46)之材料可為玻璃纖維，如：環 氧樹脂（Epoxy，俗稱FR4)、聚醯亞胺（Polyimide，俗稱 FR5)、碳氫樹脂（Tefi〇n);強化塑膠，如：杜勞特鉻合 金鋼（Duruid)或陶曼。 ❹ 所述與基板模組32 ( 46)電連接之半導體元件34 ( 64) 為已封裝完成之晶片模組，其可為先前之半導體晶片模 組，例如：薄四方扁平封裝模組（Thin Quad Flat Package， TQFP)、薄型小尺寸封裝（Thin Small Outline Package， TSOP )、小型方塊平面封裝模組（Quad Flat Package，QFP)、 球柵陣列封裝核組（Ball Grid Array Package，BGA)、微 型球柵陣列封裝模組（Micro Ball Grid Array Package， MBGA)、倒裝晶片模組（Flip chip)或晶片級封裝模組（Chip 〇 Scale Package，CSP)等。 所述基板模組32 ( 64)與外界裝置之電連接可藉由表 面組裝技術（Surface Mounted Technology，SMT)、異方 向性導電膠（Anisotropic Conductive Adhesives，ACA)或 異方向性導電膜（Anisotropic Conductive Film，ACF )等 方法來實現。 上述本發明第一實施方式及第二實施方式所提供之半 導體封裝結構可藉由在内部已佈線之整體基板上刻槽、封 裝元件後再切割之方法而制得。 200933867 如圖4A及圖4B所示，其分別為本發明第一實施方式及 -第二實施方式所提供之半導體封裝結構之基板模組32( 64 ) •之切割示意圖。所述整體基板68a( 68b)具有一上表面72a (72b )及一下表面74a ( 74b )，其内部埋設有電連接片鏈 條76a (76b)。分別在所述上表面72a (72b)及下表面74a (74b)之相應位置開設凹槽78a (78b)，凹槽78a(78b)位 置根據所要切割成之基板模組32(64)之形狀不同而不同。 所述凹槽78a(78b)具有一凹槽底面8〇a ( 8〇b )及兩個凹槽 ❹側面82a ( 82b )，在所述凹槽底面8〇a ( 8〇b )之電連接片76a (76b )上封裝半導體元件84，對封裝好之整體基板 (68b)進行測試以確保每個凹槽78a(78b)内之半導體元 件84與整體基板68a (68b)正常連接’最後將測試合格之 整體基板68a (68b)切割成獨立之基板模組32 ( 64)。橫截 面為倒置T ”形之基板模組32為沿著所述凹槽78a邊緣 所在之平面AA、切割而成，橫截面為“工，，形之基板模 組64為沿著所述凹槽78b之間之連接部之中軸面bb、切判 ❹而成。 上述縱向堆疊之半導體封裝結構利用所述基板模祖上 之承載面板將原來半導體晶片之水平層疊封裝轉變為在所 述承載面板側面上之縱向堆疊封裝。相比於先前技術，本 發明提供之半導體封裝結構可令每個半導體元件之封裝過 程同時進行’有效地縮短了制程時間，其次縱向堆疊封裝 避免了各個半導體元件之間膠體之内應力而導致之半導體 封裝結構強度低之問題，同時也避免了因一個半導體元件 損壞而使得整個封裝結構報廢之問題。 11 200933867 、本技術領域之普通技術人員應當認識到，以上之實施 ‘ f式僅係用於說明本發明，而並非用作為對本發明之限 •疋，只要在本發明之實質精神範圍之内，對以上實施方々 内。 炎及變化均洛在本發明要求保護之範圍之 【圖式簡單說明】 圖1為先前疊晶封裝結構示意圖。 ❹意圖圖2為本發明第—實施方式提供之何體封裝結構示 意圖圖3為本發明第二實施方式提供之半導體封裝結構示 圖4A為本發明第—實 之基板模組切割示意圖。只 /提供之半導體封裝結構 圖4B為本發明第二實施 之基板模組切割示意圖。 "提供之半導體封裝結構 ❹ 12 200933867 主要元件符號說明】 第一基板 2 第一導線 6 第三導線 1〇 焊球 14 第一基板 20 第二晶片 22 ©第二封膠 26 底面 30、62 半導體元件 34、48、84 承載面板 38、50 底部電連接片 35、59 橫向電連接片 49、65 頂部電連接片 57 側面 44、64 ©下外接面板 54 凹槽 78a、78b 第一晶片 4 次封裝結構 8 第一封膠 12 上表面 16'40'56'72a ' 72b 下表面 18、42、58、74a、74b 第二導線 24 頂面 28、60 基板模組 32、46 外接面板 36 上外接面板 52 侧面電連接片 45、47、61、63 縱向電連接片 51'67 凹槽侧面 82a、82b 電連接片鍵條 76a ' 76b 凹槽底面 80a ' 80b 整體基板 68a ' 68b 13200933867 IX. Description of the Invention: The technical field to which the invention pertains is, in particular, to a high-density semiconductor package structure in which a semiconductor package is utilized to make full use of space. [Prior Art] With the development of science and technology, the demand for electronic production σ cost control is growing. Wide range of functions, high density and wide range, used for different functions:: chip mode, r, month, for example, microprocessor L Pr〇CeSS〇rS), 1 memory, memory, logic component =, optical integration The circuit (0ptic ICs) and the capacitor (Ca__) are in the same module to replace the single-chip sealing technology. In the prior art, the package structure of the cymbal module is mainly adopted by stacking the stacked wafers on the substrate in order to be sufficient; and the problem that the plurality of crystal grains occupy a large area. J uses a one-dimensional inter-work to reduce the package structure. 1. It is a previous stacked crystal sealing structure, which includes - a plurality of second wires 10, a first sealant 12 and a plurality of solder balls . The first substrate 2 has an upper surface 16 and a lower surface 18. 4 is attached to the upper surface 16 of the first substrate 2 and electrically connected to the first substrate 2 by using the wire 6 and the n-substrate structure 8 ^ a first substrate 2G, a second wafer 22, a plurality of Two wires 24, one brother and two sealants 26. The sub-package structure 8 has a top surface 28 and a bottom surface 3, and the bottom surface 3 of the sub-package structure 8 is adhered to the first wafer 4 of the 200933867 by a glue. In the package structure, the internal forces of the individual wafers will be affected by the stress caused by the different nucleation of the varnishes. In addition, in the process of laminating the crystal, it is a difficult time to locate the nucleus after the bamboo layer is crystallized. In addition, the stacked crystal package must be in the whole crystal = β human forest; 曰 y 〇 〇 〇 测 测 测 测 测 测 , , , 而 而 而 而 而 而 而 而 叠 叠 叠 叠 叠 叠 叠 叠 叠 叠 叠 叠 叠 叠 叠 叠 叠 叠 叠 叠In addition to the influence of factors, it will be covered by each wafer and process. The stacked crystal structure has problems such as low overall strength and low yield. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a vertically stacked semiconductor package structure to solve the problems of the above-described stacked crystal package structure. A semiconductor package structure includes a substrate module and a plurality of semiconductor elements electrically connected to the second core. The substrate module includes a panel, and at least one external panel. The carrier panel and the external connector are vertically connected to each other. The external panel is used to electrically connect the substrate module to an external device, and the carrier panel is configured to carry the semiconductor component electrically connected to the substrate module. - In contrast to the prior art stacked package structure, first, in the fabrication of the semiconductor package structure provided by the present invention, each semiconductor element can be tested before being connected to the 200933867 carrier panel, thereby ensuring the final semiconductor package structure. The rate of good products. Secondly, the semiconductor package structure provided by the present invention avoids the direct bonding between the semiconductor elements, and solves the problem that the strength of the package structure is low due to stress in the glue body. Further, in the fabrication of the semiconductor package structure provided by the present invention, the operation of connecting the semiconductor elements to the carrier panel can be performed simultaneously, which shortens the process time. [Embodiment] FIG. 2 is a schematic view showing a semiconductor package armor structure according to a first embodiment of the present invention. As can be seen from the figure, the semiconductor package structure includes a substrate module 32 and a plurality of semiconductor components 34 electrically connected to the substrate module 32. The substrate module 32 includes an external panel and a carrier panel. The carrier panel 38 and the external panel 36 are each rectangular. The carrier panel 38 and the external panel 36 are on the external panel. The central axis is connected perpendicularly to each other. Therefore, the entire substrate module 3 has a cross section T, shape. The outer panel 36 of the straight material substrate module 32 has an upper surface slightly connected to the material: the lower surface 42 of the panel has a bottom electrical connection piece, and the eight earth plate group 32 is connected to the outside by the bottom electrical connection piece 35. The device is electrically connected. The carrying panel 38 has two side materials, and the side surfaces 44 are respectively electrically connected to the side, and the semiconductor element is established by the side electrical connecting sheets 45 and 47 and the substrate module 32. Electrically, in the substrate module 32, a lateral electrical connection piece 49 connects the side electrical connection pieces 45, 47 on the load ===. In the substrate pull group 32, the fiscal-longitudinal electrical connecting piece 51 and the horizontal electrical connecting piece 49 are perpendicularly connected to each other and connected to the bottom electrical connecting piece 35 on the external panel 36. The horizontal electrical connecting piece 49 is used to derive the signal of the semiconductor component 34 connected to the carrier panel 38. * As shown in FIG. 3, it is a schematic diagram of a semiconductor package structure according to a second embodiment of the present invention. As can be seen from the figure, the semiconductor package structure includes a substrate module 46 and a plurality of semiconductor components 48 electrically connected to the substrate module 46. The substrate module 46 includes a carrying panel 50, an upper outer panel 52, and a lower outer panel 54. The carrying panel 50, the upper outer panel 52, and the lower outer panel 54 are all rectangular, and the carrying panel 50 is The upper and lower outer panels 52 and 54 are vertically connected to each other. In the present embodiment, the load panel 50 is connected to the central axis of the upper outer panel 52 and the lower outer panel 54. Therefore, the cross section of the substrate module 46 is a "work" shape. The upper outer panel 52 has an upper surface 56 and a lower surface 58, respectively. The lower outer panel 54 has a top surface 60 and a bottom surface 62, respectively. The top surface 56 of the upper outer panel 52 and the bottom surface 62 of the lower outer panel 54 respectively have a top electrical connecting piece 57 and a bottom electrical connecting piece 59. The substrate module 46 is connected to the top electrical connecting piece 57. And the bottom electrical connection piece 59 is electrically connected to the external device. The carrying panel 50 has two side faces 64. Each of the two side faces 64 has a side connecting piece 61, 63. The semiconductor component 48 is connected between the side connecting pieces 61 and 63 and the substrate module 46. Establish an electrical connection. A lateral electrical connection piece 65 is disposed in the substrate module 46 to connect the side electrical connecting pieces 61, 63 on the side 64 of the carrying panel 50. In the substrate module 46, a longitudinal electrical connecting piece 67 is directly intersected with the horizontal electrical connecting piece 65 200933867 and respectively connected to the bottom of the top electrical connecting piece 57 and the lower external connecting plate 54 on the upper external connecting plate 52. The electrical connecting tabs 59 are connected to each other. The longitudinal electrical connecting strips 67 are used to derive the signals of the semiconductor components 48 connected to the carrying panel 5. The material of the substrate module 32 (46) may be glass fiber, such as epoxy. Resin (Epoxy, commonly known as FR4), Polyimide (commonly known as FR5), hydrocarbon resin (Tefi〇n); reinforced plastic, such as: Duruid chrome alloy steel (Duruid) or Tauman. The semiconductor component 34 (64) electrically connected to the substrate module 32 (46) is a packaged wafer module, which may be a prior semiconductor wafer module, such as a thin quad flat package module (Thin Quad). Flat Package, TQFP), Thin Small Outline Package (TSOP), Quad Flat Package (QFP), Ball Grid Array Package (BGA), Miniature Ball A Micro Ball Grid Array Package (MBGA), a Flip Chip, or a Chip 〇 Scale Package (CSP). The electrical connection between the substrate module 32 (64) and the external device can be performed by Surface Mounted Technology (SMT), Anisotropic Conductive Adhesives (ACA) or Anisotropic Conductive (Anisotropic Conductive). Film, ACF) and other methods to achieve. The semiconductor package structure according to the first embodiment and the second embodiment of the present invention can be obtained by grooving and sealing a component on a whole substrate which has been internally wired. 200933867 is a schematic view showing the cutting of the substrate module 32 (64) of the semiconductor package structure according to the first embodiment and the second embodiment of the present invention, as shown in FIG. 4A and FIG. 4B. The unitary substrate 68a (68b) has an upper surface 72a (72b) and a lower surface 74a (74b), and an electrical connection strip chain 76a (76b) is embedded therein. Grooves 78a (78b) are formed at respective positions of the upper surface 72a (72b) and the lower surface 74a (74b), and the positions of the recesses 78a (78b) are different according to the shape of the substrate module 32 (64) to be cut. And different. The groove 78a (78b) has a groove bottom surface 8〇a (8〇b) and two groove side surfaces 82a (82b), and electrical connection at the bottom surface 8〇a (8〇b) of the groove The semiconductor component 84 is packaged on the sheet 76a (76b), and the packaged integral substrate (68b) is tested to ensure that the semiconductor component 84 in each of the recesses 78a (78b) is properly connected to the integral substrate 68a (68b). The qualified integral substrate 68a (68b) is cut into individual substrate modules 32 (64). The substrate module 32 having an inverted T" shape is cut along a plane AA along the edge of the groove 78a, and the cross section is "work," and the substrate module 64 is formed along the groove. The axial surface bb of the joint between the 78b is cut and cut. The vertically stacked semiconductor package structure utilizes a carrier panel on the substrate die to convert a horizontal stacked package of the original semiconductor wafer into a vertically stacked package on the side of the carrier panel. Compared with the prior art, the semiconductor package structure provided by the present invention can make the packaging process of each semiconductor element simultaneously 'effectively shorten the process time, and the vertical stacking package avoids the internal stress of the colloid between the semiconductor elements. The problem of low strength of the semiconductor package structure also avoids the problem that the entire package structure is scrapped due to damage of one semiconductor element. 11 200933867, those skilled in the art will recognize that the above embodiments are merely illustrative of the invention and are not intended to limit the scope of the invention, as long as it is within the spirit of the invention. For the above implementations. The inflammation and the variation are within the scope of the claimed invention. [Schematic Description of the Drawings] FIG. 1 is a schematic view of a prior art stacked crystal package structure. 2 is a schematic view of a semiconductor package structure according to a second embodiment of the present invention. FIG. 4A is a schematic view showing a first embodiment of the present invention. Only/provided semiconductor package structure Fig. 4B is a schematic view showing the cutting of the substrate module of the second embodiment of the present invention. "Semiconductor package structure provided ❹ 12 200933867 Main component symbol description] First substrate 2 First wire 6 Third wire 1 〇 solder ball 14 First substrate 20 Second wafer 22 © Second seal 26 Bottom surface 30, 62 Semiconductor Components 34, 48, 84 Carrier Panels 38, 50 Bottom Electrical Connections 35, 59 Transverse Electrical Connections 49, 65 Top Electrical Connections 57 Sides 44, 64 © Lower External Panel 54 Grooves 78a, 78b First Wafer 4 Package Structure 8 First adhesive 12 Upper surface 16'40'56'72a '72b Lower surface 18, 42, 58, 74a, 74b Second lead 24 Top surface 28, 60 Substrate module 32, 46 External panel 36 External panel 52 side electrical connecting pieces 45, 47, 61, 63 longitudinal electrical connecting piece 51'67 groove side 82a, 82b electrically connecting the sheet key strip 76a ' 76b groove bottom surface 80a ' 80b integral substrate 68a ' 68b 13