CN106449612A - Stacking and packaging structure for memory chips - Google Patents
Stacking and packaging structure for memory chips Download PDFInfo
- Publication number
- CN106449612A CN106449612A CN201610708849.3A CN201610708849A CN106449612A CN 106449612 A CN106449612 A CN 106449612A CN 201610708849 A CN201610708849 A CN 201610708849A CN 106449612 A CN106449612 A CN 106449612A
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- chip
- keyset
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- solder joint
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a stacking and packaging structure for memory chips. The stacking and packaging structure comprises a substrate with a two-sided signal layer, wherein a transfer board is connected between every two adjacent to-be-packaged chips; a window for wiring is formed in the middle of each transfer board; a welding point, close to the corresponding window, on each to-be-packaged chip passes through the window of the transfer board positioned above the chip to be welded on the transfer board through a gold wire; and the transfer boards and the substrate are welded through gold wires. By virtue of the transfer boards, the welding points are distributed from the centers of the chips to the peripheries, so that utilization of a wafer-level technological process is avoided, the technological difficulty is lowered and the cost is lowered consequently; in addition, the interconnection between chips and the transfer boards is realized firstly, so that the dimensions of the transfer boards can be set according to requirements; the dimensions of the transfer boards of the lower layer chips can be enlarged, so that perpendicular distribution of the gold wires and the upper layer chips is avoided; and furthermore, a special film, in which the gold wires can be embedded, is avoided, so that the cost is lowered and the technological difficulty is lowered.
Description
Technical field
The invention belongs to technical field of semiconductor encapsulation, in particular to a kind of memory chip stack package structure.
Background technology
Flourish with electronic industry, electronics technology constantly evolution, electronic product is also towards light, thin, short, little
Trend designs.With the increase of microminiaturization and high operating techniques demand, multiple chips can be incorporated in a packaging structure, with
Reach the capacity of more than twice or systematic functional requirement, such as, in conventional Multichip stacking encapsulation constructs, it is
By multiple chip-stacked and sealing in an encapsulating material.Common chip welding spot position distribution in chip edge, easy gold thread
Welding, it is achieved stacked package, but the memory chip in the middle of chip is positioned at for solder joint, such as dynamic RAM (Dynamic
Radom Access Memory, memory chip) for, it is achieved stacked package is relatively difficult.
It is said that in general, storage core flake products, it is known that single-chip package technology among common structure as shown in Figure 1,
Chip tips upside down on substrate.It mainly comprises a substrate 5a, and on this substrate 5a, back-off one chip 1a, substrate 5a has a window
8a, welds a plurality of bonding wire 3a in substrate window 8a, and for the connection of chip 1a and substrate circuit, chip 1a and substrate 5a pushes up
End plastic packaging material 6a parcel.And a plurality of external terminal 4a is set on substrate, for the connection of substrate circuit and external circuit.
In said structure, owing to memory chip solder joint is positioned at chip central authorities, by welding gold thread 3a in the 8a that windows
Form realizes the electric connection of chip, practical reliable.But this package body structure known, can only carry out the encapsulation of single-chip, no
Stacking can be realized.For realizing that capacity is double, improving packaging density, those skilled in the art considers to use and stores as shown in Figure 2
Device chip stack package structure.
In fig. 2, two stacked chips realize that front mounts, it was demonstrated that welding gold thread 14b and 3b, therefore substrate 5b is complete base
Plate structure, it is no longer necessary to window welds for gold thread.In this encapsulating structure, comprise a complete substrate 5b, substrate 5b following table
Face is similarly external terminal 4b.Except for the difference that, before lower layer chip 1b with upper strata chip 2b paster, need to carry out external solder joint
Redistribution, the solder joint that will be located in memory chip center is redistributed to chip surrounding, makes memory chip organization meet weldering
Point surrounding, can carry out direct stacked package.Owing to lower layer chip 1b is identical with upper strata chip 2b size, therefore lower floor's core
Should there is a kind of special film 7b between piece 1b and upper strata chip 2b, during upper strata chip 2b attachment, the gold of welding in lower layer chip 1b
Line 14b can be embedded into this tunic 7b inside and gold thread is not impaired, and can bond again upper and lower layers of chips.The upper and lower equal gold thread of layers of chips
After welding completes, by resin 6b encapsulating protection.
This package body structure, two chips all achieve stacked package in the way of the attachment of front, but, in this stacked package
In body structure, the solder joint of two chips is required to redistribution, belongs to wafer Wiring technique again, and by disk, factory completes, equipment, technology
Cost requirement is higher, needs mask plate customized, expensive.In addition, in the stack package structure of Fig. 2, be used for being bonded with down
The film of layers of chips, gold thread can embed, expensive, and mount technology requires relatively for paster (DIE Bond) craft precision
Height, all adds technology difficulty, it is achieved cost is high.
As can be seen here, above-mentioned known multi-chip package technology can realize that memory chip capacity is double, improves chip
Packaging density, but expensive, it is not provided simultaneously with the high function of high I/O density and the demand of low cost.
Content of the invention
Present invention aim to overcome that above-mentioned the deficiencies in the prior art provide a kind of memory chip stack package structure,
This encapsulating structure is in the case of improving packaging body chip density, and technique realizes that difficulty is relatively low.
Realize that the object of the invention employed technical scheme comprise that a kind of memory chip stack package structure, including have two sides
The substrate of signals layer, is connected with keyset between the adjacent chip to be packaged of each two, and the middle part of described keyset has use
On the window of routing, each chip to be packaged, the solder joint near window is placed through the window of keyset above this chip and turns
Fishplate bar is welded by gold thread；Described keyset and substrate are welded by gold thread.
The present invention by keyset realize solder joint by chip central distribution to surrounding, thus avoid use wafer level technique skill
Art, reduces technology difficulty, thus reduces cost.Further, since first realize the interconnection of chip and keyset, the chi of keyset
Very little can arrange according to demand, the keyset size of lower layer chip can be done greatly, it is to avoid gold thread divides with upper strata Chip Vertical
Cloth, can not use the special film that gold thread can embed, and reduces price, reduces technology difficulty.
Brief description
Fig. 1 is known a kind of memory chip single die package schematic diagram.
Fig. 2 is existing a kind of memory chip Multichip stacking encapsulation structural representation.
Fig. 3 is based on a cross-sectional view of memory chip stack package structure of the present invention.
Fig. 4 is based on the top of keyset in a kind of memory chip stack package structure being realized by keyset of the present invention
Face schematic diagram.
Detailed description of the invention
As it is shown on figure 3, memory chip stack package structure of the present invention is application keyset, combine cheap routing key
Conjunction technology (Wire Bonding) will at least be set together in layers of chips stacking combination, and avoid price height, complex process
Disk Wiring technique again, i.e. add I/O density and the function of packaging body, reduce the realisation difficulty of technique, reduce life
Produce cost.
By technological means and effect that the present invention by reach predetermined goal of the invention taked is expanded on further, below in conjunction with attached
Figure and preferred embodiment, to according to its detailed description of the invention of multichip packaging structure of the present invention, structure, feature and effect thereof,
After describing in detail such as.
According to first specific embodiment of the present invention, disclosing a kind of memory chip stack package structure, Fig. 3 is that this deposits more
The schematic cross-section of memory chip stack package structure, Fig. 4 is keyset in this multi-memory chip stack package structure
End face schematic diagram.
Referring initially to shown in accompanying drawing 3 and Fig. 4, this stack package structure its be illustrated as the present invention preferably implement structure,
The memory chip stacked package body of the present invention, mainly comprises a substrate 5c, lower layer chip 1c, a upper strata chip 2c, majority
Individual external terminal solder ball 4c, once keyset 12c, two pad 13c, keyset 17c on.Keyset used by the present invention
Meet the universal of wiring board, but typically only have face line layer, between the inside and outside pin welding for gold thread and inside and outside pin
Lead-in wire, is respectively positioned on this sandwich circuit layer.
This example memory chip stack package structure technique realizes：
Upper and lower layers of chips (2c, 1c) is adhered on the keyset 12c that separately designs, the switching of upper and lower two chips
Board size can be identical, it is also possible to different.It is mounted on lower layer chip 1c being bonded on lower keyset 12c on substrate 5c, profit
Realize the welding of lower layer chip 1c and lower keyset 12c with the gold thread 15c in the window 8d opening on lower keyset 12c, by gold
Line 14c realizes the electrical interconnection of lower keyset 12c and substrate 5c, indirectly achieves electrically connecting of lower layer chip 1c and substrate 5c
Connect.
Upper surface at lower keyset 12c pastes two pad 13c, in order to support and to be bonded with chip 2c.By upper strata core
Piece 2c affixes on pad 13c, equally, utilizes window 8d reserved on the keyset 17c above the chip 2c of upper strata to carry out upper strata
The gold thread 16c welding of chip 2c, then carry out the welding to the gold thread 3c between substrate 5c for the upper keyset 17c.Application claims pad
The height more than gold thread 15c for the thickness of piece 13c, during in order to protect upper strata chip 2c to mount, gold thread 15c is injury-free.Gold thread welds
Connect after completing, carry out the parcel of plastic packaging material 6c to whole packaging body, including what region on the upside of chip, substrate and keyset were windowed
Region, whole packaging body plants external terminal 4c, for the external electrical connection of whole packaging body.
As shown in Figure 4, it, in above-mentioned lower keyset 12c structure, is distributed according to solder joint in lower layer chip 1c, at lower keyset
Fenestration 8d is made, it is achieved solder joint is at the gold thread 15c welding of internal chip and lower keyset 12c, lower keyset on 12c
12c is welded by gold thread 14c with substrate 5c, indirectly realize the electrical connection of lower layer chip 1c and substrate 5c, it is to avoid wafer is again
The complicated processing procedure of Wiring technique, reduces expense.
By designing the size of keyset, pin solder joint 11d outer on lower keyset 12c is positioned over fan-out upper strata chip 2c
Region, such upper strata chip 2c paste when, do not interfere with gold thread 14c region.The surrounding of fenestration 8d in lower keyset 12c
Being dispersed with the interior pin solder joint 10d for gold thread welding, in these, solder joint directly and in lower layer chip 2c for the solder joint passes through gold thread
15c connects.Be dispersed with the outer pin solder joint 11d of equal number in the edge of keyset 12c, interior pin solder joint 10d with draw outward
Pin solder joint 11d one_to_one corresponding, the solder joint on outer pin solder joint 11d and substrate 5c realizes electrical connection, lower keyset by gold thread
Inside and outside solder joint on 12c is realized by wiring on keyset.
The logical principle of electrical connection of upper keyset 17c and upper strata chip 2c is same as electrically connecting of lower keyset and lower layer chip
Connecing, here is omitted.
Lower layer chip 1c is positioned at the gold thread 15c of window 8c, supports protection by two pad 13c, therefore also will not be because of upper
Layer chip attachment and impaired.Being applied in combination of the two structure, it is to avoid use the film allowing gold thread embedded, saved cost,
Reduce technique and realize difficulty.
The stacked package of two keysets is used to be illustrated only for two chips above, encapsulating structure of the present invention
It is applicable to the stacked package of multiple chip, when number of chips is more than two, need the keyset identical with number of chips to carry out
Stacking uses, and concrete structure is same as the previously described embodiments with using method, and here is omitted.
The above, be only presently preferred embodiments of the present invention, not does any pro forma restriction to the present invention, though
The right present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any technology people being familiar with this specialty
Member, in the range of without departing from technical solution of the present invention, when the technology contents of available the disclosure above makes a little change or modification
For the Equivalent embodiments of equivalent variations, as long as being the content without departing from technical solution of the present invention, according to the technical spirit of the present invention
To any simple modification made for any of the above embodiments, equivalent variations and modification, in the range of all still falling within technical solution of the present invention.
Claims (3)
1. a memory chip stack package structure, including have the substrate of two sides signals layer, is characterised by：Adjacent in each two
Being connected with keyset between the chip to be packaged connecing, the middle part of described keyset has the window for routing, and each is to be packaged
On chip, the solder joint near window is placed through the window of keyset above this chip and keyset is welded by gold thread；Described turn
Fishplate bar is welded by gold thread with substrate.
2. memory chip stack package structure according to claim 1, it is characterised in that：Keyset be connected to this switching
Being provided with pad between the chip of plate upper surface, described spacer thickness is more than the height by the gold thread of welding at this keyset window
Degree.
3. memory chip stack package structure according to claim 2, it is characterised in that：Near window on described keyset
Position be provided with multiple interior pin solder joint, keyset edge is provided with the outer pin weldering that multiple and described interior pin solder joint is connected
Point；On each chip to be packaged described, the solder joint near window is placed through window and this keyset of keyset above this chip
On interior pin solder joint welded by gold thread；Outer pin solder joint realizes electrical connection with the solder joint on substrate by gold thread.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610708849.3A CN106449612A (en) | 2016-08-23 | 2016-08-23 | Stacking and packaging structure for memory chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610708849.3A CN106449612A (en) | 2016-08-23 | 2016-08-23 | Stacking and packaging structure for memory chips |
Publications (1)
| Publication Number | Publication Date |
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| CN106449612A true CN106449612A (en) | 2017-02-22 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610708849.3A Pending CN106449612A (en) | 2016-08-23 | 2016-08-23 | Stacking and packaging structure for memory chips |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109581202A (en) * | 2017-09-28 | 2019-04-05 | 华为技术有限公司 | The test device and test macro of stacked package |
| CN112234026A (en) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | 3D chip package |
| CN114566456A (en) * | 2022-04-29 | 2022-05-31 | 深圳市铨天科技有限公司 | Packaging equipment for multilayer stacked storage chips |
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| US20040061211A1 (en) * | 2002-10-01 | 2004-04-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor package |
| CN101315922A (en) * | 2007-05-30 | 2008-12-03 | 力成科技股份有限公司 | Semiconductor packaging stack device for preventing semiconductor stack from micro-contact soldering point rupture |
| CN103236425A (en) * | 2013-04-23 | 2013-08-07 | 山东华芯半导体有限公司 | DRAM (dynamic random access memory) double-chip stacking and packaging structure and packaging technology |
| CN206022359U (en) * | 2016-08-23 | 2017-03-15 | 武汉寻泉科技有限公司 | Memory chip stack package structure |
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2016
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| US20040061211A1 (en) * | 2002-10-01 | 2004-04-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor package |
| CN101315922A (en) * | 2007-05-30 | 2008-12-03 | 力成科技股份有限公司 | Semiconductor packaging stack device for preventing semiconductor stack from micro-contact soldering point rupture |
| CN103236425A (en) * | 2013-04-23 | 2013-08-07 | 山东华芯半导体有限公司 | DRAM (dynamic random access memory) double-chip stacking and packaging structure and packaging technology |
| CN206022359U (en) * | 2016-08-23 | 2017-03-15 | 武汉寻泉科技有限公司 | Memory chip stack package structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109581202A (en) * | 2017-09-28 | 2019-04-05 | 华为技术有限公司 | The test device and test macro of stacked package |
| CN109581202B (en) * | 2017-09-28 | 2020-07-07 | 华为技术有限公司 | Testing device and testing system for laminated package |
| CN112234026A (en) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | 3D chip package |
| CN114566456A (en) * | 2022-04-29 | 2022-05-31 | 深圳市铨天科技有限公司 | Packaging equipment for multilayer stacked storage chips |
| CN114566456B (en) * | 2022-04-29 | 2022-08-23 | 深圳市铨天科技有限公司 | Packaging equipment for multilayer stacked storage chips |
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Application publication date: 20170222 |