CN101315922A - Semiconductor packaging stack device for preventing semiconductor stack from micro-contact soldering point rupture - Google Patents
Semiconductor packaging stack device for preventing semiconductor stack from micro-contact soldering point rupture Download PDFInfo
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- CN101315922A CN101315922A CN 200710106720 CN200710106720A CN101315922A CN 101315922 A CN101315922 A CN 101315922A CN 200710106720 CN200710106720 CN 200710106720 CN 200710106720 A CN200710106720 A CN 200710106720A CN 101315922 A CN101315922 A CN 101315922A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
Abstract
The invention relates to a semiconductor package stacking device for avoiding the occurrence of broken micro-contact welding points during the semiconductor stacking. The semiconductor package stacking device mainly comprises a plurality of semiconductor package parts with the micro-contact welding points and solders for welding the micro-contact welding points. Each semiconductor package part comprises a substrate and a wafer on the substrate. The micro-contact welding points of the lower semiconductor package parts are a plurality of upper layer of convex blocks which are positioned at the upper surfaces of the substrates thereof; and the micro-contact welding points of the upper semiconductor package parts are a plurality of lower layer of convex blocks which are positioned at the lower surfaces of the substrates thereof, wherein, the lower layer of convex blocks can be aligned to the upper layer of convex blocks, thus allowing the solders to bond the upper layer of convex blocks and the lower layer of convex blocks. Thereby, the same solder bonding shape and the area of the upper layer of convex blocks and the lower layer of convex blocks are provided, thus being conductive to even welding and avoiding the occurrence of broken micro-contact welding points during the semiconductor stacking.
Description
Technical field
The present invention relates to a kind of framework that a plurality of semiconductor package part high density 3D are piled up, particularly relate to a kind of can homogenizing solder bonds shape and area, can reach and avoid the semiconductor stack from micro-contact soldering point rupture effect, in addition can also with the semiconductor packaging stack device of avoiding semiconductor stack from micro-contact soldering point rupture of thermal diffusivity and little distance maintaining effect (Package-On-Packagedevice, POP).
Background technology
When a circuit board more and more hour, its surface can also dwindle for the area of installation elements.Can directly join a plurality of semiconductor package parts to circuit board in (side-by-side) mode side by side in the past, and advanced microminiaturization electronic product can't be reached, so there is the people to propose and the vertical 3D of a plurality of semiconductor package parts can be piled up, to meet the requirement that small-sized surperficial bonding area and high density components are provided with, promptly be referred to as semiconductor packaging stack device (Package-On-Package device, POP).Changeover mechanism at two semiconductor package parts is the keyset that soldered ball or upper and lower surface all have scolder at present, adopt soldered ball except having breakage problem, soldered ball must become can provide greatly and piles up at interval, so be easy to generate soldered ball bridge joint and scolder pollution problems, and existing known interval soldered ball can't reach the kenel of little contact, and causes pin count and cabling wiring to be restricted.Adopt keyset, then must establish ccontaining open slot in the middle of keyset, and the periphery of open slot is provided with via, the element cost is higher.
Fujitsu company respectively proposes a kind of little contact framework that can be applicable to encapsulation stacking at No. the 6476503rd, United States Patent (USP) and Tessera company for No. 2006/0138647 in U.S. Patent Publication.Seeing also shown in Figure 1ly, is a kind of schematic cross-section of existing known semiconductor packaging stack device.Existing known semiconductor packaging stack device 100, mainly comprise one first semiconductor package part 110, one second semiconductor package part 120 and scolder 130, wherein, this second semiconductor package part 120 is to be stacked on this first semiconductor package part 110, and connects two semiconductor packaging parts 110 and 120 with scolder 130.This first semiconductor package part 110 has first wafer 112 and a plurality of projection 113 that is formed at a lower surface 111B of this substrate that one first substrate 111, is arranged at a upper surface 111A of this first substrate 111.Utilize the one first slotted eye 111C of a plurality of first bonding wires 114 by this first substrate 111, with the weld pad that electrically connects this first wafer 112 to this first substrate 111, and with one first adhesive body, 115 those first bonding wires 114 of sealing.As this first semiconductor package part 110, this second semiconductor package part 120, have one second substrate 121, and be arranged at second wafer 122 and a plurality of projection 123 that is formed at a lower surface 121B of this substrate of a upper surface 121A of this second substrate 121, for example the column-like projection block that copper bump or other can not reflows.A plurality of second bonding wires 124 pass through one second slotted eye 121C of this second substrate 121, and electrically connect this second wafer 122 to this second substrate 121, and with one second adhesive body, 125 those second bonding wires 124 of sealing.Prior art is the connection gasket 111D that are provided with a plurality of plain cushion shapes at the upper surface 111A of this first substrate 111 of this first semiconductor package part 110, engage the corresponding connection gasket 111D of those projections 123 of this second semiconductor package part 120 by those scolders 130 to this first semiconductor package part 110, use and reach little contacting structure kenel, when packaging part 110 and 120 piles up with those projections 123 as the microminiaturization contact, can increase signal pin count (high pin count) and can increase the cabling area, more can dwindle encapsulation stacking gap (small POP stacking standoff).
Because both are inequality for the weld strength of those projections 123 and for the weld strength of those connection gaskets 111D after reflow for the joint shape of welding and not the matching of area, scolder 130.Particularly, this scolder 130 is plane at the face of weld of those connection gaskets 111D, for cut to the resistance of stress (i.e. first substrate 111 expand with heat and contract with cold and produce thermal stress) a little less than.In addition, the surface that has known those connection gaskets 111D now is to be electroplate with nickel-gold layer, and the gold layer can fuse into and produce golden crisp effect in the scolder 130, and it is weaker that the intensity of weld interface will become.Therefore, when existing known semiconductor packaging stack device 100 under high-speed computation or be in the heat radiation bad environment, easily at those connection gaskets 111D and scolder 130 contact interfaces, or the surface of projection 123 produces little contact solder joint and ruptures.
This shows that above-mentioned conventional semiconductor packages stack device obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.For solving the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of semiconductor packaging stack device of avoiding semiconductor stack from micro-contact soldering point rupture of new structure, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned conventional semiconductor packages stack device exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and cooperate scientific principle to use, actively studied innovation, in the hope of founding a kind of semiconductor packaging stack device of avoiding semiconductor stack from micro-contact soldering point rupture of new structure, can improve the conventional semiconductor packages stack device, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present invention is, overcome the existing defective of conventional semiconductor packages stack device, and provide a kind of semiconductor packaging stack device of avoiding semiconductor stack from micro-contact soldering point rupture of new structure, technical problem to be solved is to make it can homogenizing solder bonds shape and area, and can reach the effect of avoiding semiconductor stack from micro-contact soldering point rupture, be very suitable for practicality.
Another object of the present invention is to, a kind of semiconductor packaging stack device of avoiding semiconductor stack from micro-contact soldering point rupture is provided, technical problem to be solved is to make it can be with the effect of thermal diffusivity and little distance maintaining, thereby is suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of semiconductor packaging stack device according to the present invention's proposition, it comprises: one first semiconductor package part, it comprises one first substrate, one first wafer and a plurality of upper stratas projection, and wherein those upper strata projections and this first wafer are upper surfaces that is arranged at this first substrate; One second semiconductor package part, it comprises one second substrate, one second wafer and a plurality of lower floors projection, and wherein those lower floor's projections are a lower surface that are arranged at this second substrate, and this second wafer is a upper surface that is arranged at this second substrate; And a plurality of scolders, it engages those upper strata projections and those lower floor's projections; Wherein, this second semiconductor package part is folded being located on this first semiconductor package part, and makes those lower floor's projections in alignment with those upper strata projections, in order to even welding.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor packaging stack device, wherein said first semiconductor package part more comprise a plurality of second lower floor's projections, and those second lower floor projections are a lower surface that are arranged at this first substrate.
Aforesaid semiconductor packaging stack device, it comprises second scolder in addition, and it is to coat those second lower floor projections.
Aforesaid semiconductor packaging stack device, wherein said second semiconductor package part more comprise a plurality of second upper strata projections, and those second upper strata projections are upper surfaces that are arranged at this second substrate.
Aforesaid semiconductor packaging stack device, wherein said first semiconductor package part more comprises a plurality of first bonding wires, this first substrate is to have one first slotted eye, and those first bonding wires are to electrically connect this first wafer and this first substrate by this first slotted eye.
Aforesaid semiconductor packaging stack device, wherein said first semiconductor package part more comprises one first adhesive body, and it is to be formed at this first slotted eye, to seal those first bonding wires.
Aforesaid semiconductor packaging stack device, wherein said first adhesive body are not cover this first wafer.
Aforesaid semiconductor packaging stack device, wherein said second semiconductor package part are that essence is same as this first semiconductor packages, and include a plurality of second bonding wires and one second adhesive body.
Aforesaid semiconductor packaging stack device, wherein said those lower floor's projections and those upper strata projections are to have same size and profile.
Aforesaid semiconductor packaging stack device, wherein said those lower floor's projections and those upper strata projections are to have the half-cone cross section.
Aforesaid semiconductor packaging stack device, wherein said those lower floor's projections and those upper strata projections are to be the copper post.
Aforesaid semiconductor packaging stack device, wherein said second semiconductor package part have a plurality of void and put projection, and it is arranged at the lower surface of this second substrate, and are positioned at this first wafer top of this first semiconductor package part, for heat radiation.
Aforesaid semiconductor packaging stack device, wherein said those void are put the back side that projection is this first wafer of contact.
Aforesaid semiconductor packaging stack device, wherein said those scolders have H shape welded section.
Aforesaid semiconductor packaging stack device, wherein said those scolders are to be unleaded solder.
The object of the invention to solve the technical problems also realizes by the following technical solutions.A kind of semiconductor packaging stack device according to the present invention's proposition, it comprises a plurality of semiconductor package parts that pile up mutually, each semiconductor package part comprises a substrate, a wafer, a plurality of lower floors projection and a plurality of upper stratas projection, wherein those first lower floor projections are a lower surface that are arranged at this substrate, those upper strata projections and this wafer are upper surfaces that is arranged at this substrate, and those upper strata projections are to have identical solder bonds shape and area with those lower floor's projections.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor packaging stack device, the solder bonds shape of wherein said those upper strata projections and those lower floor's projections are the U-shapeds that enlarge for opening.
Aforesaid semiconductor packaging stack device, wherein said each semiconductor package part more comprises a plurality of bonding wires, and this substrate is to have a slotted eye, and those bonding wires are to electrically connect this wafer and this substrate by this slotted eye.
Aforesaid semiconductor packaging stack device, wherein said each semiconductor package part more comprises an adhesive body, and it is to be formed at this slotted eye, to seal those bonding wires.
Aforesaid semiconductor packaging stack device, wherein said each adhesive body is not cover this wafer.
Aforesaid semiconductor packaging stack device, wherein said those lower floor's projections and those upper strata projections are to have the half-cone cross section.
Aforesaid semiconductor packaging stack device, wherein said those lower floor's projections and those upper strata projections are to be the copper post.
Aforesaid semiconductor packaging stack device, wherein said each semiconductor package part have a plurality of void and put projection, and it is a lower surface of being located at this substrate, for heat radiation.
The present invention compared with prior art has tangible advantage and beneficial effect.By technique scheme, the present invention avoids the semiconductor packaging stack device of semiconductor stack from micro-contact soldering point rupture to have following advantage and beneficial effect at least:
1, the present invention can homogenizing solder bonds shape and area, and can reach the good effect of avoiding semiconductor stack from micro-contact soldering point rupture, is very suitable for practicality.
2, the present invention can also be with the good effect of thermal diffusivity and little distance maintaining, thereby is suitable for practicality more.
In sum, the present invention is relevant a kind of semiconductor packaging stack device of avoiding semiconductor stack from micro-contact soldering point rupture.This semiconductor packaging stack device mainly comprises the semiconductor package part of a plurality of little contact solder joints and welds this scolder of Contact welding point slightly.Each semiconductor package part comprises the wafer of a substrate and on substrate.Little contact solder joint of lower semiconductor packaging part is that the position is at a plurality of upper strata projections that are positioned at its upper surface of base plate; Little contact solder joint of top semiconductor package part is that the position is at a plurality of lower floor's projections that are positioned at its base lower surface.Wherein, those lower floor's projections are to be aligned in those upper strata projections, make those upper strata projections of those solder bonds and those lower floor's projections.Therefore those upper strata projections provide identical solder bonds shape and area with those lower floor's projections, and can avoid semiconductor stack from micro-contact soldering point rupture in order to even welding.The present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure or function, obvious improvement is arranged technically, and produced handy and practical effect, and the outstanding effect that has enhancement than the conventional semiconductor packages stack device, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is a kind of schematic cross-section that has known semiconductor packaging stack device now.
Fig. 2 is the schematic cross-section according to a kind of semiconductor packaging stack device of the present invention's first specific embodiment.
Fig. 3 is according to the present invention's first specific embodiment, and first semiconductor package part and second semiconductor package part are in the schematic partial cross-sectional view at solder bonds place in this semiconductor packaging stack device.
Fig. 4 is according to the present invention's first specific embodiment, can be engaged to the schematic cross-section an of the external circuit board by the semiconductor packaging stack device that a plurality of semiconductor package parts are formed.
Fig. 5 is according to the present invention's second specific embodiment, the schematic cross-section of another kind of semiconductor packaging stack device.
10: circuit board 100: semiconductor packaging stack device
111: the first substrates of 110: the first semiconductor package parts
111A: upper surface 111B: lower surface
111C: the first slotted eye 111D: connection gasket
Wafer 113 in 112: the first: projection
115: the first adhesive bodies of 114: the first bonding wires
121: the second substrates of 120: the second semiconductor package parts
121A: upper surface 121B: lower surface
121C: 122: the second wafers of second slotted eye
123: 124: the second bonding wires of projection
200: 210: the first semiconductor package parts of semiconductor packaging stack device
211: the first substrate 211A: upper surface
211B: lower surface 211C: first slotted eye
212: the first wafer 212A: first weld pad
214: the second lower floor's projections of 213: the first upper strata projections
216: the first adhesive bodies of 215: the first bonding wires
221: the second substrates of 220: the second semiconductor package parts
221A: upper surface 221B: lower surface
221C: 222: the second wafers of second slotted eye
222A: 223: the first lower floor's projections of second weld pad
225: the second bonding wires of 224: the second upper strata projections
311: the first substrates of 310: the first semiconductor package parts
311A: upper surface 311B: lower surface
314: 320: the second semiconductor package parts of lower floor's projection
321: the second substrate 321A: upper surface
321B: 322: the second wafers of lower surface
323: lower floor's projection 324: void is put projection
340: the second scolders of 330: the first scolders
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of the semiconductor packaging stack device of avoiding semiconductor stack from micro-contact soldering point rupture, structure, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
According to first specific embodiment of the present invention, disclosed a kind of semiconductor packaging stack device of avoiding semiconductor stack from micro-contact soldering point rupture.Seeing also shown in Figure 2ly, is the schematic cross-section according to a kind of semiconductor packaging stack device of the present invention's first specific embodiment.A kind of semiconductor packaging stack device 200 of the present invention's first specific embodiment mainly comprises one first semiconductor package part 210, one second semiconductor package part 220 and a plurality of scolder 230.
The first above-mentioned semiconductor package part 210 mainly comprises one first substrate 211, one first wafer 212 and a plurality of first upper strata projection 213, wherein:
This first substrate 211 is the circuit board for double-side conduction, for example printed circuit board (PCB).
Those first upper strata projections 213 and this first wafer 212 are upper surface 211A that are arranged at this first substrate 211.The active surface of this first wafer 212 is towards this first substrate 211, is bonded on the upper surface 211A of this first substrate 211 with sticking brilliant glue, adhesive tape or chip-covered boss.
In the present embodiment, this first substrate 211 is to have one first slotted eye 211C, and it is upper surface 211A and the lower surface 211B that runs through this first substrate 211.And this first semiconductor package part 210 can more comprise a plurality of first bonding wires 215, and those first bonding wires 215 are to form in the routing mode, electrically connects a plurality of first weld pad 212A and this first substrate 211 of this first wafer 212 by this first slotted eye 211C.
This first semiconductor package part 210 can more comprise one first adhesive body 216, with pressing mold or some glue mode, makes it be formed at this first slotted eye 211C, to seal those first bonding wires 215.This first adhesive body 216 is not cover this first wafer 212, so that the back side of this first wafer 212, helps heat radiation and encapsulation thinning for appearing.
The second above-mentioned semiconductor package part 220 comprises one second substrate 221, one second wafer 222 and a plurality of first lower floor's projection 223, wherein:
This second wafer 222 is upper surface 221A that are arranged at this second substrate 221;
Those first lower floor projections 223 are a lower surface 221B that are arranged at this second substrate 221.
Preferably, be same as this first semiconductor package part 210 but this second semiconductor package part 220 is an essence, and include a plurality of second bonding wires 225 and one second adhesive body 226.Those second bonding wires 225 are a plurality of second weld pad 222A and this second substrates 221 that electrically connect this second wafer 222 by this second slotted eye 221C, and are sealed by this second adhesive body 226.
In the present embodiment, this first semiconductor package part 210 can more comprise a plurality of second lower floor's projections 214, and those second lower floor projections 214 are arranged at a lower surface 211B of this first substrate 211.This second semiconductor package part 220 can more comprise a plurality of second upper strata projections 224, and those second upper strata projections 224 are upper surface 221A that are arranged at this second substrate 221.
Those above-mentioned scolders 230 are to engage those first upper strata projections 213 and those first lower floor projections 223.Wherein, this second semiconductor package part 220 is folded being located on this first semiconductor package part 210, and makes those first lower floor projections 223 in alignment with those first upper strata projections 213, in order to even welding.Usually those scolders 230 are to can be unleaded solder, scolder with tin 96.5%-silver 3%-copper 0.5%, arrive more than reflow temperature 217 degree Celsius approximately, the highest temperature is about Celsius 245 can produce the wettability of welding when spending, yet those first upper strata projections 213 must have the fusing point that is higher than above-mentioned reflow temperature with those first lower floor projections 223.
Seeing also shown in Figure 3ly, is according to the present invention's first specific embodiment, and first semiconductor package part and second semiconductor package part are in the schematic partial cross-sectional view at solder bonds place in this semiconductor packaging stack device.Those first lower floor projections 223 and those first upper strata projections 213, be to have same size and profile, for example those first lower floor projections 223 can have the half-cone cross section with those first upper strata projections 213, as semicircle cone or prismatoid, also can be the tie lines projection that routing forms.Those first lower floor projections 223 can be the copper post with those first upper strata projections 213 or other does not need the projection of reflow.Those first lower floor projections 223 are to have little kenel that contacts with those first upper strata projections 213.
The employed window type ball grid array encapsulation construction of Dynamic Random Access Memory (wBGA) with the existing known double data transmission rate second generation (DDR2) is an example, the tin bulb diameter that has known packaging structure now is about 0.45mm, the substrate interconnection connection pad opening that can engage the tin ball is about between the 0.35mm to 0.4mm, and the interval height of finishing in surface adhering (SMT) (standoff height) is about about 0.3mm.Relatively, the height of the first lower floor's projection 223 of the present invention and the first upper strata projection 213 approximately can be between between the 0.08mm to 0.15mm, the projection top end surface is more than 0.06mm, the projection bottom size is about 0.18mm, and both pile up this first semiconductor package part 210 and this second semiconductor package part 220 and combine the back interval height and be about 0.275mm.Therefore, the present invention can supply the spacing of the substrate interconnection connection pad of engagement protrusion to dwindle more, and can meet the requirement of high density multiterminal subnumber.
Please consult shown in Figure 3ly again, those scolders 230 will have H shape welded section, make that the intensity of welding up and down be unanimity, and stronger for the resistance of cutting to stress.In other words, those first upper strata projections 213 can reach with those first lower floor projections 223 and have identical solder bonds shape and area.Therefore, the present invention can homogenizing solder bonds shape and area, and can reach the effect of avoiding semiconductor stack from micro-contact soldering point rupture, and then has promoted the upper plate reliability that pile up on the two sides (board level reliability).
Seeing also shown in Figure 4ly, is according to the present invention's first specific embodiment, can be engaged to the schematic cross-section an of the external circuit board by the semiconductor packaging stack device that a plurality of semiconductor package parts are formed.This semiconductor packaging stack device 200 can comprise second scolder 240 in addition, and it is to coat those second lower floor projections 214.This semiconductor packaging stack device 200 externally is engaged to a external circuit board 10 by those second scolders 240.And on this semiconductor packaging stack device 200, can pile up this second semiconductor package part 220 of right quantity more arbitrarily, reach the memory body capacity or the expansion of function.
Seeing also shown in Figure 5ly, is according to the present invention's second specific embodiment, the schematic cross-section of another kind of semiconductor packaging stack device.According to second specific embodiment of the present invention, disclosed another kind of semiconductor packaging stack device.This semiconductor packaging stack device 300 mainly comprises one first semiconductor package part 310, one second semiconductor package part 320 and a plurality of first scolder 330.
The first above-mentioned semiconductor package part 310 comprises one first substrate 311, one first wafer 312 and a plurality of upper stratas projection 313; Wherein, those upper strata projections 313 are upper surface 311A that are arranged at this first substrate 311 with this first wafer 312.In the present embodiment, this first wafer 312 mode of being arranged at this first substrate 311 is to be chip bonding.
The second above-mentioned semiconductor package part 320 comprises one second substrate 321, one second wafer 322 and a plurality of lower floors projection 323; Wherein, those lower floor's projections 323 are a lower surface 321B that are arranged at this second substrate 321, and this second wafer 322 is upper surface 321A that are arranged at this second substrate 321.
Above-mentioned those first scolder 330 is to engage those upper strata projections 313 and those lower floor's projections 323.Wherein, this second semiconductor package part 320 is folded being located on this first semiconductor package part 310, and makes those lower floor's projections 323 in alignment with those upper strata projections 313, in order to even welding.And preferably, those upper strata projections 313 are the U-shapeds that enlarge for opening with the solder bonds shape of those lower floor's projections 323.
This first semiconductor package part 310 can more comprise a plurality of lower floors projection 314, and those lower floor's projections 314 are a lower surface 311B that are arranged at this first substrate 311.This semiconductor packaging stack device 300 can comprise second scolder 340 in addition, and it is to coat those lower floor's projections 314.
Preferably, this second semiconductor package part 320 can have a plurality of void and put projection 324, and it is arranged at the lower surface 321B of this second substrate 321, and is positioned at the top of this first wafer 312 of this first semiconductor package part 310, for heat radiation.Those void are put the back side that projection 324 can contact this first wafer 312, so those void are put projection 324 except promoting the thermal diffusivity, also with the effect of little distance maintaining.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (23)
1, a kind of semiconductor packaging stack device is characterized in that it comprises:
One first semiconductor package part, it comprises one first substrate, one first wafer and a plurality of upper stratas projection, and wherein those upper strata projections and this first wafer are upper surfaces that is arranged at this first substrate;
One second semiconductor package part, it comprises one second substrate, one second wafer and a plurality of lower floors projection, and wherein those lower floor's projections are a lower surface that are arranged at this second substrate, and this second wafer is a upper surface that is arranged at this second substrate; And
A plurality of scolders, it engages those upper strata projections and those lower floor's projections;
Wherein, this second semiconductor package part is folded being located on this first semiconductor package part, and makes those lower floor's projections in alignment with those upper strata projections, in order to even welding.
2, semiconductor packaging stack device according to claim 1 is characterized in that wherein said first semiconductor package part more comprises a plurality of second lower floor's projections, and those second lower floor projections are a lower surface that are arranged at this first substrate.
3, semiconductor packaging stack device according to claim 2 is characterized in that it comprises second scolder in addition, and it is to coat those second lower floor projections.
4, semiconductor packaging stack device according to claim 1 is characterized in that wherein said second semiconductor package part more comprises a plurality of second upper strata projections, and those second upper strata projections are upper surfaces that are arranged at this second substrate.
5, semiconductor packaging stack device according to claim 1, it is characterized in that wherein said first semiconductor package part more comprises a plurality of first bonding wires, this first substrate is to have one first slotted eye, and those first bonding wires are to electrically connect this first wafer and this first substrate by this first slotted eye.
6, semiconductor packaging stack device according to claim 5 is characterized in that wherein said first semiconductor package part more comprises one first adhesive body, and it is to be formed at this first slotted eye, to seal those first bonding wires.
7, semiconductor packaging stack device according to claim 6 is characterized in that wherein said first adhesive body is not cover this first wafer.
8,, it is characterized in that wherein said second semiconductor package part is that essence is same as this first semiconductor packages, and include a plurality of second bonding wires and one second adhesive body according to claim 6 or 7 described semiconductor packaging stack devices.
9, semiconductor packaging stack device according to claim 1 is characterized in that wherein said those lower floor's projections and those upper strata projections are to have same size and profile.
10, semiconductor packaging stack device according to claim 1 is characterized in that wherein said those lower floor's projections and those upper strata projections are to have the half-cone cross section.
11, semiconductor packaging stack device according to claim 1 is characterized in that wherein said those lower floor's projections and those upper strata projections are to be the copper post.
12, semiconductor packaging stack device according to claim 1, it is characterized in that wherein said second semiconductor package part has a plurality of void and puts projection, it is the lower surface that is arranged at this second substrate, and is positioned at this first wafer top of this first semiconductor package part, for heat radiation.
13, semiconductor packaging stack device according to claim 12 is characterized in that it is the back side that contacts this first wafer that wherein said those void are put projection.
14, semiconductor packaging stack device according to claim 1 is characterized in that wherein said those scolders have H shape welded section.
15, semiconductor packaging stack device according to claim 1 is characterized in that wherein said those scolders are to be unleaded solder.
16, a kind of semiconductor packaging stack device, it is characterized in that it comprises a plurality of semiconductor package parts that pile up mutually, each semiconductor package part comprises a substrate, a wafer, a plurality of lower floors projection and a plurality of upper stratas projection, wherein those first lower floor projections are a lower surface that are arranged at this substrate, those upper strata projections and this wafer are upper surfaces that is arranged at this substrate, and those upper strata projections are to have identical solder bonds shape and area with those lower floor's projections.
17, semiconductor packaging stack device according to claim 16, the solder bonds shape that it is characterized in that wherein said those upper strata projections and those lower floor's projections are the U-shapeds that enlarges for opening.
18, semiconductor packaging stack device according to claim 16, it is characterized in that wherein said each semiconductor package part more comprises a plurality of bonding wires, this substrate is to have a slotted eye, and those bonding wires are to electrically connect this wafer and this substrate by this slotted eye.
19, semiconductor packaging stack device according to claim 18 is characterized in that wherein said each semiconductor package part more comprises an adhesive body, and it is to be formed at this slotted eye, to seal those bonding wires.
20, semiconductor packaging stack device according to claim 19 is characterized in that wherein said each adhesive body is not cover this wafer.
21, semiconductor packaging stack device according to claim 16 is characterized in that wherein said those lower floor's projections and those upper strata projections are to have the half-cone cross section.
22, semiconductor packaging stack device according to claim 16 is characterized in that wherein said those lower floor's projections and those upper strata projections are to be the copper post.
23, semiconductor packaging stack device according to claim 16 is characterized in that wherein said each semiconductor package part has a plurality of void and puts projection, and it is a lower surface of being located at this substrate, for heat radiation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710106720 CN100539128C (en) | 2007-05-30 | 2007-05-30 | Avoid the packaging stack device of semiconductor stack from micro-contact soldering point rupture |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710106720 CN100539128C (en) | 2007-05-30 | 2007-05-30 | Avoid the packaging stack device of semiconductor stack from micro-contact soldering point rupture |
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| Publication Number | Publication Date |
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| CN101315922A true CN101315922A (en) | 2008-12-03 |
| CN100539128C CN100539128C (en) | 2009-09-09 |
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| CN 200710106720 Expired - Fee Related CN100539128C (en) | 2007-05-30 | 2007-05-30 | Avoid the packaging stack device of semiconductor stack from micro-contact soldering point rupture |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347319A (en) * | 2010-07-26 | 2012-02-08 | 台湾积体电路制造股份有限公司 | Package-on-package structures with reduced bump bridging |
| CN102361028A (en) * | 2011-10-11 | 2012-02-22 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure with multiple convex block structures |
| CN103262237A (en) * | 2010-10-19 | 2013-08-21 | 德塞拉股份有限公司 | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristic |
| CN104681530A (en) * | 2013-11-26 | 2015-06-03 | 日月光半导体制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN106449612A (en) * | 2016-08-23 | 2017-02-22 | 武汉寻泉科技有限公司 | Stacking and packaging structure for memory chips |
| CN108780789A (en) * | 2016-03-31 | 2018-11-09 | 英特尔公司 | Optoelectronic transceiver device assembly |
-
2007
- 2007-05-30 CN CN 200710106720 patent/CN100539128C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347319A (en) * | 2010-07-26 | 2012-02-08 | 台湾积体电路制造股份有限公司 | Package-on-package structures with reduced bump bridging |
| CN102347319B (en) * | 2010-07-26 | 2014-03-05 | 台湾积体电路制造股份有限公司 | Package-on-package structures with reduced bump bridging |
| CN103262237A (en) * | 2010-10-19 | 2013-08-21 | 德塞拉股份有限公司 | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristic |
| CN102361028A (en) * | 2011-10-11 | 2012-02-22 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure with multiple convex block structures |
| CN104681530A (en) * | 2013-11-26 | 2015-06-03 | 日月光半导体制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN104681530B (en) * | 2013-11-26 | 2017-09-26 | 日月光半导体制造股份有限公司 | Semiconductor structure and its manufacture method |
| CN108780789A (en) * | 2016-03-31 | 2018-11-09 | 英特尔公司 | Optoelectronic transceiver device assembly |
| CN106449612A (en) * | 2016-08-23 | 2017-02-22 | 武汉寻泉科技有限公司 | Stacking and packaging structure for memory chips |
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| Publication number | Publication date |
|---|---|
| CN100539128C (en) | 2009-09-09 |
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