CN102254890A - Stacked semiconductor package and method for manufacturing the same - Google Patents

Stacked semiconductor package and method for manufacturing the same Download PDF

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Publication number
CN102254890A
CN102254890A CN2011101879065A CN201110187906A CN102254890A CN 102254890 A CN102254890 A CN 102254890A CN 2011101879065 A CN2011101879065 A CN 2011101879065A CN 201110187906 A CN201110187906 A CN 201110187906A CN 102254890 A CN102254890 A CN 102254890A
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CN
China
Prior art keywords
hole
semiconductor
semiconductor packages
stacked
substrate
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Pending
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CN2011101879065A
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Chinese (zh)
Inventor
李圭远
赵哲浩
都恩惠
金祉夽
申熙珉
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SK Hynix Inc
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Hynix Semiconductor Inc
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Publication of CN102254890A publication Critical patent/CN102254890A/en
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Abstract

The invention provides a stacked semiconductor package and the method for manufacturing the same. The stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads.

Description

Stacked semiconductor encapsulation and manufacture method thereof
Technical field
The present invention relates to stacked semiconductor encapsulation and manufacture method thereof.
Background technology
In semicon industry, the encapsulation technology that is used for semiconductor integrated circuit just in sustainable development to satisfy demand for miniaturization and efficiency of assembling.For example, the demand of miniaturization has been quickened the development of technology that size is similar to the encapsulation of chip, and the demand of assembly reliability has been highlighted the importance that is used to improve the encapsulation technology of machinery and electric reliability after assembly work efficient and the assembling.In addition since in the Electrical and Electronic product to miniaturization and high performance needs, lamination techniques has been suggested and has just developed at present and all kinds in the art.
Related term " stacked " refers to the technology of at least two semiconductor chips of vertical accumulation or semiconductor packages in semicon industry.By using lamination techniques, for example,, can configure the DRAM of a 512M by the DRAM of stacked two 256M.In addition,, stacked semiconductor provides advantage, so the research and development of stacked semiconductor encapsulation is quickened owing to being encapsulated in memory capacity, packaging density and assembling area utilization ratio aspect.
Fig. 1 is a viewgraph of cross-section, and the encapsulation of a known POP (packaging body lamination) type stacked semiconductor is shown.Under encapsulate 20 and go up encapsulation 30 and be layered on the main substrate 10, be electrically connected by soldered ball 41 and 42 simultaneously.
Particularly, main substrate 10 and down encapsulation 20 be electrically connected to each other by soldered ball 41, this solder sphere 41 forms being formed at the ball island-shaped pattern 11 on main substrate 10 upper surfaces and being formed between the ball island-shaped pattern 23A on substrate 21 lower surfaces of down encapsulation 20, and following encapsulation 20 is electrically connected to each other by soldered ball 42 with last encapsulation 30, the formation between the ball island-shaped pattern 33 on the lower surface that is formed at ball island-shaped pattern 23B and the substrate 31 that is formed at encapsulation 30 on the upper surface of the substrate 21 of encapsulation 20 down of this soldered ball 42.
Undefined Reference numeral 22,24,25 and 26 refers to first semiconductor chip, first bond, first closing line and the lower mould parts that constitute encapsulation 20 down respectively, and undefined Reference numeral 32,34,35 and 36 refers to second semiconductor chip, second bond, second closing line that constitutes upward encapsulation 30 respectively and goes up moulding part.
Yet, in the encapsulation of known stacked semiconductor, when soldered ball 41 and 42 is implemented reflux techniques, at main substrate 10, down encapsulate 20 and on warpage may appear in the encapsulation 30, and because the appearance of warpage the crack may occur in soldered ball 41 and 42.The appearance in crack may cause the generation of substandard product, and making output and productivity ratio thus may worsen.
Summary of the invention
Embodiments of the present invention are at the stacked semiconductor encapsulation and can suppress this structure making process that inefficacy takes place.
In an illustrative embodiments of the present invention, the stacked semiconductor encapsulation comprises: the semiconductor package module that contains a plurality of semiconductor packages and bond, wherein each semiconductor packages has first surface, second surface back to this first surface, connect the side surface of first surface and second surface and be formed on this side surface to pass the through hole of this first surface and second surface, and these a plurality of semiconductor packages are stacked to make their through hole vertically connect each other, and described bond is formed between the semiconductor packages and with semiconductor packages and is attached to one another; Main substrate, support semiconductor package module and on the 3rd surface of semiconductor package module, be formed with the main connection gasket of aiming at through hole at it; And conducting connecting part, be formed in the through hole, and be electrically connected semiconductor packages and main connection gasket.
In another illustrative embodiments of the present invention, a kind of method that is used to make the stacked semiconductor encapsulation comprises step: form a plurality of semiconductor packages, each semiconductor packages all has first surface, back to the second surface of this first surface and the side surface that connects first surface and second surface, and on side surface, be formed with the through hole that passes first surface and second surface; Cover the mode of the cross section of the through hole that the second surface of semiconductor packages opens wide with part, first bond is attached to the second surface of semiconductor packages; Soldered ball is inserted in the through hole; Be formed with stacked this semiconductor packages on the main substrate of main connection gasket, making the through hole of semiconductor packages vertically connect each other; And this soldered ball that refluxes, form the conducting connecting part that is electrically connected semiconductor packages and main connection gasket thus.
In another illustrative embodiments of the present invention, the stacked semiconductor encapsulation comprises: a plurality of semiconductor package modules, each semiconductor package module comprises a plurality of semiconductor packages and bond, wherein each semiconductor packages has first surface, second surface back to this first surface, the side surface that connects first surface and second surface, and be formed on this side surface to pass the through hole of this first surface and second surface, and stacked their through hole that makes of these a plurality of semiconductor packages connects each other vertically, and described bond is formed between the semiconductor packages and with semiconductor packages and is attached to one another, and these a plurality of semiconductor package modules form with matrix form and are adjacent to each other, and make the through hole of the semiconductor packages that in the vertical direction connects connect in the horizontal direction; And main substrate, supporting this semiconductor package module and on the 3rd surface of semiconductor package module, be formed with main connection gasket at it, the through hole that this main connection gasket links to each other with in the vertical direction is aimed at; And conducting connecting part, be formed in the through hole, and be electrically connected semiconductor packages and main connection gasket.
Description of drawings
Fig. 1 is a viewgraph of cross-section, and a known POP type stacked semiconductor encapsulation is shown;
Fig. 2 is a perspective view, and the stacked semiconductor encapsulation of one illustrative embodiments according to the present invention is shown;
Fig. 3 is the viewgraph of cross-section along the line I-I ' intercepting of Fig. 2;
Fig. 4 is the cut-away section perspective view of semiconductor packages shown in Figure 2;
Fig. 5 to 12 is views that explanation is used to make the method for stacked semiconductor encapsulation shown in Figure 2;
Figure 13 is a perspective view, and the stacked semiconductor encapsulation of another illustrative embodiments according to the present invention is shown;
Figure 14 is the viewgraph of cross-section along the line II-II ' intercepting of Figure 13;
Figure 15 A and Figure 15 B are the views of explaining the effect that is reached in the stacked semiconductor encapsulation of another illustrative embodiments according to the present invention.
Embodiment
Below, describe specific implementations of the present invention with reference to the accompanying drawings in detail.
Should be appreciated that at this that accompanying drawing needs not to be in proportion and draw, and in order more clearly to describe the special characteristic of invention, ratio may be exaggerated in some instances.
Fig. 2 is a perspective view, and the stacked semiconductor encapsulation according to an illustrative embodiments of the present invention is shown; Fig. 3 is the viewgraph of cross-section along the line I-I ' intercepting of Fig. 2; And Fig. 4 is the part section view of semiconductor packages shown in Figure 2.
With reference to Fig. 2 and Fig. 3, comprise semiconductor package module 40, main substrate 50 and conducting connecting part 60 according to the encapsulation of the stacked semiconductor of the present invention's one illustrative embodiments.
Semiconductor package module 40 comprises a plurality of semiconductor packages 100 and first bond 200.In current illustrative embodiments, semiconductor package module 40 comprises three semiconductor packages 100.
With reference to Fig. 4, each semiconductor packages 100 has first surface 100A, back to the second surface 100B of this first surface 100A and the side surface 100C that connects first surface 100A and second surface 100B.In current illustrative embodiments, each semiconductor packages 100 has the right angle hexahedral shape.Semiconductor packages 100 with right angle hexahedral shape has four side surface 100C.Through hole 140 is formed on the side surface 100C of semiconductor packages 100 in the mode of passing first surface 100A and second surface 100B.In current illustrative embodiments, form a plurality of through holes 140 at the side surface 100C of semiconductor packages 100.Each through hole 140 can have cylinder form.
According to an example, the inside diameter D of through hole 140 has the size greater than soldered ball (solder ball) diameter, so soldered ball can insert this through hole 140.And, for the soldered ball that prevents to insert moves on to outside the through hole 140, the open width W of this through hole 140 has the little size of inside diameter D than the diameter of soldered ball and through hole 140, and wherein this through hole 140 opens wide described open width W at the side surface 100C of semiconductor packages 100.For example, the open width W of through hole 140 can be about 10% to 50% of through hole 140 inside diameter D.Although in current illustrative embodiments, through hole 140 has cylinder form, and this through hole 140 can be the prism shape with at least three sides.
In current illustrative embodiments, semiconductor packages 100 comprises that through hole 140 passes the substrate 110 and the moulding part 130 of its formation, and semiconductor chip 120.
According to an example, substrate 110 is the quadrangular plate shape.This substrate 110 has the 5th surperficial 110A, back to the 6th surperficial 110B of the 5th surperficial 110A and four side surface 110C that connect the 5th surperficial 110A and the 6th surperficial 110B.
Connection gasket 112 is formed on the 5th surperficial 110A of substrate 110, and sidepiece pad (side pad) 113 is formed on the inwall of the through hole 140 that forms on the side surface 110C of substrate 110.Although not shown in figures, substrate 110 can comprise circuit pattern (not shown) that forms the formation multilayer and the through hole (not shown) that electrical connection is formed on the circuit pattern in the different layers therein.Connection gasket 112 and sidepiece pad 113 can be electrically connected to each other by circuit pattern and the through hole that forms in substrate 110.
Semiconductor chip 120 has in the face of the 7th surface 121 of substrate 110 and back to the 8th surface 122 on the 7th surface 121.
The 7th surface 121 of semiconductor chip 120 utilizes second bond 150 to be attached to the 5th surperficial 110A of substrate 110, and the joint sheet (bonding pad) 123 that is connected with the connection gasket 112 of substrate 110 is formed on the 8th surface 122 of semiconductor chip 120.Although it is not shown in figures, but the circuit unit (not shown) that is made of with storage and deal with data transistor, capacitor, resistor or the like is formed in the semiconductor chip 120, and joint sheet 123 is as the electric contact of this circuit unit, in order to be connected to the outside.
In current illustrative embodiments, the connection gasket 112 of substrate 110 and the joint sheet 123 of semiconductor chip 120 are connected to each other by closing line 124.Although in current illustrative embodiments, substrate 110 and semiconductor chip 120 utilize closing line 124 to be connected to each other by the wire-bonded mode, and substrate 110 and semiconductor chip 120 can be connected to each other in the flip-chip bonded mode.
The 5th surperficial 110A that comprises semiconductor chip 120 and closing line 124 of moulding part 130 hermetic sealing substrates 110.
Return referring to figs. 2 and 3, a plurality of semiconductor packages 100 is stacked, makes through hole 140 aim at vertically each other, and constitutes semiconductor package module 40 thus.
First bond 200 is formed between the stacked semiconductor encapsulation 100.The second surface 100B of the semiconductor packages 100 above each first bond 200 will be positioned at and the first surface 100A of the semiconductor packages 100 that is positioned at the below are attached to each other.
First bond 200 forms in the mode that part covers the cross section of the first surface 100A of semiconductor packages 100 and the through hole 140 that second surface 100B upward opens wide.For example, first bond 200 forms and covers about 20% to 50% of through hole 140 cross sections.First bond 200 is used for supporting the soldered ball that inserts through hole 140, thereby avoids soldered ball to shift out through hole 140.
First bond 200 can form flexible adhesive sheet.For example can use WBL (chip back surface stacked (wafer backside lamination)) film, intervallum and prepreg (prepreg) as adhesive sheet.
Main substrate 50 supports this semiconductor package module 40.
Semiconductor package module 40 utilizes first bond 200 to be attached to main substrate 50, and this first bond 200 is attached to the second surface 100B of the semiconductor packages 100 that is positioned at the bottom.
Main substrate 50 has in the face of the 3rd surface 51 of semiconductor package module 40 and back to the 4th surface 52 on the 3rd surface 51.Main connection gasket 53 is formed on the 3rd surface 51 of main substrate 50 in the mode of aiming at through hole 140.
Conducting connecting part 60 is formed in the through hole 140, and this through hole 140 is electrically connected the main connection gasket 53 of stacked formula semiconductor packages 100 and main substrate 50.In current illustrative embodiments, conducting connecting part 60 is electrically connected the main connection gasket 53 of sidepiece pad 113 and main substrate 50, and wherein this sidepiece pad 113 is formed on the side surface 110C of the substrate 110 of stacked semiconductor encapsulation 100.
On the 3rd surface 51 that semiconductor packages 100 is layered in vertically main substrate 50, wherein soldered ball inserts in the through hole 140, and by via reflux technique fusing soldered ball, can form conducting connecting part 60.
Although it is not shown in figures, but under the situations that semiconductor packages 100 should be isolated with conducting connecting part 60 electricity, the insulation ball, rather than soldered ball, can be inserted in the through hole 140, this through hole 140 is formed in the corresponding semiconductor packages 100, makes that the sidepiece pad 113 on the side surface 110C of the substrate 110 be formed on corresponding semiconductor encapsulation 100 is isolated with conducting connecting part 60 electricity.At this, the silicon ball can be as the insulation ball.
Use description to make the method for stacked semiconductor encapsulation below with said structure.
Fig. 5 to Figure 12 is a view of explaining a method of the stacked semiconductor encapsulation of making the above-mentioned illustrative embodiments according to the present invention.
Fig. 5, Fig. 7, Fig. 9, Figure 11 and Figure 12 are the viewgraph of cross-section according to processing sequence, and Fig. 6, Fig. 8 and Figure 10 are the plane graphs of Fig. 5, Fig. 7 and Fig. 9.For the ease of understanding, moulding part 130 is not shown in Fig. 6, Fig. 8 and Figure 10.
With reference to Fig. 5 and Fig. 6, prepared strip level (level) substrate 70, this substrate 70 has a plurality of unit horizontal substrates 110, its each unit horizontal substrate 110 all has the 5th surperficial 110A and back to the 6th surperficial 110B of the 5th surperficial 110A, and on its 5th surperficial 110A, be formed with connection gasket 112, and on its side surface, be formed with conductive layer 113A as the sidepiece pad.
The unit horizontal substrate 110 of adjacency is connected to each other along line of cut S, and the conductive layer 113A of the sidepiece pad of the unit horizontal substrate 110 of adjacency is coupled to each other.
Although not shown in figures, each unit horizontal substrate 110 can comprise circuit pattern (not shown) that forms the formation multilayer and the through hole (not shown) that is connected electrically in the circuit pattern that forms on the different layers therein.Connection gasket 112 and can be electrically connected to each other by circuit pattern and the through hole that in unit horizontal substrate 110, forms as the conductive layer 113A of sidepiece pad.
Semiconductor chip 120 utilizes second bond 150 to be attached to each unit horizontal substrate 110, and the connection gasket 112 of the joint sheet 123 of semiconductor chip 120 and unit horizontal substrate 110 is connected to each other by closing line 124.
By forming moulding part 130, wherein the 5th surperficial 110A that comprises closing line 124 and semiconductor chip 120 of these moulding part 130 sealing unit horizontal base plates 110 forms the horizontal semiconductor packages 100 of a plurality of strips.
With reference to Fig. 7 and Fig. 8, pass strip horizontal base plate 70 and moulding part 130 formation through holes 140, to pass the conductive layer 113A in the unit horizontal substrate 110 as the sidepiece pad.This through hole 140 can form by bore process or laser drilling process.
The open width W of this through hole 140 is confirmed as having less than the inside diameter D of through hole 140 and will be inserted into the size of the diameter of the soldered ball in the through hole 140, and wherein this through hole 140 opens wide described open width W at the side surface of unit horizontal substrate 110.Conductive layer 113A as the sidepiece pad does not Remove All and is retained in the through hole 140.By the conductive layer 113A that keeps in such a manner, on the inwall of the through hole 140 of unit horizontal substrate 110, form sidepiece pad 113 as the sidepiece pad.
Although in current illustrative embodiments, the through hole 140 that forms in unit horizontal substrate 110 has columniform in fact shape, and this through hole 140 can be for having the prism shape of at least three sides.
With reference to Fig. 9 and Figure 10, by cut this strip horizontal base plate 70 and moulding part 130 along line of cut S, semiconductor packages 100 is by individuation.
With reference to Figure 11, first bond 200 is attached to the surface of other semiconductor packages 100.After this, first bond, the 200 attached surfaces thereon of semiconductor packages 100 form second surface 100B, and another surface back to this second surface 100B of semiconductor packages 100 forms first surface 100A.
Partly to cover the mode of the cross section of through hole 140, wherein this through hole 140 opens wide on the second surface 100B of semiconductor packages 100, forms first bond 200.For example, first bond 200 forms the about 20% to 50% of the cross section that covers through hole 140, and this through hole 140 opens wide at the second surface 100B of semiconductor packages 100.
First bond 200 can form flexible adhesive sheet.For example can use WBL (chip back surface is stacked) film, intervallum and prepreg as adhesive sheet.
Soldered ball 300 is inserted in the through hole 140.The soldered ball 300 that inserts through hole 140 is supported by first bond 200, can not shift out through hole 140 downwards.Because the open width W of through hole 140 is confirmed as having the size less than the diameter of soldered ball 300, wherein this through hole 140 opens wide described open width W on the side surface of semiconductor packages 100, can not move and shift out through hole 140 so insert the soldered ball 300 of through hole 140 yet, and keep in the insertion through hole 140 to the side.
Though not shown in figures, in the through hole 140 that the ball that insulate replaces soldered ball 300 to be inserted in not needing forming on the side surface of the semiconductor packages 100 that is electrically connected.At this, the silicon ball can be as the insulation ball.
With reference to Figure 12, semiconductor packages 100 is layered on the 3rd surface 51 of main substrate 50, and the mode that main connection gasket 53 is vertically aimed at through hole 140 and main connection gasket 53 on the 3rd surface 51 forms.By first bond 200 that on the second surface 100B of semiconductor packages 100, forms that semiconductor packages 100 is stacked vertically and attached mutually, and utilize and to be attached to first bond 200 that is positioned at undermost semiconductor packages 100 and to be attached to main substrate 50.
Return with reference to Fig. 2 and Fig. 3,,, form conducting connecting part 60 with the sidepiece pad 113 of formation in the substrate 110 that is connected electrically in semiconductor packages 100 and the mode of main connection gasket 53 by via reflux technique fusing soldered ball.
Because soldered ball 300 melts and flows downward during reflux technique, so conducting connecting part 60 may not form in the through hole 140 of the stacked semiconductor packages 100 in top.In this case, after carrying out reflux technique, soldered ball 300 is additionally inserted in the through hole 140, and carries out reflux technique once more.
Although in above illustrative embodiments, described by on main substrate 50, carrying out reflux technique after stacked a plurality of semiconductor packages 100, the soldered ball 300 that inserts in the through hole 140 of a plurality of semiconductor packages 100 is once melted, but reflux technique can be carried out in each time of stacked each semiconductor packages 100, made soldered ball 300 to be melted by semiconductor packages 100.
Figure 13 is a perspective view, the stacked semiconductor encapsulation of another illustrative embodiments according to the present invention is shown, and Figure 14 is the viewgraph of cross-section along the line II-II ' intercepting of Figure 13.
With reference to Figure 13 and Figure 14, encapsulation comprises a plurality of semiconductor package module 40A, 40B, 40C and 40D, main substrate 50 and conducting connecting part 60 according to the stacked semiconductor of another illustrative embodiments of the present invention.
In current illustrative embodiments, the stacked semiconductor encapsulation comprises four semiconductor package module 40A, 40B, 40C and 40D.These four semiconductor package module 40A, 40B, 40C and 40D form first to fourth semiconductor package module respectively, and after this, will use these terms to describe.
First to fourth semiconductor package module 40A, 40B, 40C and 40D are formed on the main substrate 50 with 2 * 2 matrix forms, make the side of first to fourth semiconductor package module 40A, 40B, 40C and 40D be connected to each other.That is to say that the second semiconductor package module 40B forms and be close to this first semiconductor package module 40A on first direction, the 3rd semiconductor package module 40C forms on perpendicular to the second direction of first direction and is close to the first semiconductor package module 40A.The 4th semiconductor package module 40D forms on to the angular direction and is close to the first semiconductor package module 40A.
First to fourth semiconductor package module 40A, 40B, 40C and 40D can have with above in the semiconductor packages identical construction described in first illustrative embodiments.Therefore, will omit being repeated in this description of same structure, and identical technical term and identical Reference numeral will be used to indicate identical element at this.
Among first to fourth semiconductor package module 40A, 40B, 40C and the 40D each has a structure, and the semiconductor packages 100 that is formed with through hole 140 in this structure on its each side surface is stacked vertically, makes their through hole 140 be connected to each other.
First to fourth semiconductor package module 40A, 40B, 40C and 40D formed be adjacent to each other, make the through hole 140 that vertically connects each other also be connected to each other in the horizontal direction.
Main substrate 50 supports first to fourth semiconductor package module 40A, 40B, 40C and 40D.
First bond, 200, first to fourth semiconductor package module 40A, 40B, 40C and 40D that utilization is attached to the second surface 100B of the semiconductor packages 100 that is positioned at the bottom are attached to main substrate 50.
Main substrate 50 has in the face of the 3rd surface 51 of first to fourth semiconductor package module 40A, 40B, 40C and 40D and back to the 4th surface 52 on the 3rd surface 51.The main connection gasket of aiming at the through hole 140 of first to fourth semiconductor package module 40A, 40B, 40C and 40D 53 is formed on the 3rd surface 51 of main substrate 50.
Conducting connecting part 60 is formed in the through hole 140 of first to fourth semiconductor package module 40A, 40B, 40C and 40D, and be electrically connected the main connection gasket 53 of sidepiece pad 113 and main substrate 50 in the substrate 110 be formed on semiconductor packages 100, wherein this semiconductor packages 100 is included among first to fourth semiconductor package module 40A, 40B, 40C and the 40D.
By assembling on vertical and horizontal direction and layout semiconductor packages 100, wherein soldered ball inserts in the through hole 140, and passes through the enforcement reflux technique with the fusing soldered ball, formation conducting connecting part 60.
Though it is not shown in figures, but under the situations that semiconductor packages 100 should be isolated with conducting connecting part 60 electricity, can in the through hole 140 that in the substrate 110 of corresponding semiconductor packages 100, forms, insert the insulation ball, rather than soldered ball, make that the sidepiece pad 113 in the substrate 110 that is formed on corresponding semiconductor packages 100 can be isolated with conducting connecting part 60 electricity.The silicon ball can be as the insulation ball.
The through hole 140 that forms on the side surface of first to fourth semiconductor package module 40A, 40B, 40C and 40D is connected to each other in the horizontal direction.Because by the conducting connecting part 60 that in through hole 140, forms, first to fourth semiconductor package module 40A, 40B, 40C and 40D are connected with main substrate 50, so can reduce compared to the prior art, the quantity of the required main connection gasket 53 of main substrate 50 and the quantity of wiring.
That is to say, shown in Figure 15 A, independently be assembled under the situation of main substrate 50 that circuitry needed wiring number is 16 (=4 * 4) in main substrate 50 at four semiconductor package module 40A, 40B, 40C and 40D.Yet, shown in Figure 15 B, be adjacently formed with 2 * 2 matrix form at four semiconductor package module 40A, 40B, 40C and 40D, make that the number of required wiring only is 6 in main substrate 50 under through hole 140 situation connected to one another in the horizontal direction.
By above description apparently, in the present invention, owing to utilize bond that the stacked semiconductor encapsulation is attached fully each other, so can be suppressed at the warpage that occurs in the semiconductor packages.And, because by having that flexible bond can alleviate because the stress that the warpage of semiconductor packages causes, the crack appears so can be suppressed in the soldered ball as connector.Further, owing to be formed on the side surface of semiconductor packages, can reduce the height of stacked semiconductor encapsulation as the soldered ball of connector.In addition, because the fact that semiconductor package module is connected with adjacent semiconductor package module by connector, so can reduce wiring number required in main substrate.
Although for purposes of illustration, specific exemplary embodiments of the present invention has been described, those skilled in the art are possible with understanding various improvement, interpolation and replacement, and do not break away from by the disclosed scope and spirit of the present invention of claims.
The Korean Patent Application No. that the application requires to submit on May 6th, 2010 is the priority of 10-2010-42457, at this by referring in conjunction with its full content.

Claims (25)

1. stacked semiconductor encapsulation comprises:
Semiconductor package module, comprise a plurality of semiconductor packages and bond, wherein each semiconductor packages has the side surface of first surface, the second surface back to described first surface, the described first surface of connection and described second surface and is formed on the described side surface to penetrate the through hole of described first surface and described second surface, and described a plurality of semiconductor packages is stacked to make their through hole connect vertically each other, and described bond is formed between the described semiconductor packages and with described semiconductor packages and is attached to each other;
Main substrate supports described semiconductor package module, and is formed with the main connection gasket of aiming at described through hole at it in the face of on the 3rd surface of described semiconductor package module; And
Conducting connecting part forms in described through hole, and is electrically connected described semiconductor packages and described main connection gasket.
2. stacked semiconductor encapsulation according to claim 1, wherein each semiconductor packages comprises:
Substrate has the 5th surface, back to the 6th surface on the 5th surface and connect described the 5th surface and the side surface on described the 6th surface, is formed with connection gasket on described the 5th surface, and is formed with described through hole on described side surface;
Semiconductor chip is positioned on the described substrate, and has the joint sheet that is connected with described connection gasket; And
Moulding part seals described the 5th surface that comprises described semiconductor chip of described substrate, and be formed with described through hole on its side surface.
3. stacked semiconductor encapsulation according to claim 2, wherein said substrate comprises the sidepiece pad on the inwall that is formed on described through hole, wherein this through hole is formed on the described side surface of described substrate.
4. stacked semiconductor encapsulation according to claim 1, wherein said through hole is cylindric or has the prism shape of at least three sides.
5. stacked semiconductor encapsulation according to claim 1, the open width of wherein said through hole has the size less than the internal diameter of described through hole, and wherein said through hole opens wide described open width on the described side surface of described semiconductor packages.
6. stacked semiconductor according to claim 5 encapsulation, the size of the described open width of wherein said through hole and the internal diameter of described through hole about 10% to 50% corresponding.
7. stacked semiconductor encapsulation according to claim 1, wherein said bond forms flexible adhesive sheet.
8. stacked semiconductor encapsulation according to claim 7, wherein said bond uses any one formation in chip back surface stacked film, intervallum and the prepreg.
9. stacked semiconductor according to claim 1 encapsulation, wherein said bond form the cross section of the described through hole that the described first surface that partly covers described semiconductor packages and described second surface open wide.
10. stacked semiconductor according to claim 9 encapsulation, wherein bond forms about 20% to 50% of the cross section that covers described through hole.
11. stacked semiconductor encapsulation according to claim 1, wherein said conducting connecting part uses soldered ball to form.
12. a method for preparing stacked semiconductor packages comprises step:
Form a plurality of semiconductor packages, each semiconductor packages has first surface, back to the second surface of described first surface and the side surface that connects described first surface and described second surface, and on described side surface, be formed with the through hole that passes described first surface and described second surface;
Cover the mode of the cross section of the through hole that the second surface of described semiconductor packages opens wide with part, first bond is attached to the second surface of described semiconductor packages;
Soldered ball is inserted in the described through hole;
Be formed with stacked described semiconductor packages on the main substrate of main connection gasket, making the described through hole of described semiconductor packages connect vertically each other; And
The described soldered ball that refluxes, and form the conducting connecting part that is electrically connected described semiconductor packages and described main connection gasket thus.
13. method according to claim 12, wherein said through hole forms by bore process or laser drilling process.
14. method according to claim 12, wherein said bond form the described through hole that the second surface that covers described semiconductor packages opens wide cross section about 20% to 50%.
15. a stacked semiconductor encapsulation comprises:
A plurality of semiconductor package modules, each semiconductor package module comprises a plurality of semiconductor packages and bond, wherein each semiconductor packages has first surface, second surface back to described first surface, the side surface that connects described first surface and described second surface, and be formed on the described side surface to penetrate the through hole of described first surface and described second surface, and these a plurality of semiconductor packages are stacked, make their through hole connect vertically each other, and described bond is formed between the described semiconductor packages and with described semiconductor packages and is attached to one another, and these a plurality of semiconductor package modules form with matrix form and are adjacent to each other, and make the described through hole of the described semiconductor packages that in the vertical direction connects connect in the horizontal direction;
Main substrate supports described semiconductor package module, and is formed with main connection gasket at it in the face of on the 3rd surface of described semiconductor package module, and this main connection gasket is connected with the described through hole that in the vertical direction links to each other; And
Conducting connecting part is formed in the described through hole, and is electrically connected described semiconductor packages and main connection gasket.
16. stacked semiconductor encapsulation according to claim 15, wherein each semiconductor packages comprises:
Substrate has the 5th surface, back to the 6th surface on the 5th surface and connect described the 5th surface and the side surface on described the 6th surface, is formed with connection gasket on described the 5th surface, and is formed with described through hole on described side surface;
Semiconductor chip is positioned on the described substrate, and has the joint sheet that is connected with described connection gasket; And
Moulding part seals described the 5th surface that comprises described semiconductor chip of described substrate, and be formed with described through hole on its side surface.
17. stacked semiconductor encapsulation according to claim 15, wherein said substrate comprises the sidepiece pad on the inwall that is formed on described through hole, and wherein this through hole is formed on the described side surface of described substrate.
18. stacked semiconductor encapsulation according to claim 15, wherein said through hole is cylindric or has the prism shape of at least three sides.
19. stacked semiconductor encapsulation according to claim 15, the open width of wherein said through hole has the size less than the internal diameter of described through hole, and this through hole opens wide described open width at the side surface of described semiconductor packages.
20. stacked semiconductor according to claim 19 encapsulation, the size of the described open width of wherein said through hole and the internal diameter of described through hole about 10% to 50% corresponding.
21. stacked semiconductor encapsulation according to claim 15, wherein bond forms flexible adhesive sheet.
22. stacked semiconductor encapsulation according to claim 21, wherein bond uses any one formation in chip back surface stacked film, intervallum and the prepreg.
23. stacked semiconductor according to claim 15 encapsulation, wherein bond forms the cross section of the described through hole that the described first surface that partly covers described semiconductor packages and described second surface open wide.
24. stacked semiconductor according to claim 23 encapsulation, wherein bond forms about 20% to 50% of the described cross section that covers described through hole.
25. stacked semiconductor encapsulation according to claim 15, wherein said conducting connecting part uses soldered ball to form.
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