KR101663640B1 - A substrate for die bonding and a die bonding method of semiconductor chip using the same - Google Patents

A substrate for die bonding and a die bonding method of semiconductor chip using the same Download PDF

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Publication number
KR101663640B1
KR101663640B1 KR1020150121952A KR20150121952A KR101663640B1 KR 101663640 B1 KR101663640 B1 KR 101663640B1 KR 1020150121952 A KR1020150121952 A KR 1020150121952A KR 20150121952 A KR20150121952 A KR 20150121952A KR 101663640 B1 KR101663640 B1 KR 101663640B1
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KR
South Korea
Prior art keywords
semiconductor chip
die bonding
substrate
package
adhesive
Prior art date
Application number
KR1020150121952A
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Korean (ko)
Inventor
안준은
이정신
Original Assignee
국방과학연구소
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Priority to KR1020150121952A priority Critical patent/KR101663640B1/en
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Publication of KR101663640B1 publication Critical patent/KR101663640B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/447—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428 involving the application of pressure, e.g. thermo-compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a die bonding substrate and a die bonding method of a semiconductor chip using the same. A substrate for die bonding according to an embodiment of the present invention is interposed between a semiconductor chip 100 and a package 200 for fixing the semiconductor chip 100 to adjust a bonding area of the semiconductor chip 100 A plurality of holes 310 arranged on a plurality of circumferences formed on the basis of a center point of the bonding area of the semiconductor chip 100. The plurality According to the present invention, by controlling the diffusion area of the adhesive applied to the semiconductor chip by using the substrate for die bonding having a plurality of holes inserted between the semiconductor chip and the package, the difference in thermal expansion coefficient between the semiconductor chip and the package- It is possible to reduce the thermal stress.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a substrate for die bonding and a die bonding method for a semiconductor chip using the same. 2. Description of the Related Art [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a substrate for die bonding and a die bonding method of a semiconductor chip using the same, and more particularly to a die bonding substrate for controlling the area (i.e., bonding area) To a die bonding method of a chip.

In the semiconductor industry, a semiconductor chip is protected from the external environment, and a semiconductor chip is mounted on a package made of ceramic or metal for electrical connection between the semiconductor chip and the chip. The step of fixing the semiconductor chip to the package in this mounting step is called " die bonding ". Die bonding enables mechanical maintenance of the semiconductor chip and electrical and thermal connection between the semiconductor chip and the package. Die bonding can be divided into an adhesive method using a polymer or an epoxy as a bonding material and a fusion bonding method in which a metal is melted and bonded.

When the semiconductor chip and the package coupled by die bonding are placed in a temperature environment different from the initial manufacturing process due to power supplied to the semiconductor chip or ambient temperature change, the semiconductor chip and the package may have different ratios . As a result, a thermal stress is generated in the semiconductor chip, and the mechanical and electrical characteristics of the device fabricated in the semiconductor chip are changed by the thermal stress, thereby deteriorating the performance and lifetime of the device.

In order to solve this problem, conventionally, a material having a low elastic modulus is used as an adhesive so that the adhesive functions as a buffer layer for relieving thermal stress between the semiconductor chip and the package. Particularly, in order to further reduce the thermal stress problem, a material having a low modulus of elasticity is applied only to a part of the surface of the semiconductor chip and the package facing the package, within the range of securing the mechanical stability of the semiconductor chip and the package assembly. However, since the adhesive having a low elastic modulus has a low viscosity, even when a minimum amount is applied by a coating method (dispensing method) commonly used in a semiconductor process, the semiconductor chip and the package are spread widely in an irregular shape along the bonding surface, There is a problem that it is difficult for a designer to control the joint area within a limited area reproducibly.

Patent Registration No. 10-0450004 (September 14, 2004)

SUMMARY OF THE INVENTION The present invention has been conceived to solve the above problems, and an object of the present invention is to provide a die bonding substrate having a plurality of holes inserted between a semiconductor chip and a package, Bonding area) between the semiconductor chip and the package so as to reduce the thermal stress problem between the semiconductor chip and the package, and a method of die bonding the semiconductor chip using the substrate.

A substrate for die bonding according to an embodiment of the present invention is interposed between a semiconductor chip 100 and a package 200 for fixing the semiconductor chip 100 to adjust a bonding area of the semiconductor chip 100 A plurality of holes 310 arranged on a plurality of circumferences formed on the basis of a center point of the bonding area of the semiconductor chip 100. The plurality

The plurality of holes 310 are spaced apart from each other by a predetermined first distance so as to control a bonding area of the semiconductor chip 100.

And the plurality of circumferences are spaced apart from each other by a predetermined second distance so as to adjust a bonding area of the semiconductor chip 100. [

The plurality of holes 310 are formed to have a predetermined diameter so that the adhesive 400 can be sucked by the capillary phenomenon.

A semiconductor chip assembly according to another embodiment of the present invention includes the die bonding substrate 300; A package 200 on which the lower surface of the substrate 300 for die bonding is fixed; An adhesive 400 applied to an upper surface of the die bonding substrate 300; And a semiconductor chip (100) fixed to the die bonding substrate (300) by the adhesive (400).

According to another embodiment of the present invention, a method of die bonding a semiconductor chip includes the steps of: (S100) fixing the die bonding substrate 300 to a package 200; A step (S200) of applying an adhesive agent (400) to an upper surface of the die bonding substrate (300); (S300) of placing the semiconductor chip (100) on the upper surface of the die bonding substrate (300) coated with the adhesive (400); A step (S400) of pressing the semiconductor chip (100) so that the semiconductor chip (100) and the die bonding substrate (300) are in close contact with each other; And curing the adhesive 400 (S500).

As described above, according to the present invention, by controlling the diffusion area of the adhesive applied to the semiconductor chip by using the substrate for die bonding having a plurality of holes inserted between the semiconductor chip and the package, the thermal expansion of the semiconductor chip and the package- The thermal stress caused by the coefficient difference can be reduced.

1 is an illustration of an adhesive applied to a package according to the prior art;
2 is an illustration of an example of a widely diffused adhesive between a package and a semiconductor chip according to the prior art;
3 is an illustration of an example of a substrate for die bonding according to an embodiment of the present invention.
4 is an illustration of an adhesive applied to a die bonding substrate according to an embodiment of the present invention.
FIG. 5 is an exemplary view showing an adhesive spread on a substrate for die bonding according to an embodiment of the present invention; FIG.
FIG. 6 is an exemplary view showing an example in which the adhesive applied on the substrate for die bonding in the semiconductor chip assembly according to another embodiment of the present invention is sucked into the hole by capillary phenomenon to restrict diffusion.
7 is a flowchart of a method of die bonding a semiconductor chip according to still another embodiment of the present invention.

It is to be understood that the words or words used in the present specification and claims are not to be construed in a conventional or dictionary sense and that the inventor can properly define the concept of a term to describe its invention in the best way And should be construed in accordance with the meaning and concept consistent with the technical idea of the present invention. Therefore, the embodiments described in the present specification and the configurations shown in the drawings are merely the most preferred embodiments of the present invention and are not intended to represent all of the technical ideas of the present invention. Therefore, various equivalents It should be understood that water and variations may be present. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is an exemplary view of a substrate for die bonding according to an embodiment of the present invention, FIG. 4 is an exemplary view of an adhesive applied to a substrate for die bonding according to an embodiment of the present invention, and FIG. Fig. 6 is an exemplary diagram showing an example in which an adhesive applied to a substrate for die bonding according to an embodiment is diffused.

3 to 5, a substrate for die bonding according to an embodiment of the present invention is interposed between a semiconductor chip 100 and a package 200 for fixing the semiconductor chip 100, A plurality of holes (310) arranged on a plurality of circumferences formed on the basis of a center point of a bonding area of the semiconductor chip (100), in a substrate (300) for die bonding for adjusting a bonding area of the chip . That is, unlike the prior art, a hole 310 is formed between the semiconductor chip 100 and the package 200 through the die-bonding substrate 300 and through the die-bonding substrate 300 in the vertical direction So that the adhesive 400 is sucked. Thus, the diffusion area (i.e., junction area) of the adhesive applied to the semiconductor chip can be controlled (see FIG. 5). Therefore, after the die bonding, the thermal stress caused by the difference in thermal expansion coefficient between the semiconductor chip and the package can be reduced.

The plurality of holes 310 are spaced apart from each other by a predetermined first distance so as to control a bonding area of the semiconductor chip 100. In addition, the plurality of circumferences are spaced apart from each other by a predetermined second distance so as to adjust a bonding area of the semiconductor chip 100. The plurality of holes 310 may be formed to have a predetermined diameter so that the adhesive 400 can be sucked by the capillary phenomenon. The predetermined first distance, the predetermined second distance, and the predetermined length may be set differently according to the joint area that the designer intended. That is, the area to which the adhesive material 400 is applied between the semiconductor chip 100 and the die bonding substrate 300 is set to be the predetermined first distance, the predetermined second distance, Distance and the predetermined length.

FIG. 6 is an exemplary diagram illustrating that the adhesive applied to the substrate for die bonding in the semiconductor chip assembly according to another embodiment of the present invention is sucked into the hole by capillary phenomenon to restrict diffusion. Referring to FIG. 6, a semiconductor chip assembly according to another embodiment of the present invention includes the die-bonding substrate 300; A package 200 on which the lower surface of the substrate 300 for die bonding is fixed; An adhesive 400 applied to an upper surface of the die bonding substrate 300; And a semiconductor chip (100) fixed to the die bonding substrate (300) by the adhesive (400). That is, in contrast to the prior art in which the semiconductor chip and the package are directly bonded by an adhesive, there is a difference in that the die bonding substrate is interposed between the semiconductor chip and the package. Accordingly, since a part of the adhesive 400 is sucked into the hole 310 formed according to the intended bonding area of the designer by the capillary phenomenon, the bonding area between the semiconductor chip 100 and the die bonding substrate 300 can be adjusted You can.

7 is a flowchart of a method of die bonding a semiconductor chip according to another embodiment of the present invention. Referring to FIG. 7, a method of die bonding a semiconductor chip according to another embodiment of the present invention includes: (S100) fixing the die bonding substrate 300 to a package 200; A step (S200) of applying an adhesive agent (400) to an upper surface of the die bonding substrate (300); (S300) of placing the semiconductor chip (100) on the upper surface of the die bonding substrate (300) coated with the adhesive (400); A step (S400) of pressing the semiconductor chip (100) so that the semiconductor chip (100) and the die bonding substrate (300) are in close contact with each other; And curing the adhesive 400 (S500).

In the step S100 of fixing the die bonding substrate 300 to the package 200, the die bonding substrate 300 may be fixed to the package 200 with an adhesive 400 or the like.

In step S400 of pressing the semiconductor chip 100, a part of the adhesive agent 400 is sucked into the hole 310 formed according to the intended bonding area by the capillary phenomenon. Accordingly, the bonding area between the semiconductor chip 100 and the die bonding substrate 300 can be adjusted.

In step S500 of curing the adhesive 400, the semiconductor chip 100 is fixed to the die bonding substrate 300, thereby completing the semiconductor chip assembly.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory only and are not restrictive of the invention, as claimed, and will be fully understood by those of ordinary skill in the art. The present invention is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and variations are possible within the scope of the present invention, and it is obvious that those parts easily changeable by those skilled in the art are included in the scope of the present invention .

100 semiconductor chip
200 packages
300 Die bonding substrate
310 holes
400 Adhesive

Claims (5)

A die bonding substrate (not shown) interposed between the semiconductor chip 100 and the package 200 for fixing the semiconductor chip 100 to adjust the bonding area, which is the diffusion area of the adhesive applied to the semiconductor chip 100 300,
And a plurality of holes (310) arranged on a plurality of circumferences formed on the basis of a center point of a bonding area of the semiconductor chip (100)
The plurality of holes 310 are spaced apart from each other by a predetermined first distance so as to control a bonding area of the semiconductor chip 100,
Wherein the plurality of circumferences are spaced apart from each other by a predetermined second distance so as to control a bonding area of the semiconductor chip. delete delete A substrate (300) for die bonding according to claim 1;
A package 200 on which the lower surface of the substrate 300 for die bonding is fixed;
An adhesive 400 applied to an upper surface of the die bonding substrate 300; And
A semiconductor chip (100) fixed to the die bonding substrate (300) by the adhesive (400);
≪ / RTI > (S100) of fixing the die bonding substrate 300 of claim 1 to the package 200;
A step (S200) of applying an adhesive agent (400) to an upper surface of the die bonding substrate (300);
(S300) of placing the semiconductor chip (100) on the upper surface of the die bonding substrate (300) coated with the adhesive (400);
A step (S400) of pressing the semiconductor chip (100) so that the semiconductor chip (100) and the die bonding substrate (300) are in close contact with each other; And
Curing the adhesive 400 (S500);
And bonding the semiconductor chip to the semiconductor chip.
KR1020150121952A 2015-08-28 2015-08-28 A substrate for die bonding and a die bonding method of semiconductor chip using the same KR101663640B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100450004B1 (en) 1994-12-26 2004-09-24 히다치 가세고교 가부시끼가이샤 Laminating method using laminating film-like organic die-bonding material, die-bonding method, laminating device, die-bonding device, semiconductor device and method for manufacturing semiconductor device
JP2007012714A (en) * 2005-06-28 2007-01-18 Rohm Co Ltd Semiconductor device
KR20110123038A (en) * 2010-05-06 2011-11-14 주식회사 하이닉스반도체 Stacked semiconductor package and method for fabricating the same
KR20130072294A (en) * 2011-12-22 2013-07-02 앰코 테크놀로지 코리아 주식회사 Semiconductor package and method for manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100450004B1 (en) 1994-12-26 2004-09-24 히다치 가세고교 가부시끼가이샤 Laminating method using laminating film-like organic die-bonding material, die-bonding method, laminating device, die-bonding device, semiconductor device and method for manufacturing semiconductor device
JP2007012714A (en) * 2005-06-28 2007-01-18 Rohm Co Ltd Semiconductor device
KR20110123038A (en) * 2010-05-06 2011-11-14 주식회사 하이닉스반도체 Stacked semiconductor package and method for fabricating the same
KR20130072294A (en) * 2011-12-22 2013-07-02 앰코 테크놀로지 코리아 주식회사 Semiconductor package and method for manufacturing the same

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