CN206022359U - Memory chip stack package structure - Google Patents
Memory chip stack package structure Download PDFInfo
- Publication number
- CN206022359U CN206022359U CN201620925315.1U CN201620925315U CN206022359U CN 206022359 U CN206022359 U CN 206022359U CN 201620925315 U CN201620925315 U CN 201620925315U CN 206022359 U CN206022359 U CN 206022359U
- Authority
- CN
- China
- Prior art keywords
- pinboard
- chip
- gold thread
- window
- solder joint
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
This utility model is related to a kind of memory chip stack package structure, including the substrate with two sides signals layer, pinboard is connected between the adjacent chip to be packaged of each two, the window for routing is provided with the middle part of the pinboard, and the solder joint on each chip to be packaged near window is placed through the window of pinboard above the chip and is welded by gold thread with pinboard；The pinboard is welded by gold thread with substrate.This utility model realizes solder joint by chip central distribution to surrounding by pinboard, so as to avoid, using wafer level Technology, reducing technology difficulty, so as to reduce cost.Further, since first realizing the interconnection of chip and pinboard, the size of pinboard can be arranged according to demand, the switching board size of lower layer chip can be done greatly, it is to avoid gold thread and the distribution of upper strata Chip Vertical, the special film that gold thread can not be used to be embedded in, reduce price, reduce technology difficulty.
Description
Technical field
This utility model belongs to technical field of semiconductor encapsulation, in particular to a kind of memory chip stack package structure.
Background technology
With flourishing for electronic industry, electronics technology constantly evolution, electronic product is also towards light, thin, short, little
Trend is designed.With the increase of microminiaturization and high operating techniques demand, multiple chips can be incorporated in a packaging structure, with
The capacity or systematic functional requirement of more than twice is reached, such as, in conventional Multichip stacking encapsulation construction, which is
By multiple chip-stacked and sealing in an encapsulating material.Common chip welding spot position distribution in chip edge, easy gold thread
Welding, realizes stacked package, but the memory chip for solder joint in the middle of chip, such as dynamic RAM (Dynamic
Radom Access Memory, memory chip) for, realize that stacked package is relatively difficult.
In general, storage core flake products, it is known that single-chip package technology among common structure as shown in Figure 1,
Chip is tipped upside down on substrate.Which mainly includes a substrate 5a, and on substrate 5a, one chip 1a of back-off, has a window on substrate 5a
8a, welds a plurality of bonding wire 3a in substrate window 8a, and for the connection of chip 1a and substrate circuit, chip 1a and substrate 5a is pushed up
Wrapped up with plastic packaging material 6a at end.And a plurality of external terminal 4a are set on substrate, for the connection of substrate circuit and external circuit.
In said structure, as memory chip solder joint is located at chip central authorities, by welding gold thread 3a's in the 8a that opens a window
Form realizes the electric connection of chip, practical reliable.But package body structure known to this, can only carry out the encapsulation of single-chip, no
Stacking can be realized.For realizing that capacity is double, packaging density is improved, those skilled in the art's consideration is using storage as shown in Figure 2
Device chip stack package structure.
In fig. 2, two stacked chips realize that front mounts, it was demonstrated that welding gold thread 14b and 3b, and therefore substrate 5b is complete base
Hardened structure, it is no longer necessary to which window is welded for gold thread.In this encapsulating structure, comprising a complete substrate 5b, substrate 5b following tables
Face is similarly external terminal 4b.Except for the difference that, before lower layer chip 1b with upper strata chip 2b pasters, need to carry out external solder joint
The solder joint for being located at memory chip center is redistributed to chip surrounding by redistribution, makes memory chip organization meet weldering
Point surrounding, can carry out direct stacked package.Due to lower layer chip 1b identical with upper strata chip 2b sizes, therefore lower floor's core
There should be a kind of special film 7b between piece 1b and upper strata chip 2b, when upper strata chip 2b is mounted, the gold welded in lower layer chip 1b
Line 14b can be embedded into inside this tunic 7b and gold thread is not damaged, and the upper and lower layers of chips that can bond.The equal gold thread of upper and lower layers of chips
After the completion of welding, by resin 6b encapsulating protections.
This package body structure, two chips achieve stacked package in the way of the attachment of front, however, in this stacked package
In body structure, the solder joint of two chips is required to redistribute, and belongs to wafer Wiring technique again, and by disk, factory completes, equipment, technology
Cost requirement is higher, needs mask plate customized, expensive.In addition, in the stack package structure of Fig. 2, for being bonded with down
The film of layers of chips, gold thread can be embedded in, expensive, and mount technology for paster (DIE Bond) craft precision require compared with
Height, increased technology difficulty, and cost of implementation is high.
As can be seen here, above-mentioned known multi-chip package technology can realize that memory chip capacity is double, improve chip
Packaging density, but expensive, it is not provided simultaneously with the high function of high I/O density and the demand of low cost.
Content of the invention
This utility model aims to overcome that above-mentioned the deficiencies in the prior art and provides a kind of memory chip stacked package
Structure, in the case where packaging body chip density is improved, technique realizes that difficulty is relatively low to the encapsulating structure.
Realize that the technical scheme that this utility model purpose is adopted is a kind of memory chip stack package structure, including having
The substrate of two sides signals layer, between the adjacent chip to be packaged of each two is connected with pinboard, opens in the middle part of the pinboard
There is the window for routing, the solder joint on each chip to be packaged near window is placed through the window of pinboard above the chip
Welded by gold thread with pinboard；The pinboard is welded by gold thread with substrate.
This utility model realizes solder joint by chip central distribution to surrounding by pinboard, so as to avoid using wafer level
Technology, reduces technology difficulty, so as to reduce cost.Further, since first realizing the interconnection of chip and pinboard, transfer
The size of plate can be arranged according to demand, can be done greatly the switching board size of lower layer chip, it is to avoid gold thread and upper strata chip
Vertical distribution, the special film that gold thread can not be used to be embedded in reduce price, reduce technology difficulty.
Description of the drawings
Fig. 1 is a kind of known memory chip single die package schematic diagram.
Fig. 2 is a kind of existing memory chip Multichip stacking encapsulation structural representation.
Fig. 3 is according to a cross-sectional view of the present utility model.
Fig. 4 is according to pinboard in a kind of memory chip stack package structure that is realized by pinboard of the present utility model
Top schematic diagram.
Specific embodiment
As shown in figure 3, this utility model memory chip stack package structure is application pinboard, cheap beating is combined
Line bonding technology (Wire Bonding) at least will be set together in layers of chips stacking combination, and avoid price height, technique
Complicated disk Wiring technique again, that is, increased the I/O density and function of packaging body, reduce the realisation difficulty of technique, reduce
Production cost.
It is to reach technological means and effect that predetermined utility model purpose is taken for this utility model is expanded on further, with
Lower combination accompanying drawing and preferred embodiment, to according to multichip packaging structure of the present utility model its specific embodiment, structure, spy
Levy and its effect, describe in detail as after.
According to the first specific embodiment of the present utility model, a kind of memory chip stack package structure is disclosed, Fig. 3 is this
The schematic cross-section of multi-memory chip stack package structure, Fig. 4 are for switching in the multi-memory chip stack package structure
The top schematic diagram of plate.
Referring initially to shown in accompanying drawing 3 and Fig. 4, the stack package structure its be illustrated as of the present utility model preferable implementing knot
Structure, memory chip stacked package body of the present utility model mainly include a substrate 5c, lower layer chip 1c, a upper strata chip
2c, how several external terminal solder balls 4c, once pinboard 12c, two pad 13c, pinboard 17c on.This practicality is new
Pinboard used by type meets the general concept of wiring board, but typically only face line layer, for gold thread welding inside and outside pin with
And lead between interior outer pin, it is respectively positioned on this sandwich circuit layer.
This example memory chip stack package structure technique is realized：
Upper and lower layers of chips (2c, 1c) is adhered on the pinboard 12c for separately designing, the switching of upper and lower two chip
Board size can be with identical, it is also possible to different.Lower layer chip 1c being bonded on lower pinboard 12c is mounted on substrate 5c, profit
The welding that lower layer chip 1c and lower pinboard 12c are realized with the gold thread 15c in the window 8d opened on lower pinboard 12c, by gold
Line 14c realizes the electrical interconnection of lower pinboard 12c and substrate 5c, achieves indirectly electrically connecting for lower layer chip 1c and substrate 5c
Connect.
Two pad 13c are pasted in the upper surface of lower pinboard 12c, in order to support and be bonded with chip 2c.By upper strata core
Piece 2c is affixed on pad 13c, equally, carries out upper strata using the window 8d reserved on the pinboard 17c above the chip 2c of upper strata
The gold thread 16c welding of chip 2c, then carry out welding of the pinboard 17c to the gold thread 3c between substrate 5c.This utility model will
The thickness of pad 13c is sought more than the height of gold thread 15c, during in order to protecting upper strata chip 2c to mount, gold thread 15c is injury-free.Gold
After the completion of wire bonding, the parcel that carries out plastic packaging material 6c to whole packaging body is opened including the region on the upside of chip, substrate and pinboard
Upper external terminal 4c is planted in the region of window, whole packaging body, for the external electrical connection of whole packaging body.
As shown in figure 4, in above-mentioned lower pinboard 12c structures, being distributed according to solder joint in lower layer chip 1c, in lower pinboard
Fenestration 8d is made on 12c, realizes that solder joint chip internally and the gold thread 15c of lower pinboard 12c are welded, lower pinboard
12c is welded by gold thread 14c with substrate 5c, realize indirectly the electrical connection of lower layer chip 1c and substrate 5c, it is to avoid wafer is again
The complicated processing procedure of Wiring technique, reduces expense.
By designing the size of pinboard, outer pin solder joint 11d on lower pinboard 12c is positioned over and is fanned out to upper strata chip 2c
Region, when such upper strata chip 2c pastes, do not interfere with gold thread 14c regions.The surrounding of fenestration 8d in lower pinboard 12c
The interior pin solder joint 10d for gold thread welding is dispersed with, solder joint directly passes through gold thread with the solder joint in lower layer chip 2c in these
15c connects.Be dispersed with the outer pin solder joint 11d of equal number in the edge of pinboard 12c, interior pin solder joint 10d with draw outward
Foot solder joint 11d is corresponded, and the solder joint on outer pin solder joint 11d and substrate 5c realizes electrical connection, lower pinboard by gold thread
Inside and outside solder joint on 12c is realized by wiring on pinboard.
The logical principle of the electrical connection of upper pinboard 17c and upper strata chip 2c is same as electrically connecting for lower pinboard and lower layer chip
Connect, here is omitted.
Lower layer chip 1c is located at the gold thread 15c in window 8c, supports protection by two pad 13c, therefore also will not be because upper
Layer chip attachment and be damaged.The two structures are applied in combination, it is to avoid using the film for allowing gold thread embedded, have saved cost,
Reduce technique and realize difficulty.
It is illustrated using the stacked package of two pinboards only for two chips above, this utility model is encapsulated
Structure is applied to the stacked package of multiple chips, when number of chips is more than two, needs and number of chips identical pinboard
Stacking use is carried out, concrete structure is same as the previously described embodiments with using method, and here is omitted.
The above, is only preferred embodiment of the present utility model, not this utility model is done any formal
Restriction, although this utility model is disclosed above with preferred embodiment, but is not limited to this utility model, any ripe
Professional and technical personnel is known, in the range of without departing from technical solutions of the utility model, when in the technology using the disclosure above
Hold the Equivalent embodiments that makes a little change or be modified to equivalent variations, as long as without departing from technical solutions of the utility model
Hold, according to technical spirit of the present utility model to any simple modification made for any of the above embodiments, equivalent variations and modification, still
Belong in the range of technical solutions of the utility model.
Claims (3)
1. a kind of memory chip stack package structure, including the substrate with two sides signals layer, is characterised by：Adjacent in each two
Pinboard is connected between the chip to be packaged for connecing, the window for routing is provided with the middle part of the pinboard, and each is to be packaged
Solder joint on chip near window is placed through the window of pinboard above the chip and is welded by gold thread with pinboard；Described turn
Fishplate bar is welded by gold thread with substrate.
2. memory chip stack package structure according to claim 1, it is characterised in that：Pinboard be connected to the switching
Pad, height of the spacer thickness more than the gold thread by welding at the pinboard window is provided between the chip of plate upper surface
Degree.
3. memory chip stack package structure according to claim 2, it is characterised in that：Near window on the pinboard
Position at be provided with multiple interior pin solder joints, pinboard edge is provided with multiple outer pins welderings being connected with the interior pin solder joint
Point；Solder joint on each chip to be packaged described near window is placed through the window of pinboard and the pinboard above the chip
On interior pin solder joint welded by gold thread；Outer pin solder joint realizes electrical connection with the solder joint on substrate by gold thread.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620925315.1U CN206022359U (en) | 2016-08-23 | 2016-08-23 | Memory chip stack package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620925315.1U CN206022359U (en) | 2016-08-23 | 2016-08-23 | Memory chip stack package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206022359U true CN206022359U (en) | 2017-03-15 |
Family
ID=58249663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620925315.1U Expired - Fee Related CN206022359U (en) | 2016-08-23 | 2016-08-23 | Memory chip stack package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206022359U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449612A (en) * | 2016-08-23 | 2017-02-22 | 武汉寻泉科技有限公司 | Stacking and packaging structure for memory chips |
-
2016
- 2016-08-23 CN CN201620925315.1U patent/CN206022359U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449612A (en) * | 2016-08-23 | 2017-02-22 | 武汉寻泉科技有限公司 | Stacking and packaging structure for memory chips |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170315 Termination date: 20200823 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |