CN104051450B - Semiconductor packages - Google Patents
Semiconductor packages Download PDFInfo
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- CN104051450B CN104051450B CN201410091379.1A CN201410091379A CN104051450B CN 104051450 B CN104051450 B CN 104051450B CN 201410091379 A CN201410091379 A CN 201410091379A CN 104051450 B CN104051450 B CN 104051450B
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- semiconductor packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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Abstract
The present invention provides a kind of semiconductor packages, including the first semiconductor packages and the second semiconductor packages.First semiconductor packages includes the first substrate, attaches face with the first element and attaches face relative to the first projection that the first element attaches face.The first element that second semiconductor packages is bonded to the first semiconductor packages attaches face, including the second substrate, dynamic random access memory, decoupling capacitance and multiple conductive structures.There is the second element to attach face and face is attached relative to the second projection that the second element attaches face for second substrate.Dynamic random access memory is fixed on the second element attaching face.Decoupling capacitance is fixed on the second element attaching face.Multiple conductive structures are arranged on the second projection attaching face, and are connected to the first element attaching face.Disclosed semiconductor packages, can make the additional areas of the first semiconductor packages and the original package dimension of the second semiconductor packages maintenance without being supplied to decoupling capacitance in semiconductor packages.
Description
Technical field
The present invention is related to a kind of semiconductor packages, particularly with regard to a kind of laminate packaging formula (package on
Package, POP) semiconductor packages.
Background technology
Laminate packaging formula (package on package, POP) semiconductor packages is that vertical junction closes system single chip
(system-on-chip, SOC) encapsulates a kind of integrated antenna package with memory package (memory package).Stacking envelope
Dress formula semiconductor packages can stack two or more packaging bodies by the way that standard interface (standard interface) is mutual, with
The signal of transmission between the two.Laminate packaging formula semiconductor packages can improve such as mobile phone, personal digital assistant sum
The component density of the device of word camera.
Input/output (the input/ encapsulated due to the system single chip positioned at bottom of laminate packaging formula semiconductor packages
Output, I/O) connection accelerate can by the memory package positioned at top and positioned at bottom system single chip encapsulation
Between height limitation, so be difficult to design extra electronic component in traditional laminate packaging formula semiconductor packages be to strengthen
The performance for single-chip package of uniting.
Therefore, in this technical field, it is necessary to a kind of laminate packaging formula semiconductor packages of Improvement type.
The content of the invention
In view of this, it is an object of the invention to provide a kind of semiconductor packages of Improvement type.
One embodiment of the invention provides a kind of semiconductor packages.The semiconductor packages includes the first semiconductor packages and the
Two semiconductor packages.First semiconductor packages includes the first substrate, and face is attached and relative to the first element patch with the first element
First projection in attached face attaches face.The first element that second semiconductor packages is bonded to the first semiconductor packages attaches face, including
Second substrate, dynamic random access memory, decoupling capacitance and multiple conductive structures.Second substrate has the second element
Attaching face and the second projection attaching face that face is attached relative to the second element.Dynamic random access memory is fixed in second
On element attaching face.Decoupling capacitance is fixed on the second element attaching face.Multiple conductive structures are arranged on the attaching of the second projection
On face, and it is connected to the first element attaching face.
Another embodiment of the present invention provides a kind of semiconductor packages.The semiconductor packages includes pedestal, dynamic random and deposited
Access to memory is encapsulated and external power source.The dynamic random access memory encapsulation, is bonded to the pedestal, wherein the dynamic
Random access memory encapsulation includes：Substrate；Dynamic random access memory, it is affixed on the substrate；And decoupling
Electric capacity is closed, is fixed in substrate, and separated with the dynamic random access memory.The external power source, is arranged at institute
State on pedestal, and separated with dynamic random access memory encapsulation.
Further embodiment of this invention provides a kind of semiconductor packages.The semiconductor packages includes：Pedestal；System single chip
Encapsulation, is bonded to the pedestal；Memory package, is bonded to the system single chip encapsulation, and wherein memory package includes going
Coupled capacitor, is fixed in the memory package；And external power source, be arranged on the pedestal, and with the system list
Chip package is separated.
Disclosed semiconductor packages, it is possible to provide extra decoupling capacitance, and can make in semiconductor packages
System single chip encapsulates extra face of the package dimension original with memory package maintenance without being supplied to decoupling capacitance
Product.
For having read follow-up those skilled in the art as the better embodiment shown by each accompanying drawing and content
For, each purpose of the invention is obvious.
Brief description of the drawings
Fig. 1 is the sectional view of the semiconductor packages of one embodiment of the invention.
Fig. 2 is the top view of the semiconductor packages of one embodiment of the invention.
Embodiment
Some vocabulary have been used in claims and specification to censure specific component.Technology in art
Personnel are, it is to be appreciated that hardware manufacturer may call same component with different nouns.The claims and explanation
Book is used as the standard of differentiation with the difference of component functionally not in the way of the difference of title is used as differentiation component
Then.It is open term in the " comprising " mentioned in claims and specification, therefore should be construed to " including but do not limit
In ".In addition, " coupling " one word includes any direct and indirect electrical connection herein.Therefore, if described in text first dress
Put and be coupled to second device, then the second device can be directly electrically connected to by representing the first device, or pass through other devices
Or connection means are electrically connected to the second device indirectly.
In order to which the purpose of the present invention, feature and advantage can be become apparent, special embodiment below, and coordinate appended
Diagram, is described in detail.Description of the invention provides different embodiments to illustrate the technology of different embodiments of the present invention
Feature.Wherein, the explanation that is configured to of each element in embodiment is used, and is not used to the limitation present invention.And schema mark in embodiment
Number part repeat, be for the purpose of simplifying the description, to be not meant as the relevance between not be the same as Example.
Fig. 1 is the sectional view of the semiconductor packages 500 of one embodiment of the invention.Fig. 2 partly leads for one embodiment of the invention
The top view of body encapsulation 500.In the present embodiment, above-mentioned semiconductor packages 500 is laminate packaging formula (package on
Package, POP) semiconductor packages.In an embodiment of the present invention, above-mentioned laminate packaging formula semiconductor packages 500 is included at least
Wafer scale (wafer-leveled) semiconductor packages of two vertical stackings.Above-mentioned laminate packaging formula semiconductor packages 500 includes
Memory package (the memory that system single chip (system-on-chip, SOC) is encapsulated and is stacked in SOC encapsulation
Package), wherein SOC encapsulation for example, logical wrapper (logic package), and memory package is, for example, dynamic random
Access memory (dynamic random access memory, DRAM) encapsulation.Because the design rule of memory package leads to
The design rule that SOC is encapsulated can be often more than, so memory package there can be enough spaces, make memory and decoupling capacitance
(decoupling capacitor) is affixed thereon, with the power supply transport net for the DRAM elements for strengthening memory package
(power delivery network, PDN), or even strengthen the central processing unit (central of SOC encapsulation
Processing unit, CPU) and painting processor (graphic processing unit, GPU) power supply transport net.
Also, each semiconductor packages of above-mentioned semiconductor packages 500 can be chip package (flipchip package), above-mentioned to cover
Semiconductor element is connected to base by crystalline substance encapsulation using the conductive structure of such as copper post shape projection (copper pillar bumps)
Seat (base).
Fig. 1 is refer to, semiconductor packages 500 includes pedestal (base) 200, is fixed in the first semiconductor on pedestal 200
Encapsulation 206, and the second semiconductor packages 232 for stacking and being fixed in the first semiconductor packages 206.Implement in the present invention one
In example, said base 200, for example, printed circuit board (PCB) (print circuit board, PCB) can be by polypropylene
(polypropylene, PP) is formed.Should be appreciated that said base 200 can be individual layer (single layer) structure or multilayer
(multilayer) structure.The element that multiple wire (not shown) and weld pad (not shown) are arranged at pedestal 200 attaches face
On (device attach surface) 202.In an embodiment of the present invention, above-mentioned wire may include signal line segment（signal
trace segments）Or ground connection line segment, above-mentioned signal line segment or ground connection line segment can be used for above-mentioned first semiconductor packages 206
Input/output (input/output, I/O) is connected.Also, weld pad is arranged at the element of pedestal 200 and attached on face 202, connection
To the different ends of multiple wires.Above-mentioned weld pad is used to make the first semiconductor packages 206 affixed (mounted) thereon.
As shown in figure 1, above-mentioned first semiconductor packages 206 is fixed in by bonding process (bonding process)
The element for stating pedestal 200 is attached on face 202.In the present embodiment, above-mentioned first semiconductor packages 206 is system single chip
(SOC) encapsulate, such as logical wrapper (logic package).Above-mentioned first semiconductor packages 206 includes the first substrate（body）
208, there is the first element to attach face 210 and face 212 is attached relative to the first projection that above-mentioned first element attaches face 210 for it.
Above-mentioned first substrate 208 may include circuit 216, metal pad 218 and metal pad 220.Above-mentioned metal pad 218 is arranged at electricity
The top that face 210 is attached close to the first element on road 216, and above-mentioned metal pad 220 be arranged at circuit 216 close to the
One projection attaches the bottom in face 212.The circuit 216 of above-mentioned first semiconductor packages 206 is mutual by multiple first conductive structures 214
The circuit of said base 200 is connected to, and the first projection that the first conductive structure 214 is arranged at the first substrate 208 attaches face 212
On.Also, above-mentioned first conductive structure 214 contacts said base 200.In an embodiment of the present invention, the above-mentioned first conductive knot
Structure 214 may include conductive lug structure, conductive columns thing structure, the wire knot of for example, copper bump structure or solder bump structures
Structure or conductive adhesive structure (conductive paste structure).Logic element 222 is using Flip Chip and passes through conduction
Structure 228 is fixed in above-mentioned first element of above-mentioned first substrate 208 and attached on face 210.In an embodiment of the present invention, it is above-mentioned
Logic element 222 may include central processing unit (CPU), painting processor (GPU), dynamic RAM Controller
(DRAM controller) or above-mentioned any combination.In the present embodiment, above-mentioned logic element 222 includes central processing unit
And/or painting processor (GPU) 224 and the dynamic random access memory control integrated with above-mentioned CPU and/or GPU224 (CPU)
Device (DRAM controller) 226 processed.In an embodiment of the present invention, above-mentioned conductive structure 228 may include for example, copper bump
Conductive lug structure, conductive columns thing structure, conductor structure or the conductive adhesive structure of structure or solder tappet structure
(conductive paste structure).In an embodiment of the present invention, can be in above-mentioned logic element 222 and above-mentioned first
Primer filling material or primer (an underfill material or an are imported in gap between substrate 208
underfill)230.In an embodiment of the present invention, primer filling material or primer 230 may include that capillary fills glue
(capillary underfill, CUF), contoured bottom filling glue (molded underfill, MUF), non-conductive insulating cement
(nonconductive paste, NCP), non-conductive dielectric film (nonconductive film, NCF) or above-mentioned any group
Close.
It refer again to Fig. 1.Second semiconductor packages 232, can be stacked to above-mentioned first semiconductor packages by bonding process
206 above-mentioned first element is attached on face 210.In the present embodiment, above-mentioned second semiconductor packages 232 can be memory envelope
Dress, for example, dynamic random access memory (DRAM) are encapsulated.Above-mentioned second semiconductor packages 232 includes the second substrate 234, tool
There is the second element to attach face 236 and attach face 238 relative to the second projection that above-mentioned second element attaches face 236.Similar to upper
The first substrate 208 is stated, above-mentioned second substrate 234 may include circuit 250, metal pad 248 and metal pad 252.Above-mentioned metal
Weld pad 248 is arranged at the top that face 236 is attached close to the second element of circuit 250, and above-mentioned metal pad 252 is arranged at electricity
The bottom that face 238 is attached close to the second projection on road 250.The circuit 250 of above-mentioned second semiconductor packages 232 passes through multiple
Two conductive structures 240 are interconnected to the circuit 216 of above-mentioned first semiconductor packages 206, and the second conductive structure 240 be arranged at it is above-mentioned
Second projection of the second substrate 234 is attached on face 238.Also, above-mentioned second conductive structure 240 contacts above-mentioned first semiconductor package
The first element for filling 206 the first substrate 208 attaches face 210.In an embodiment of the present invention, above-mentioned second conductive structure 240
May include the conductive lug structures of for example, copper bump structure or solder bump structures, conductive columns thing structure, conductor structure or
Conductive adhesive structure (conductive paste structure).In an embodiment of the present invention, above-mentioned second semiconductor packages
232 may include an at least dynamic random access memory (DRAM) element, be solidly connected to the second element patch of above-mentioned second substrate 234
On attached face 236.As shown in figure 1, in the present embodiment, there is three DRAM elements, such as DRAM elements 242, the and of DRAM elements 244
DRAM elements 246, are solidly connected to the second element of above-mentioned second substrate 234 and attach on face 236.Also, above-mentioned DRAM elements 242 lead to
Conducting resinl 243 is crossed to be solidly connected on the second element of above-mentioned second substrate 234 attaching face 236.Above-mentioned DRAM elements 244 pass through conduction
Glue 245 is stacked on above-mentioned DRAM elements 242, and above-mentioned DRAM elements 246 are stacked to above-mentioned DRAM elements by conducting resinl 247
On 244.Above-mentioned DRAM elements 242, DRAM elements 244 and DRAM elements 246 can be by bonding wire (bonding wires), such as
Bonding wire 268, bonding wire 270 and bonding wire 272, are coupled to above-mentioned second substrate 234.However, the number of above-mentioned stacking DRAM elements is only
For an embodiment, and it is not used to the limitation present invention.In other embodiments of the present invention, DRAM elements 242 as shown in Figure 1,
DRAM elements 244 and DRAM elements 246 can configure for parallel (side by side).Therefore, above-mentioned DRAM elements 242, DRAM
Element 244 and DRAM elements 246 can be solidly connected to the second element of above-mentioned second substrate 234 by conducting resinl and attached on face 236.
It should be noted that above-mentioned second semiconductor packages 232, such as memory package 232, being only used for encapsulation, at least one is stored
Device element.Therefore, design rule (such as weld pad minimum spacing (the pad minimum of above-mentioned second semiconductor packages 232
Pitch), weld pad size (pad size), circuit critical size (critical dimension of the circuitry)
Deng) it is typically larger than the design rule of such as the first semiconductor packages 206 of system single chip (SOC) encapsulation.Above-mentioned the second half
Second substrate 234 of conductor encapsulation 232 can have enough spaces to make extra decoupling capacitance (decoupling
Capacitor) it is fixed in the second substrate 234 of above-mentioned second semiconductor packages 232.Also, above-mentioned second semiconductor packages
232 the second substrate 234 may include illusory weld pad and dummy circuit, be arranged at the corner of the second substrate 234.Above-mentioned illusory weld pad
It is used to discharge the pressure in the second substrate 234 with dummy circuit, and above-mentioned semiconductor package can be avoided to be mounted in the damage caused when dropping
Wound.Therefore, above-mentioned illusory weld pad and dummy circuit are available for above-mentioned extra decoupling capacitance affixed thereon, and above-mentioned extra
Decoupling capacitance can be electrically coupled to the first semiconductor packages 206 by above-mentioned illusory weld pad and dummy circuit.As shown in figure 1,
In the present embodiment, above-mentioned second semiconductor packages 232 further includes an at least decoupling capacitance (decoupling
Capacitor), the second element of above-mentioned second substrate 234 is fixed in attach on face 236.In the present embodiment, decoupling capacitance
254 and decoupling capacitance 260 be fixed in the second element of above-mentioned second substrate 234 attach face 236 on.Also, above-mentioned DRAM members
Part 242, DRAM elements 244, DRAM elements 246, decoupling capacitance 254 and decoupling capacitance 260 are the element of separation
(discrete devices).In other words, decoupling capacitance 254 and decoupling capacitance 260 and DRAM elements 242, DRAM elements
244th, DRAM elements 246 are separated.As shown in Figure 1 and Figure 2, because above-mentioned decoupling capacitance can design and be fixed in above-mentioned the second half and lead
In body encapsulation 232, and above-mentioned second semiconductor packages 232 is, for example, DRAM encapsulation and its design rule is more than such as logical wrapper
Above-mentioned first semiconductor packages 206 design rule.So above-mentioned first semiconductor packages 206 and above-mentioned second semiconductor package
Fill 232 additional areas that original package dimension can be maintained without being supplied to decoupling capacitance.As shown in Figure 1 and Figure 2, exist
In one embodiment of the invention, in a top view, above-mentioned the first the half of such as logical wrapper (lower section of the second semiconductor packages 232)
The border 280 of first substrate 208 of conductor encapsulation 206 can be with above-mentioned second substrate 234 of above-mentioned second semiconductor packages 232
One border 282 is completely overlapped.In other words, in a top view, above-mentioned second semiconductor packages 232 of for example, DRAM encapsulation is upper
Above-mentioned the first of such as logical wrapper (lower section of the second semiconductor packages 232) can be aligned in by stating the border 282 of the second substrate 234
The border 280 of first substrate 208 of semiconductor packages 206.
As shown in figure 1, in an embodiment of the present invention, above-mentioned second semiconductor packages 232 further includes shaping material
(molding material) 266, the second element for covering above-mentioned second substrate 234 attaches face 236, and including DRAM elements
242nd, DRAM elements 244, DRAM elements 246, bonding wire 268, bonding wire 270, bonding wire 272, decoupling capacitance 254 and decoupling capacitance
260。
It refer again to Fig. 1.At least one external power source (external power supply) is arranged at said base 200
Element attach face 202 on.In the present embodiment, there are two external power sources（Such as external power source 204, external power source 205）If
The element of said base 200 is placed in attach on face 202.In an embodiment of the present invention, said external power supply 204, external power source
Both 205 all separate with the above-mentioned semiconductor packages 232 of first semiconductor packages 206 and second.In the present embodiment, said external
Power supply 204, external power source 205 are used for above-mentioned CPU and/or GPU224 and dynamic random to above-mentioned first semiconductor packages 206
Access memory (DRAM) controller 226, and the DRAM elements 242 of above-mentioned second semiconductor packages 232, DRAM elements 244,
DRAM elements 246 provide power supply.
In an embodiment of the present invention, above-mentioned decoupling capacitance 254 and decoupling capacitance 260 may be coupled to above-mentioned CPU and/
Or GPU224 and/or dynamic random access memory (DRAM) controller 226, to provide compensation electric current and/or offset voltage
(compensation current and/or voltage).Also, above-mentioned decoupling capacitance 254 and decoupling capacitance 260 can
Switching output noise (simultaneous switching output (SSO) noise) while coming from power supply to mitigate, and
Above-mentioned power supply provides electric current and/or voltage to above-mentioned semiconductor packages 500.Therefore, above-mentioned decoupling capacitance 254 and uncoupling electricity
Hold the 260 power supply transport net (power for being used to strengthen the DRAM elements of memory package (above-mentioned second semiconductor packages 232)
Delivery network, PDN), or even strengthen encapsulating the central processing unit of (above-mentioned first semiconductor packages 206) in SOC
(central processing unit, CPU) and painting processor (graphic processing unit, GPU) power supply
Transport net.As shown in figure 1, in an embodiment of the present invention, the above-mentioned design of decoupling capacitance 260 is coupled to above-mentioned logic element
222 CPU and/or GPU224 and said external power supply 204.In the present embodiment, above-mentioned decoupling capacitance 260 passes through electric current road
Footpath 262 (being denoted as dotted line) provides compensation to the CPU and/or GPU224 of the logic element 222 of above-mentioned first semiconductor packages 206
Electric current and/or offset voltage.In other embodiments of the present invention, the above-mentioned design of decoupling capacitance 254 is coupled to above-mentioned DRAM members
Part 242, DRAM elements 244, DRAM elements 246, the dynamic RAM Controller integrated with above-mentioned logic element 222
226 and said external power supply 205.Above-mentioned decoupling capacitance 254 is by current path 264 (being denoted as dotted line) to above-mentioned the second half
Above-mentioned DRAM elements 242, DRAM elements 244, the DRAM elements 246 of conductor encapsulation 232 provide compensation electric current and/or compensation electricity
Pressure.Also, above-mentioned DRAM elements 242, DRAM elements 244, DRAM elements 246 and above-mentioned decoupling capacitance 254, decoupling capacitance
The 260 different conductive structures 252 for attaching face 238 by being arranged on above-mentioned second projection respectively are coupled to above-mentioned first semiconductor
Encapsulation 206.
The embodiment of the present invention provides a kind of semiconductor packages, for example, laminate packaging formula (POP) semiconductor packages.Above-mentioned half
Conductor encapsulation includes the memory package (memory package) of for example, dynamic random access memory (DRAM) encapsulation, heap
It is laminated in system single chip (SOC) encapsulation of for example, logical wrapper (logic package).Because above-mentioned memory package
Design rule (such as weld pad minimum spacing (pad minimum pitch), weld pad size (pad size), circuit critical size
(critical dimension of the circuitry) etc.) it is typically larger than such as said system single-chip (SOC) encapsulation
Design rule, so above-mentioned semiconductor packages be design include extra decoupling capacitance, be fixed in above-mentioned memory package
On.Also, above-mentioned extra decoupling capacitance can be fixed on the illusory weld pad and dummy circuit of above-mentioned memory package, above-mentioned
Illusory weld pad and dummy circuit are used to discharge the pressure in the substrate of above-mentioned memory package, and can avoid above-mentioned semiconductor packages
The damage caused when dropping.In an embodiment of the present invention, the above-mentioned decoupling capacitance for being fixed in above-mentioned memory package is set
Meter is coupled to the above-mentioned logic element said external power supply 204 of said system single-chip (SOC) encapsulation, with to above-mentioned logic element
Compensation electric current and/or offset voltage are provided.Also, above-mentioned decoupling capacitance, which can be designed, is coupled to the above-mentioned of above-mentioned memory package
DRAM elements, above-mentioned dram controller and said external power supply, to provide above-mentioned DRAM elements compensation electric current and/or compensation electricity
Pressure.Therefore, said system single-chip (SOC) encapsulation and above-mentioned memory package can maintain original package dimension without carrying
Supply the additional areas of decoupling capacitance.
The better embodiment of the present invention is the foregoing is only, all equivalent changes done according to the claims in the present invention and is repaiied
Decorations, all should belong to the covering scope of the present invention.
Claims (28)
1. a kind of semiconductor packages, it is characterised in that including：First semiconductor packages and the second semiconductor packages, described first
Semiconductor packages includes：
First substrate, attaches face with the first element and attaches face relative to the first projection that first element attaches face；With
And
Second semiconductor packages, first element for being bonded to first semiconductor packages attaches face, wherein described
Second semiconductor packages includes：
Second substrate, attaches face with the second element and attaches face relative to the second projection that second element attaches face；
Dynamic random access memory, is fixed on the second element attaching face；
Decoupling capacitance, the illusory weld pad being fixed on the second element attaching face of second substrate and dummy circuit
On, and it is coupled to first semiconductor packages；And
Multiple conductive structures, are arranged on the second projection attaching face, and are connected to the described of first semiconductor packages
First element of first substrate attaches face.
2. semiconductor packages as claimed in claim 1, it is characterised in that in a top view, the border of first substrate with
The border of second substrate is completely overlapped.
3. semiconductor packages as claimed in claim 1, it is characterised in that first semiconductor packages also includes logic basis
Part, first element for being fixed in first substrate attaches face.
4. semiconductor packages as claimed in claim 3, it is characterised in that also include：
Pedestal, wherein first semiconductor packages and second semiconductor packages pass through first semiconductor packages
One conductive structure is fixed on the pedestal；And
External power source, is arranged on the pedestal, and is separated with first semiconductor packages and second semiconductor packages.
5. semiconductor packages as claimed in claim 4, it is characterised in that the decoupling capacitance is coupled to the logic element
Both with the external power source.
6. semiconductor packages as claimed in claim 4, it is characterised in that the decoupling capacitance is coupled to the dynamic random
Access memory component, the dynamic RAM Controller and the external power source integrated with the logic element.
7. semiconductor packages as claimed in claim 1, it is characterised in that the dynamic random access memory and described
Decoupling capacitance is spaced apart.
8. semiconductor packages as claimed in claim 1, it is characterised in that the dynamic random access memory and described
Decoupling capacitance attached respectively by being arranged on second projection face different the multiple conductive structures be coupled to it is described
First semiconductor packages.
9. semiconductor packages as claimed in claim 1, it is characterised in that second semiconductor packages also includes extra dynamic
Random access memory, is stacked vertically on the dynamic random access memory, and is electrically connected to described
Two substrates.
10. a kind of semiconductor packages, it is characterised in that including：
Pedestal；
Dynamic random access memory is encapsulated, and is bonded to the pedestal；And
External power source, is arranged on the pedestal, and is separated with dynamic random access memory encapsulation；
Wherein described dynamic random access memory encapsulation includes：
Substrate；
Dynamic random access memory, it is affixed on the substrate；And
On decoupling capacitance, affixed illusory weld pad and dummy circuit on the substrate, and it is coupled to the semiconductor packages
On logical wrapper, and separated with the dynamic random access memory.
11. semiconductor packages as claimed in claim 10, it is characterised in that
The logical wrapper, between dynamic random access memory encapsulation and the pedestal, wherein the logic is sealed
Dress includes：
First substrate, attaches face with the first element and attaches face relative to the first projection that first element attaches face；
Logic element, first element for being fixed in first substrate attaches face；And
Multiple first conductive structures, are arranged on the first projection attaching face, and contact the pedestal.
12. semiconductor packages as claimed in claim 11, it is characterised in that the dynamic random access memory encapsulation passes through
The second projection for being arranged at the substrate of the dynamic random access memory encapsulation attaches multiple second conductive structures in face
It is bonded to first element and attaches face, and contact first element and attaches face.
13. semiconductor packages as claimed in claim 12, it is characterised in that the institute of the dynamic random access memory encapsulation
Stating substrate, there is the second element for attaching face relative to second projection to attach face, and wherein described dynamic random access memory
Device element is fixed on the second element attaching face.
14. semiconductor packages as claimed in claim 12, it is characterised in that the dynamic random access memory and institute
State the different the multiple second conductive structures couplings that decoupling capacitance attaches face by being arranged on second projection respectively
To the logical wrapper.
15. semiconductor packages as claimed in claim 11, it is characterised in that in a top view, the dynamic randon access is deposited
The border and the border of first substrate of the logical wrapper of the substrate of reservoir encapsulation are completely overlapped.
16. semiconductor packages as claimed in claim 11, it is characterised in that the decoupling capacitance is coupled to the logic basis
Both part and the external power source.
17. semiconductor packages as claimed in claim 11, it is characterised in that the decoupling capacitance be coupled to the dynamic with
Machine access memory component, the dynamic RAM Controller and the external power source integrated with the logic element.
18. semiconductor packages as claimed in claim 10, it is characterised in that the dynamic random access memory encapsulation is also wrapped
Extra dynamic random access memory is included, is stacked vertically on the dynamic random access memory, and is electrically connected
It is connected to the substrate of the dynamic random access memory encapsulation.
19. a kind of semiconductor packages, it is characterised in that including：
Pedestal；
System single chip is encapsulated, and is bonded to the pedestal；
Memory package, is bonded to the system single chip encapsulation, and wherein memory package includes decoupling capacitance, the decoupling
Close electric capacity to be fixed in illusory weld pad and the dummy circuit in the memory package, and be coupled to the system single chip envelope
Dress；And
External power source, is arranged on the pedestal, and is separated with system single chip encapsulation.
20. semiconductor packages as claimed in claim 19, it is characterised in that the system single chip encapsulation includes：
First substrate, attaches face with the first element and attaches face relative to the first projection that first element attaches face；
Logic element, is fixed in first element and attaches face；And
Multiple first conductive structures, are arranged on the first projection attaching face, and contact the pedestal.
21. semiconductor packages as claimed in claim 20, it is characterised in that the memory package is deposited for dynamic randon access
Reservoir is encapsulated.
22. semiconductor packages as claimed in claim 21, it is characterised in that the dynamic random access memory wrapper
Include：
Second substrate, attaches face with the second element and attaches face relative to the second projection that second element attaches face；
Dynamic random access memory and the decoupling capacitance, are fixed on the second element attaching face；And
Multiple second conductive structures, are arranged on second projection and attach face, are connected to the described of the system single chip encapsulation
First element of first substrate attaches face.
23. semiconductor packages as claimed in claim 22, it is characterised in that the dynamic random access memory and institute
State element of the decoupling capacitance for separation.
24. semiconductor packages as claimed in claim 22, it is characterised in that in a top view, the dynamic randon access is deposited
The border for first substrate that the border of second substrate of reservoir encapsulation is encapsulated with the system single chip is completely overlapped.
25. semiconductor packages as claimed in claim 22, it is characterised in that the decoupling capacitance be coupled to the dynamic with
Machine access memory component, the dynamic RAM Controller and the external power source integrated with the logic element.
26. semiconductor packages as claimed in claim 22, it is characterised in that the dynamic random access memory and institute
State the different the multiple second conductive structures couplings that decoupling capacitance attaches face by being arranged on second projection respectively
To system single chip encapsulation.
27. semiconductor packages as claimed in claim 22, it is characterised in that the dynamic random access memory encapsulation is also wrapped
Extra dynamic random access memory is included, is stacked vertically on the dynamic random access memory, and is electrically connected
It is connected to second substrate.
28. semiconductor packages as claimed in claim 20, it is characterised in that the decoupling capacitance is coupled to the logic basis
Both part and the external power source.
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| US201361782764P | 2013-03-14 | 2013-03-14 | |
| US61/782,764 | 2013-03-14 | ||
| US14/188,881 | 2014-02-25 | ||
| US14/188,881 US9331054B2 (en) | 2013-03-14 | 2014-02-25 | Semiconductor package assembly with decoupling capacitor |
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| CN104051450B true CN104051450B (en) | 2017-08-01 |
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| CN105575967B (en) * | 2016-01-26 | 2024-01-12 | 格科微电子（上海）有限公司 | Three-dimensional integrated circuit chip and power supply noise filtering method thereof |
| CN112563249A (en) * | 2019-09-25 | 2021-03-26 | 江苏长电科技股份有限公司 | Integrated packaging structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101617399A (en) * | 2007-02-27 | 2009-12-30 | 富士通微电子株式会社 | Semiconductor storage unit and manufacture method thereof, potting resin formation method |
| CN102646668A (en) * | 2011-02-17 | 2012-08-22 | 三星电子株式会社 | Semiconductor package having tsv interposer and method of manufacturing same |
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| JP4827556B2 (en) * | 2005-03-18 | 2011-11-30 | キヤノン株式会社 | Stacked semiconductor package |
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| CN101617399A (en) * | 2007-02-27 | 2009-12-30 | 富士通微电子株式会社 | Semiconductor storage unit and manufacture method thereof, potting resin formation method |
| CN102646668A (en) * | 2011-02-17 | 2012-08-22 | 三星电子株式会社 | Semiconductor package having tsv interposer and method of manufacturing same |
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