CN104051450A - Semiconductor package assembly - Google Patents
Semiconductor package assembly Download PDFInfo
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- CN104051450A CN104051450A CN201410091379.1A CN201410091379A CN104051450A CN 104051450 A CN104051450 A CN 104051450A CN 201410091379 A CN201410091379 A CN 201410091379A CN 104051450 A CN104051450 A CN 104051450A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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- H01L2924/19101—Disposition of discrete passive components
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Abstract
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. The second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body, a dynamic random access memory device, a decoupling capacitor and a plurality of conductive structures. The second body has a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. The dynamic random access memory (DRAM) device is mounted on the second device-attach surface. The decoupling capacitor is mounted on the second device-attach surface. The conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package. In the semiconductor package assembly, the original package dimensions of the first semiconductor package and the second semiconductor package can be maintained, and an extra area for the decoupling capacitor is not needed.
Description
Technical field
The present invention, relevant for a kind of semiconductor packages, is particularly to a kind of laminate packaging formula (package on package, POP) semiconductor packages.
Background technology
Laminate packaging formula (package on package, POP) semiconductor packages is a kind of integrated antenna package of vertical junction assembly system single-chip (system-on-chip, SOC) encapsulation and memory package (memory package).Laminate packaging formula semiconductor packages can be stacking mutually by standard interface (standard interface) by two or more packaging bodies, to transmit signal between the two.Laminate packaging formula semiconductor packages can improve for example component density of the device of mobile phone, personal digital assistant and digital camera.
I/O (input/output due to the system single chip encapsulation that is positioned at bottom of laminate packaging formula semiconductor packages, I/O) accelerating of connecting can be subject in the memory package at top and the limitation in height between the system single chip encapsulation in bottom, so be difficult to design the performance performance that extra electronic component strengthens system single chip encapsulation in traditional laminate packaging formula semiconductor packages.
Therefore, in this technical field, need a kind of laminate packaging formula semiconductor packages of Improvement type.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of semiconductor packages of Improvement type.
One embodiment of the invention provides a kind of semiconductor packages.Described semiconductor packages comprises the first semiconductor packages and the second semiconductor packages.The first semiconductor packages comprises the first substrate, has the first projection attaching face that the first element attaches face and attaches face with respect to the first element.The first element that the second semiconductor packages is engaged to the first semiconductor packages attaches face, comprises the second substrate, dynamic random access memory, decoupling capacitance and a plurality of conductive structure.The second substrate has the second projection attaching face that the second element attaches face and attaches face with respect to the second element.Dynamic random access memory is fixed on the second element attaching face.Decoupling capacitance is fixed on the second element attaching face.A plurality of conductive structures are arranged on the second projection attaching face, and are connected to the first element attaching face.
Another embodiment of the present invention provides a kind of semiconductor packages.Described semiconductor packages comprises pedestal, dynamic random access memory encapsulation and external power source.Described dynamic random access memory encapsulation, is engaged to described pedestal, and wherein said dynamic random access memory encapsulation comprises: substrate; Dynamic random access memory, is fixed in described substrate; And decoupling capacitance, be fixed in substrate, and separate with described dynamic random access memory.Described external power source, is arranged on described pedestal, and separates with described dynamic random access memory encapsulation.
Further embodiment of this invention provides a kind of semiconductor packages.Described semiconductor packages comprises: pedestal; System single chip encapsulation, is engaged to described pedestal; Memory package, is engaged to described system single chip encapsulation, and wherein memory package comprises decoupling capacitance, is fixed in described memory package; And external power source, be arranged on described pedestal, and separate with described system single chip encapsulation.
Disclosed semiconductor packages, can provide extra decoupling capacitance, and can make the encapsulation of system single chip in semiconductor packages and memory package maintain original package dimension and do not need to offer the additional areas of decoupling capacitance.
For reading follow-up those skilled in the art by each accompanying drawing and the shown better embodiment of content, each object of the present invention is obvious.
Accompanying drawing explanation
Fig. 1 is the cutaway view of the semiconductor packages of one embodiment of the invention.
Fig. 2 is the vertical view of the semiconductor packages of one embodiment of the invention.
Embodiment
In claims and specification, used some vocabulary to censure specific assembly.One of skill in the art should understand, and hardware manufacturer may be called same assembly with different nouns.These claims and specification are not used as distinguishing the mode of assembly with the difference of title, but the difference in function is used as the criterion of distinguishing with assembly." comprising " mentioned in claims and specification is open term, therefore should be construed to " including but not limited to ".In addition, " coupling " word comprises directly any and is indirectly electrically connected means at this.Therefore, if describe first device in literary composition, be coupled to the second device, represent that described first device can directly be electrically connected on described the second device, or be indirectly electrically connected to described the second device by other devices or connection means.
For object of the present invention, feature and advantage can be become apparent, special embodiment below, and coordinate appended diagram, be described in detail.Specification of the present invention provides different embodiment that the technical characterictic of the different execution modes of the present invention is described.Wherein, each element in embodiment be configured to illustrate use, not in order to limit the present invention.And in embodiment, the part of reference numerals repeats, and is for the purpose of simplifying the description, not means the relevance between different embodiment.
Fig. 1 is the cutaway view of the semiconductor packages 500 of one embodiment of the invention.Fig. 2 is the vertical view of the semiconductor packages 500 of one embodiment of the invention.In the present embodiment, above-mentioned semiconductor packages 500 is laminate packaging formula (package on package, POP) semiconductor packages.In an embodiment of the present invention, above-mentioned laminate packaging formula semiconductor packages 500 comprises wafer scale (wafer-leveled) semiconductor packages of at least two vertical stackings.Above-mentioned laminate packaging formula semiconductor packages 500 comprises system single chip (system-on-chip, SOC) encapsulate and be stacked on the memory package (memory package) in SOC encapsulation, wherein SOC encapsulation is for example logic encapsulation (logic package), and memory package is for example dynamic random access memory (dynamic random access memory, DRAM) encapsulation.Because the design rule of memory package can be greater than the design rule of SOC encapsulation conventionally; so memory package can have enough spaces; make memory and decoupling capacitance (decoupling capacitor) thereon affixed; to strengthen power delivery network (the power delivery network of the DRAM element of memory package; PDN); or strengthen even central processing unit (the central processing unit of SOC encapsulation; CPU) and the power delivery network of painting processor (graphic processing unit, GPU).And, each semiconductor packages of above-mentioned semiconductor packages 500 can be chip package (flipchip package), above-mentioned chip package is used for example conductive structure of copper column-like projection block (copper pillar bumps), and semiconductor element is connected to pedestal (base).
Please refer to Fig. 1, semiconductor packages 500 comprises pedestal (base) 200, is fixed in the first semiconductor packages 206 on pedestal 200, and heap superimposition is fixed in the second semiconductor packages 232 in the first semiconductor packages 206.In an embodiment of the present invention, said base 200, for example, be printed circuit board (PCB) (print circuit board, PCB), can be formed by polypropylene (polypropylene, PP).Should be appreciated that said base 200 can be individual layer (single layer) structure or multilayer (multilayer) structure.The element that a plurality of wire (not shown) and weld pad (not shown) are arranged at pedestal 200 attaches on face (device attach surface) 202.In an embodiment of the present invention, above-mentioned wire can comprise signal line segment (signal trace segments) or ground connection line segment, the I/O (input/output, I/O) that above-mentioned signal line segment or ground connection line segment can be used for above-mentioned the first semiconductor packages 206 connects.And the element that weld pad is arranged at pedestal 200 attaches on face 202, is connected to the different ends of a plurality of wires.Above-mentioned weld pad is used for making the first semiconductor packages 206 affixed (mounted) thereon.
As shown in Figure 1, the element that above-mentioned the first semiconductor packages 206 is fixed in said base 200 by bonding process (bonding process) attaches on face 202.In the present embodiment, above-mentioned the first semiconductor packages 206 is system single chip (SOC) encapsulation, for example logic encapsulation (logic package).Above-mentioned the first semiconductor packages 206 comprises the first substrate (body) 208, and it has the first projection attaching face 212 that the first element attaches face 210 and attaches face 210 with respect to above-mentioned the first element.Above-mentioned the first substrate 208 can comprise circuit 216, metal pad 218 and metal pad 220.Above-mentioned metal pad 218 is arranged at the top close to the first element attaching face 210 of circuit 216, and above-mentioned metal pad 220 is arranged at the bottom close to the first projection attaching face 212 of circuit 216.The circuit 216 of above-mentioned the first semiconductor packages 206 interconnects to the circuit of said base 200 by a plurality of the first conductive structures 214, and the first conductive structure 214 is arranged on the first projection attaching face 212 of the first substrate 208.And, above-mentioned the first conductive structure 214 contact said base 200.In an embodiment of the present invention, above-mentioned the first conductive structure 214 can comprise being for example conductive lug structure, conduction column structure, conductor structure or the conductive adhesive structure (conductive paste structure) of copper bump structure or solder bump structure.Logic element 222 is used Flip Chip and by conductive structure 228, is fixed on the above-mentioned first element attaching face 210 of above-mentioned the first substrate 208.In an embodiment of the present invention, above-mentioned logic element 222 can comprise central processing unit (CPU), painting processor (GPU), dynamic RAM Controller (DRAM controller) or above-mentioned combination in any.In the present embodiment, above-mentioned logic element 222 comprises central processing unit (CPU) and/or painting processor (GPU) 224 and the dynamic RAM Controller (DRAM controller) 226 of integrating with above-mentioned CPU and/or GPU224.In an embodiment of the present invention, above-mentioned conductive structure 228 can comprise being for example conductive lug structure, conduction column structure, conductor structure or the conductive adhesive structure (conductive paste structure) of copper bump structure or solder tappet structure.In an embodiment of the present invention, can in the gap between above-mentioned logic element 222 and above-mentioned the first substrate 208, import primer filling material or primer (an underfill material or an underfill) 230.In an embodiment of the present invention, material filled by primer or primer 230 can comprise capillary filling glue (capillary underfill, CUF), moulding underfill (molded underfill, MUF), non-conductive insulating cement (nonconductive paste, NCP), non-conductive dielectric film (nonconductive film, NCF) or above-mentioned combination in any.
Refer again to Fig. 1.The second semiconductor packages 232, can be stacked on the above-mentioned first element attaching face 210 of above-mentioned the first semiconductor packages 206 by bonding process.In the present embodiment, above-mentioned the second semiconductor packages 232 can be memory package, for example, be dynamic random access memory (DRAM) encapsulation.Above-mentioned the second semiconductor packages 232 comprises the second substrate 234, has the second projection attaching face 238 that the second element attaches face 236 and attaches face 236 with respect to above-mentioned the second element.Be similar to above-mentioned the first substrate 208, above-mentioned the second substrate 234 can comprise circuit 250, metal pad 248 and metal pad 252.Above-mentioned metal pad 248 is arranged at the top close to the second element attaching face 236 of circuit 250, and above-mentioned metal pad 252 is arranged at the bottom close to the second projection attaching face 238 of circuit 250.The circuit 250 of above-mentioned the second semiconductor packages 232 interconnects to the circuit 216 of above-mentioned the first semiconductor packages 206 by a plurality of the second conductive structures 240, and the second conductive structure 240 is arranged on the second projection attaching face 238 of above-mentioned the second substrate 234.And the first element of the first substrate 208 of above-mentioned the first semiconductor packages 206 of above-mentioned the second conductive structure 240 contact attaches face 210.In an embodiment of the present invention, above-mentioned the second conductive structure 240 can comprise being for example conductive lug structure, conduction column structure, conductor structure or the conductive adhesive structure (conductive paste structure) of copper bump structure or solder bump structure.In an embodiment of the present invention, above-mentioned the second semiconductor packages 232 can comprise at least one dynamic random access memory (DRAM) element, and the second element that is solidly connected to above-mentioned the second substrate 234 attaches on face 236.As shown in Figure 1, in the present embodiment, have three DRAM elements, for example DRAM element 242, DRAM element 244 and DRAM element 246, be solidly connected on the second element attaching face 236 of above-mentioned the second substrate 234.And the second element that above-mentioned DRAM element 242 is solidly connected to above-mentioned the second substrate 234 by conducting resinl 243 attaches on face 236.Above-mentioned DRAM element 244 is stacked on above-mentioned DRAM element 242 by conducting resinl 245, and above-mentioned DRAM element 246 is stacked on above-mentioned DRAM element 244 by conducting resinl 247.Above-mentioned DRAM element 242, DRAM element 244 and DRAM element 246 can pass through bonding wire (bonding wires), and for example bonding wire 268, bonding wire 270 and bonding wire 272, be coupled to above-mentioned the second substrate 234.Yet the number of above-mentioned stacking DRAM element is only an embodiment, not in order to limit the present invention.In other embodiments of the invention, configuration that DRAM element 242 as shown in Figure 1, DRAM element 244 and DRAM element 246 can be parallel (side by side).Therefore, above-mentioned DRAM element 242, DRAM element 244 and DRAM element 246 can be solidly connected on the second element attaching face 236 of above-mentioned the second substrate 234 by conducting resinl.
Should note above-mentioned the second semiconductor packages 232, for example memory package 232, only for encapsulating at least one memory component.Therefore, the design rule of above-mentioned the second semiconductor packages 232 (such as weld pad minimum spacing (pad minimum pitch), weld pad size (pad size), circuit critical size (critical dimension of the circuitry) etc.) can be greater than for example design rule of the first semiconductor packages 206 of system single chip (SOC) encapsulation conventionally.The second substrate 234 of above-mentioned the second semiconductor packages 232 can have enough spaces is fixed in the second substrate 234 of above-mentioned the second semiconductor packages 232 extra decoupling capacitance (decoupling capacitor).And the second substrate 234 of above-mentioned the second semiconductor packages 232 can comprise illusory weld pad and dummy circuit, is arranged at the corner of the second substrate 234.Above-mentioned illusory weld pad and dummy circuit are used for discharging the pressure in the second substrate 234, and can avoid above-mentioned semiconductor package to be contained in the damage causing while dropping.Therefore, above-mentioned illusory weld pad and dummy circuit can be thereon affixed for above-mentioned extra decoupling capacitance, and above-mentioned extra decoupling capacitance can be electrically coupled to the first semiconductor packages 206 by above-mentioned illusory weld pad and dummy circuit.As shown in Figure 1, in the present embodiment, above-mentioned the second semiconductor packages 232 more comprises at least one decoupling capacitance (decoupling capacitor), and the second element that is fixed in above-mentioned the second substrate 234 attaches on face 236.In the present embodiment, decoupling capacitance 254 and decoupling capacitance 260 are fixed on the second element attaching face 236 of above-mentioned the second substrate 234.And above-mentioned DRAM element 242, DRAM element 244, DRAM element 246, decoupling capacitance 254 and decoupling capacitance 260 are separated element (discrete devices).In other words, decoupling capacitance 254 and decoupling capacitance 260 separate with DRAM element 242, DRAM element 244, DRAM element 246.As shown in Figure 1 and Figure 2, because above-mentioned decoupling capacitance can design, be fixed in above-mentioned the second semiconductor packages 232, and above-mentioned the second semiconductor packages 232 is for example for DRAM encapsulates and its design rule is greater than for example design rule of above-mentioned first semiconductor packages 206 of logic encapsulation.The additional areas that does not need to offer decoupling capacitance so above-mentioned the first semiconductor packages 206 and above-mentioned the second semiconductor packages 232 can maintain original package dimension.As shown in Figure 1 and Figure 2, in an embodiment of the present invention, in vertical view, for example the border 280 of the first substrate 208 of above-mentioned first semiconductor packages 206 of logic encapsulation (below of the second semiconductor packages 232) can be completely overlapping with a border 282 of above-mentioned second substrate 234 of above-mentioned the second semiconductor packages 232.In other words, in vertical view, for example the border 282 for above-mentioned second substrate 234 of above-mentioned second semiconductor packages 232 of DRAM encapsulation can be aligned in for example border 280 of the first substrate 208 of above-mentioned first semiconductor packages 206 of logic encapsulation (below of the second semiconductor packages 232).
As shown in Figure 1, in an embodiment of the present invention, above-mentioned the second semiconductor packages 232 more comprises moulding material (molding material) 266, the second element that covers above-mentioned the second substrate 234 attaches face 236, and comprises DRAM element 242, DRAM element 244, DRAM element 246, bonding wire 268, bonding wire 270, bonding wire 272, decoupling capacitance 254 and decoupling capacitance 260.
Refer again to Fig. 1.The element that at least one external power source (external power supply) is arranged at said base 200 attaches on face 202.In the present embodiment, the element that has two external power sources (for example external power source 204, external power source 205) to be arranged at said base 200 attaches on face 202.In an embodiment of the present invention, said external power supply 204, external power source 205 both all separate with above-mentioned the first semiconductor packages 206 and the second semiconductor packages 232.In the present embodiment, said external power supply 204, external power source 205 be for to the above-mentioned CPU of above-mentioned the first semiconductor packages 206 and/or GPU224 and dynamic random access memory (DRAM) controller 226, and the DRAM element 242 of above-mentioned the second semiconductor packages 232, DRAM element 244, DRAM element 246 provide power supply.
In an embodiment of the present invention, above-mentioned decoupling capacitance 254 and decoupling capacitance 260 can be coupled to above-mentioned CPU and/or GPU224 and/or dynamic random access memory (DRAM) controller 226, with afford redress electric current and/or bucking voltage (compensation current and/or voltage).And, above-mentioned decoupling capacitance 254 and decoupling capacitance 260 switch output noise (simultaneous switching output (SSO) noise) when can alleviate from power supply, and above-mentioned power supply provides electric current and/or voltage to above-mentioned semiconductor packages 500.Therefore, above-mentioned decoupling capacitance 254 and decoupling capacitance 260 are for strengthening power delivery network (the power delivery network of the DRAM element of memory package (above-mentioned the second semiconductor packages 232), PDN), or even add central processing unit (the central processing unit that is better than SOC encapsulation (above-mentioned the first semiconductor packages 206), CPU) and the power delivery network of painting processor (graphic processing unit, GPU).As shown in Figure 1, in an embodiment of the present invention, above-mentioned decoupling capacitance 260 designs are coupled to CPU and/or GPU224 and the said external power supply 204 of above-mentioned logic element 222.In the present embodiment, above-mentioned decoupling capacitance 260 by current path 262 (being denoted as dotted line) to the CPU of the logic element 222 of above-mentioned the first semiconductor packages 206 and/or GPU224 afford redress electric current and/or bucking voltage.In other embodiments of the invention, dynamic RAM Controller 226 and said external power supply 205 that 254 designs of above-mentioned decoupling capacitance are coupled to above-mentioned DRAM element 242, DRAM element 244, DRAM element 246, integrate with above-mentioned logic element 222.Above-mentioned decoupling capacitance 254 by current path 264 (being denoted as dotted line) to above-mentioned DRAM element 242, DRAM element 244, the DRAM element 246 of above-mentioned the second semiconductor packages 232 afford redress electric current and/or bucking voltage.And above-mentioned DRAM element 242, DRAM element 244, DRAM element 246 and above-mentioned decoupling capacitance 254, decoupling capacitance 260 are coupled to above-mentioned the first semiconductor packages 206 by being arranged on the different conductive structure 252 of above-mentioned the second projection attaching face 238 respectively.
The embodiment of the present invention provides a kind of semiconductor packages, for example, be laminate packaging formula (POP) semiconductor packages.Above-mentioned semiconductor packages comprises being for example the memory package (memory package) of dynamic random access memory (DRAM) encapsulation, is stacked in for example system single chip (SOC) encapsulation for logic encapsulation (logic package).Because the design rule of above-mentioned memory package (such as weld pad minimum spacing (pad minimum pitch), weld pad size (pad size), circuit critical size (critical dimension of the circuitry) etc.) can be greater than for example design rule of said system single-chip (SOC) encapsulation conventionally; so above-mentioned semiconductor packages is design, comprise extra decoupling capacitance, be fixed in above-mentioned memory package.And, above-mentioned extra decoupling capacitance can be fixed on the illusory weld pad and dummy circuit of above-mentioned memory package, above-mentioned illusory weld pad and dummy circuit are used for discharging the suprabasil pressure of above-mentioned memory package, and can avoid above-mentioned semiconductor package to be contained in the damage causing while dropping.In an embodiment of the present invention, the above-mentioned decoupling capacitance design that is fixed in above-mentioned memory package is coupled to the above-mentioned logic element said external power supply 204 of said system single-chip (SOC) encapsulation, with above-mentioned logic element is afforded redress electric current and/or bucking voltage.And above-mentioned decoupling capacitance can design and be coupled to the above-mentioned DRAM element of above-mentioned memory package, above-mentioned dram controller and said external power supply, with above-mentioned DRAM element is afforded redress electric current and/or bucking voltage.Therefore, said system single-chip (SOC) encapsulation and above-mentioned memory package can maintain original package dimension and not need to offer the additional areas of decoupling capacitance.
The foregoing is only better embodiment of the present invention, all equalizations of doing according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (28)
1. a semiconductor packages, is characterized in that, comprising: the first semiconductor packages and the second semiconductor packages, and described the first semiconductor packages comprises:
The first substrate, has the first projection attaching face that the first element attaches face and attaches face with respect to described the first element; And
Described the second semiconductor packages, described the first element that is engaged to described the first semiconductor packages attaches face, and wherein said the second semiconductor packages comprises:
The second substrate, has the second projection attaching face that the second element attaches face and attaches face with respect to described the second element;
Dynamic random access memory, is fixed on described the second element attaching face;
Decoupling capacitance, is fixed on described the second element attaching face; And
A plurality of conductive structures, are arranged on described the second projection attaching face, and are connected to the described first element attaching face of described first substrate of described the first semiconductor packages.
2. semiconductor packages as claimed in claim 1, is characterized in that, in vertical view, the border of the border of described the first substrate and described the second substrate is completely overlapping.
3. semiconductor packages as claimed in claim 1, is characterized in that, described the first semiconductor packages also comprises logic element, and described the first element that is fixed in described the first substrate attaches face.
4. semiconductor packages as claimed in claim 3, is characterized in that, also comprises:
Pedestal, wherein said the first semiconductor packages and described the second semiconductor packages are fixed on described pedestal by the first conductive structure of described the first semiconductor packages; And
External power source, is arranged on described pedestal, and separates with described the first semiconductor packages and described the second semiconductor packages.
5. semiconductor packages as claimed in claim 4, is characterized in that, described decoupling capacitance is coupled to described logic element and described external power source.
6. semiconductor packages as claimed in claim 4, is characterized in that, dynamic RAM Controller and described external power source that described decoupling capacitance is coupled to described dynamic random access memory, integrates with described logic element.
7. semiconductor packages as claimed in claim 1, is characterized in that, described dynamic random access memory and described decoupling capacitance are spaced.
8. semiconductor packages as claimed in claim 1, it is characterized in that, described dynamic random access memory and described decoupling capacitance are coupled to described the first semiconductor packages by being arranged on different described a plurality of conductive structures of described the second projection attaching face respectively.
9. semiconductor packages as claimed in claim 1, is characterized in that, described the second semiconductor packages also comprises extra dynamic random access memory, is stacked vertically on described dynamic random access memory, and is electrically connected to described the second substrate.
10. a semiconductor packages, is characterized in that, comprising:
Pedestal;
Dynamic random access memory encapsulation, is engaged to described pedestal; And
External power source, is arranged on described pedestal, and separates with described dynamic random access memory encapsulation;
Wherein said dynamic random access memory encapsulation comprises:
Substrate;
Dynamic random access memory, is fixed in described substrate; And
Decoupling capacitance, is fixed in substrate, and separates with described dynamic random access memory.
11. semiconductor packages as claimed in claim 10, is characterized in that, also comprise:
Logic encapsulation, between described dynamic random access memory encapsulation and described pedestal, wherein said logic encapsulation comprises:
The first substrate, has the first projection attaching face that the first element attaches face and attaches face with respect to described the first element;
Logic element, described the first element that is fixed in described the first substrate attaches face; And
A plurality of the first conductive structures, are arranged on described the first projection attaching face, and contact described pedestal.
12. semiconductor packages as claimed in claim 11, it is characterized in that, described dynamic random access memory encapsulation attaches face a plurality of the second conductive structures by being arranged at the second projection of the described substrate of described dynamic random access memory encapsulation are engaged to described the first element attaching face, and contact described the first element attaching face.
13. semiconductor packages as claimed in claim 12, it is characterized in that, the described substrate of described dynamic random access memory encapsulation has the second element attaching face that attaches face with respect to described the second projection, and wherein said dynamic random access memory is fixed on described the second element attaching face.
14. semiconductor packages as claimed in claim 12, it is characterized in that, described dynamic random access memory and described decoupling capacitance are coupled to described logic and encapsulate by being arranged on different described a plurality of the second conductive structures that described the second projection attaches face respectively.
15. semiconductor packages as claimed in claim 11, is characterized in that, in vertical view, the border of described first substrate of the border of the described substrate of described dynamic random access memory encapsulation and the encapsulation of described logic is completely overlapping.
16. semiconductor packages as claimed in claim 11, is characterized in that, described decoupling capacitance is coupled to described logic element and described external power source.
17. semiconductor packages as claimed in claim 11, is characterized in that, dynamic RAM Controller and described external power source that described decoupling capacitance is coupled to described dynamic random access memory, integrates with described logic element.
18. semiconductor packages as claimed in claim 10, it is characterized in that, described dynamic random access memory encapsulation also comprises extra dynamic random access memory, be stacked vertically on described dynamic random access memory, and be electrically connected to the described substrate of described dynamic random access memory encapsulation.
19. 1 kinds of semiconductor packages, is characterized in that, comprising:
Pedestal;
System single chip encapsulation, is engaged to described pedestal;
Memory package, is engaged to described system single chip encapsulation, and wherein memory package comprises decoupling capacitance, is fixed in described memory package; And
External power source, is arranged on described pedestal, and separates with described system single chip encapsulation.
20. semiconductor packages as claimed in claim 19, is characterized in that, described system single chip encapsulation comprises:
The first substrate, has the first projection attaching face that the first element attaches face and attaches face with respect to described the first element;
Logic element, is fixed in described the first element and attaches face; And
A plurality of the first conductive structures, are arranged on described the first projection attaching face, and contact described pedestal.
21. semiconductor packages as claimed in claim 20, is characterized in that, described memory package is dynamic random access memory encapsulation.
22. semiconductor packages as claimed in claim 21, is characterized in that, described dynamic random access memory encapsulation comprises:
The second substrate, has the second projection attaching face that the second element attaches face and attaches face with respect to described the second element;
Dynamic random access memory and described decoupling capacitance, be fixed on described the second element attaching face; And
A plurality of the second conductive structures, are arranged on described the second projection and attach face, and described the first element that is connected to described first substrate of described system single chip encapsulation attaches face.
23. semiconductor packages as claimed in claim 22, is characterized in that, described dynamic random access memory is separated element with described decoupling capacitance.
24. semiconductor packages as claimed in claim 22, is characterized in that, in vertical view, the border of described first substrate of the border of described second substrate of described dynamic random access memory encapsulation and the encapsulation of described system single chip is completely overlapping.
25. semiconductor packages as claimed in claim 22, is characterized in that, dynamic RAM Controller and described external power source that described decoupling capacitance is coupled to described dynamic random access memory, integrates with described logic element.
26. semiconductor packages as claimed in claim 22, it is characterized in that, described dynamic random access memory and described decoupling capacitance are coupled to described system single chip and encapsulate by being arranged on different described a plurality of the second conductive structures that described the second projection attaches face respectively.
27. semiconductor packages as claimed in claim 22, it is characterized in that, described dynamic random access memory encapsulation also comprises extra dynamic random access memory, is stacked vertically on described dynamic random access memory, and is electrically connected to described the second substrate.
28. semiconductor packages as claimed in claim 20, is characterized in that, described decoupling capacitance is coupled to described logic element and described external power source.
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| US201361782764P | 2013-03-14 | 2013-03-14 | |
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| US14/188,881 | 2014-02-25 | ||
| US14/188,881 US9331054B2 (en) | 2013-03-14 | 2014-02-25 | Semiconductor package assembly with decoupling capacitor |
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