KR20150011893A - Integrated circuit package and method for manufacturing the same - Google Patents

Integrated circuit package and method for manufacturing the same Download PDF

Info

Publication number
KR20150011893A
KR20150011893A KR1020130087055A KR20130087055A KR20150011893A KR 20150011893 A KR20150011893 A KR 20150011893A KR 1020130087055 A KR1020130087055 A KR 1020130087055A KR 20130087055 A KR20130087055 A KR 20130087055A KR 20150011893 A KR20150011893 A KR 20150011893A
Authority
KR
South Korea
Prior art keywords
substrate
semiconductor chip
interposer
semiconductor package
semiconductor
Prior art date
Application number
KR1020130087055A
Other languages
Korean (ko)
Other versions
KR101550496B1 (en
Inventor
최정선
Original Assignee
에스티에스반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스티에스반도체통신 주식회사 filed Critical 에스티에스반도체통신 주식회사
Priority to KR1020130087055A priority Critical patent/KR101550496B1/en
Publication of KR20150011893A publication Critical patent/KR20150011893A/en
Application granted granted Critical
Publication of KR101550496B1 publication Critical patent/KR101550496B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Wire Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

The present invention relates to an integrated semiconductor package. The present invention relates to an integrated semiconductor package capable of improving signal response speed by applying silicon interposer and improving warpage, improving SMT yield rate, and having a package-on-package structure for enabling easy rewiring; and a method for manufacturing the same. An integrated semiconductor package according to the present invention includes: a first semiconductor package which includes a first substrate including a circuit pattern, a first semiconductor chip which is mounted to be electrically connected to the circuit pattern on the first substrate, and a first molding part sealing at least the first semiconductor chip; an interposer which is mounted on the first substrate to be electrically connected to the circuit pattern of the first substrate by a first solder bump and has a hollow part to receive the first semiconductor chip; and a second semiconductor package which is a second semiconductor package stacked on the first semiconductor package and the interposer, includes a second substrate which has a circuit pattern, a second semiconductor chip which is mounted to be electrically connected to the circuit pattern on the second substrate, and a second molding part which is formed to seal at least the second semiconductor chip. The semiconductor package is electrically connected to the interposer by a second solder pump.

Description

TECHNICAL FIELD [0001] The present invention relates to a stacked semiconductor package,

The present invention relates to a stacked semiconductor package, and more particularly, to a stacked semiconductor package having a package-on-package structure which improves signal response speed and warpage by applying a silicon interposer and improves SMT stacking yield and facilitates re- Package and a manufacturing method thereof.

BACKGROUND ART [0002] In general, the semiconductor industry is required to be lighter, more compact, more versatile, and have higher performance at an inexpensive price. One of the important technologies required to meet such demands is integrated circuit packaging technology.

Integrated circuit packaging protects semiconductor chips such as single elements and integrated circuits formed by stacking various electronic circuits and wiring lines from various external environments such as dust, moisture, electrical and mechanical loads and optimizes and maximizes the electrical performance of semiconductor chips Output terminal to the main board by using a lead frame, a printed circuit board (Printed Circuit Board), or the like, and molded by using an encapsulating material.

In recent years, as the products on which the integrated circuit packages are mounted are thin and short, and many functions are required, the integrated circuit package technology includes a SIP (System in Package), a POP Package) and the like.

As the capacity of the integrated circuit package increases, the number of input / output terminals increases. In order to increase the number of input / output terminals without increasing the overall size of the integrated circuit package, a through hole is formed in the mold part and filled with conductive paste A method of forming a through mold via (TMV) has been proposed.

1A to 1E are cross-sectional views illustrating a manufacturing process of a TMV type stacked semiconductor package according to the related art, and a method of manufacturing a conventional TMV type stacked semiconductor package will be described with reference to these drawings.

First, as shown in FIG. 1A, a substrate 10 having a via contact 13 for electrically connecting the wiring terminal 11, the external terminal 12, and the wiring terminal 11 to the external terminal 12 is formed. Prepare.

Next, a first semiconductor chip 20 and a solder ball 30 are attached to the substrate 10 in Fig. 1B. At this time, the first semiconductor chip 20 is electrically connected to the wiring terminal 11 of the substrate 10 through the conductive bumps 22 in a face-down manner such that the circuit pattern 21 faces downward, And a solder ball 30 is formed at the edge of the substrate 10. [

1C, a gap between the semiconductor chip 20 and the substrate 10 is filled with an underfill 41 and then the entire upper surface of the semiconductor chip 20 and the substrate 10 is molded with an encapsulating material, .

1D, a via hole 50 is formed by etching the molding part 40 using a process such as laser machining so that a part of the solder ball 30 on the upper surface of the substrate 10 is exposed.

Next, as shown in FIG. 1E, a second semiconductor package 60 is laminated on the first semiconductor package formed by the process up to FIG. 1D, and a solder ball is formed on the bottom surface of the substrate 10. Next,

However, in the case of the above-described conventional TMV type stacked semiconductor package, it is applied to improve the yield of the SMT stacking. However, in the semiconductor package stack, the top ball pad of the bottom package and the ball of the top package The difficulty of applying fine pitch (<0.2mm) of pad is that it is difficult to miniaturize high I / 0 interconnect and package size.

In addition, it takes a long time to process the laser for forming the via hole, and the number of input / output terminals is limited so that the rewiring of the second semiconductor package can not be practically practiced.

SUMMARY OF THE INVENTION It is therefore a general object of the present invention to provide a stacked semiconductor package capable of substantially solving various problems caused by limitations and disadvantages of the prior art, And a manufacturing method thereof.

It is a further specific object of the present invention to provide a stacked semiconductor package and a method of manufacturing the same which can improve signal response speed and warpage by applying a silicon interposer.

It is yet another specific object of the present invention to provide a stacked semiconductor package having improved SMT stacking yield and easy rewiring, and a method of manufacturing the same.

To this end, a stacked semiconductor package according to an embodiment of the present invention includes a first substrate having a circuit pattern, a first semiconductor chip mounted on the first substrate to be electrically connected to the circuit pattern, A first semiconductor package including a first molding part sealing the semiconductor chip; An interposer mounted on the first substrate to be electrically connected to a circuit pattern of the first substrate by a first solder bump, the interposer having a hollow portion to receive the first semiconductor chip; And a second semiconductor package laminated on the first semiconductor package and the interposer, wherein the second semiconductor package includes a second substrate having a circuit pattern, and a second semiconductor chip mounted on the second substrate so as to be electrically connected to the circuit pattern. And a second semiconductor package including a second molding part formed to seal at least the second semiconductor chip, the second semiconductor package being electrically connected to the interposer by a second solder bump.

In a stacked semiconductor package of an embodiment of the present invention, the interposer includes a silicon substrate; A circuit pattern formed on upper and lower surfaces of the silicon substrate; And a via contact of a through silicon via (TSV) structure for electrically connecting the upper and lower circuit patterns.

In the stacked semiconductor package of the embodiment of the present invention, the upper surface of each of the silicon substrate of the interposer and the first molding portion may be located on the same plane.

In the stacked semiconductor package of the embodiment of the present invention, the first semiconductor chip may be mounted on the first substrate with a flip chip bonding structure by a solder ball.

In the stacked semiconductor package of the embodiment of the present invention, the solder ball of the first semiconductor chip may be molded underfill.

In the stacked semiconductor package of the embodiment of the present invention, the second semiconductor chip can be mounted on the second substrate in a wire bonding structure.

In the stacked semiconductor package of the embodiment of the present invention, the interposer may have a lead frame or an interconnectionable layer structure.

According to another aspect of the present invention, there is provided a method of manufacturing a stacked semiconductor package including: mounting a first semiconductor chip on a first substrate having a circuit pattern; A step S2 of mounting an interposer having a hollow portion on the first substrate to receive the first semiconductor chip; A step S3 of sealing the first semiconductor chip between the first substrate and the interposer and between the first semiconductor chip and the interposer with an encapsulating material; A second semiconductor package including a second substrate and a second semiconductor chip mounted on the second substrate is stacked on the first semiconductor chip so that the second semiconductor chip is electrically connected through the interposer (S4). &Lt; / RTI &gt;

In the method of manufacturing a stacked semiconductor package according to an embodiment of the present invention, the interposer includes a silicon substrate; A circuit pattern formed on upper and lower surfaces of the silicon substrate; And a via contact of a through silicon via (TSV) structure for electrically connecting the upper and lower circuit patterns, wherein the via contact can be connected to the second semiconductor chip.

In the method of manufacturing a stacked semiconductor package according to an embodiment of the present invention, the first semiconductor chip of the step S1 may be mounted on the first substrate with a flip chip bonding structure by a solder ball.

In the method of manufacturing a stacked semiconductor package according to an embodiment of the present invention, the solder ball of the first semiconductor chip in step S1 may be molded underfill.

In the method of manufacturing a stacked semiconductor package according to an embodiment of the present invention, the step S3 may be configured such that the silicon substrate of the interposer and the first molding part are located on the same plane.

In the method of manufacturing a stacked semiconductor package according to an embodiment of the present invention, the interposer may have a lead frame or an interconnectionable layer structure.

In the method of manufacturing a stacked semiconductor package according to an embodiment of the present invention, the second semiconductor chip in step S4 may be mounted on the second substrate in a wire bonding structure.

According to the stacked semiconductor package and the method for fabricating the same according to the present invention, it is possible to improve the signal response speed and warpage by applying the silicon interposer.

Further, according to the laminated semiconductor package and the manufacturing method thereof, there is an effect that the yield of the SMT lamination is improved and the rewiring is facilitated.

1A to 1E are cross-sectional views illustrating a manufacturing process of a TMV type stacked semiconductor package according to the related art.
2 is a cross-sectional view showing one embodiment of a stacked semiconductor package according to the present invention.
3 is a plan view showing a configuration of an interposer according to the present invention.
4A to 4D are cross-sectional views illustrating a process for fabricating a stacked semiconductor package according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the terms described below are defined in consideration of the functions of the present invention, and these may vary depending on the intention or precedent of the user. Therefore, the definition should be based on the contents throughout this specification.

FIG. 2 is a cross-sectional view showing one embodiment of a stacked semiconductor package according to the present invention, and FIG. 3 is a plan view showing a configuration of an interposer according to the present invention.

Referring to FIG. 2, the stacked semiconductor package according to the present invention may include a first semiconductor package, an interposer, and a second semiconductor package. The first to third solder bumps 400, 500 and 600 formed on the bottom surface of the second semiconductor package and between the interposer 300 and the first semiconductor package 100 or the second semiconductor package 200 .

The first semiconductor package includes a first substrate 110 having a circuit pattern, a first semiconductor chip 120 mounted on the first substrate 110 so as to be electrically connected to the circuit pattern, And a first molding part 130 that seals the semiconductor chip 120.

The first semiconductor package 100 includes a first substrate 110, a first semiconductor chip 120, and a first molding part 130.

The first substrate 110 includes a wiring terminal 111 formed on an upper surface thereof and an external terminal 112 formed on a lower surface of the first substrate 110 to be connected to the outside through a second solder bump 500, And a via contact 115 formed to penetrate the first substrate 110 to connect the terminal 111 and the external terminal 112. In addition, a solder ball pad (not shown) may be provided on the upper surface.

The first semiconductor chip 120 is flip-chip bonded to the wiring terminal 117 formed on the upper surface of the first substrate 110 through the solder ball 121. Here, the first semiconductor chip 120 is flip-chip bonded on the first substrate 110 in face-down form, and is bonded to the first semiconductor chip 120 through the solder ball 121 formed on the first semiconductor chip 120, And is electrically connected to the wiring terminal 111 of the substrate 110. The solder ball may be molded through an underfill, and the underfill may be made of any one selected from, for example, an epoxy resin, a silicone resin, and the like.

The first molding part 130 is formed to seal the first semiconductor chip and the interposer, and the upper surface of the interposer is exposed.

The second semiconductor package 200 includes a second substrate 210, second semiconductor chips 220 and 225, and a second molding part 230.

The second substrate 210 includes a wiring terminal 211 formed on an upper surface (one surface), an external terminal 212 formed on a lower surface (another surface) and connected to the outside through the interposer 300, And a via contact 213 formed to penetrate the second substrate 210 to connect the external terminal 212 and the external terminal 212 to each other.

The second semiconductor chips 220 and 225 may be electrically connected to bonding pads (not shown) formed on respective upper surfaces of the second semiconductor chips 220 and 225 through wires 240 and 241, respectively. However, the second semiconductor chip may be connected to a wiring terminal formed on the upper surface of the second substrate 210 through a solder ball (not shown) by flip-chip bonding.

The second molding part 230 is molded on the entire upper surfaces of the second semiconductor chips 220 and 225 and the second substrate 210 and may be formed of any one selected from epoxy resin, silicone resin and the like, for example.

The interposer 300 has a hollow portion 350 for receiving a semiconductor chip as shown in FIG. The hollow 350 may be formed to have a larger size than the first semiconductor chip 120 to accommodate the first semiconductor chip 120 and may be formed between the first semiconductor chip 120 and the hollow 350 And the hollow portion 350 is formed at the central portion of the interposer 300. [0054]

The interposer 300 may have the same layer structure as the first substrate 110 or the second substrate 210. That is, the via contact 313 having a through silicon via (TSV) structure that interconnects the wiring terminals 311 and 312 formed on the upper and lower surfaces of the silicon substrate 310 of the interposer and the wiring terminals 311 and 312 on the upper and lower surfaces, . In addition, the interposer 300 may be made of a material having a thermal expansion coefficient similar to that of the first substrate 110 or the second substrate 210, specifically silicon. This is because the substrate, the semiconductor chip, It is possible to reduce the warpage due to the difference in the coefficient of thermal expansion between the layers.

In addition, the laminated semiconductor package of the present invention can be manufactured by implementing a bottom PKG (first semiconductor package) having a top ball pad (wiring terminal) of 0.2 mm pitch or less by applying a silicon interposer employing a TSV (Through Silicon Via) structure It has a high response speed and can be miniaturized.

The first solder bump 400 is attached to the wiring terminal 312 formed on the lower surface of the interposer 300 and is for electrical connection with the substrate of the first semiconductor package, that is, with the first substrate.

The second solder bump 500 is attached to an external terminal 212 formed on the substrate of the second semiconductor package 210 or the second substrate 210 and electrically connected to the first semiconductor package 100 and the second semiconductor package 200 ) Can be stacked through the second solder bump (500).

The third solder bump 600 is attached to the external terminal 112 formed on the bottom surface of the first substrate 110 and the PoP integrated circuit package in which the second semiconductor package is stacked on the first semiconductor package is connected to an external device ) Or for electrically connecting with the substrate.

The size, shape, arrangement, etc. of the first to third solder bumps 400, 500, and 600 are not particularly limited and can be appropriately designed as needed.

As described above, in the present embodiment, the interposer is interposed between the first semiconductor package and the second semiconductor package, whereby the second semiconductor package can be re-routed and the number of input / output terminals can be increased.

4A to 4D are cross-sectional views illustrating a process of fabricating a stacked semiconductor package according to an embodiment of the present invention. Referring to these drawings, a method of fabricating a stacked semiconductor package according to an embodiment of the present invention will be described.

First, as shown in FIG. 4A, a via terminal 113 is provided on an upper surface, a via contact 113 having an external terminal 112 on a lower surface and connecting the wiring terminal 111 and the external terminal 112, The first substrate 110 is prepared.

The semiconductor chip 120 is flip-chip bonded on the wiring terminal 101 of the first substrate 110 by using the solder ball 121. The first semiconductor chip 120 and the first substrate 110 And the solder ball 121 connected thereto is sealed with the underfill 125.

Next, as shown in FIG. 4B, the interposer 300 is attached on the first substrate 110. Next, as shown in FIG. At this time, the interposer 300 is arranged to receive the first semiconductor chip 120 in the hollow portion of the interposer 300, and then the interposer 300 is connected to the wiring terminals (not shown) of the first substrate 110 using the first solder bumps 400 111).

4C, the first semiconductor chip 120 and the interposer 300 and the first semiconductor substrate 110 and the interposer 300 are sealed with an encapsulating material to form a first molding part 130 are formed.

A third solder bump 600 is formed on the external terminal 112 formed on the bottom surface of the first substrate 110.

Next, as shown in FIG. 4D, the second semiconductor package 200 is stacked on the first semiconductor package 100 using the second solder bumps 500. The second semiconductor package 200 includes a second substrate 210 having a wiring terminal 211, an external terminal 212 and a via contact 213 and a second substrate 210 via wires 240 and 241. [ And a second molding part 230 formed on the entire upper surface of the second semiconductor chip 220 and the second substrate 210. The first semiconductor chip 220 and the second semiconductor chip 220 are electrically connected to the wiring terminal 211 of the second semiconductor chip 220, The wiring terminal 311 of the interposer 300 and the external terminal 213 of the second substrate 210 are electrically connected to each other through the second solder bump 500.

In the above-described embodiments, the first semiconductor chip is mounted on the first substrate and then the interposer is attached. However, after the interposer is first stacked on the first substrate, the first semiconductor chip is placed in the opening of the interposer 1 semiconductor chips may be stacked. In addition, since the flip chip bonding structure of the first semiconductor chip and the wire bonding structure of the second semiconductor chip are merely one embodiment, it is needless to say that they can be changed to other bonding structures.

As described above, according to the present embodiment, the interposer is interposed so that the semiconductor chip is positioned in the hollow portion of the interposer before molding the semiconductor chip of the first semiconductor package, and then the molding process is performed. Mounting of the second semiconductor package on the second semiconductor package does not proceed with processes such as laser processing and underfilling which take a long time, so that the process can be shortened and manufacturing cost can be reduced accordingly.

Further, according to the stacked semiconductor package and the manufacturing method thereof according to the present invention, by applying the silicon interposer, it is possible to improve the signal response characteristics and reduce the high temperature warpage.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. Accordingly, the scope of the present invention should be construed as being limited to the embodiments described, and it is intended that the scope of the present invention encompasses not only the following claims, but also equivalents thereto.

100, 200: semiconductor package 110, 210: substrate
120, 220, 225: semiconductor chip 130, 230: molding part
300: interposer 350: hollow
400, 500, 600: solder bump

Claims (14)

A semiconductor device comprising: a first substrate having a circuit pattern; a first semiconductor chip mounted on the first substrate so as to be electrically connected to the circuit pattern; and a first molding section sealing at least the first semiconductor chip A package;
An interposer mounted on the first substrate to be electrically connected to a circuit pattern of the first substrate by a first solder bump, the interposer having a hollow portion to receive the first semiconductor chip; And
A second semiconductor chip mounted on the second substrate so as to be electrically connected to the circuit pattern; and a second semiconductor chip mounted on the first substrate and electrically connected to the circuit pattern, And a second semiconductor package including a second molding part formed to seal at least the second semiconductor chip, the second semiconductor package being electrically connected to the interposer by a second solder bump.
The method according to claim 1,
The interposer comprising: a silicon substrate; A circuit pattern formed on upper and lower surfaces of the silicon substrate; And a via contact of a through silicon via (TSV) structure for electrically connecting the upper and lower circuit patterns to each other.
The method according to claim 1,
Wherein the upper surface of each of the silicon substrate of the interposer and the first molding portion is located on the same plane.
The method according to claim 1,
Wherein the first semiconductor chip is mounted on the first substrate with a flip chip bonding structure by a solder ball.
5. The method of claim 4,
Wherein the solder balls of the first semiconductor chip are molded underfill.
The method according to claim 1,
Wherein the second semiconductor chip is mounted on the second substrate in a wire bonding structure.
The method according to claim 1,
Wherein the interposer has a lead frame or an interconnection layer structure.
A step S1 of mounting a first semiconductor chip on a first substrate having a circuit pattern;
A step S2 of mounting an interposer having a hollow portion on the first substrate to receive the first semiconductor chip;
A step S3 of sealing the first semiconductor chip between the first substrate and the interposer and between the first semiconductor chip and the interposer with an encapsulating material;
A second semiconductor package including a second substrate and a second semiconductor chip mounted on the second substrate is stacked on the first semiconductor chip so that the second semiconductor chip is electrically connected through the interposer Step S4;
Wherein the semiconductor package is formed of a semiconductor material.
9. The method of claim 8,
The interposer comprising: a silicon substrate; A circuit pattern formed on upper and lower surfaces of the silicon substrate; And a via contact of a through silicon via (TSV) structure for electrically connecting the top and bottom circuit patterns,
And the via contact is connected to the second semiconductor chip.
9. The method of claim 8,
Wherein the first semiconductor chip in step S1 is mounted on the first substrate in a flip chip bonding structure by a solder ball.
11. The method of claim 10,
Wherein the solder balls of the first semiconductor chip in step S1 are molded underfill.
9. The method of claim 8,
Wherein the silicon substrate of the interposer and the first molding part are located on the same plane. 9. The method of claim 8,
Wherein the interposer has a lead frame or a layer structure capable of interconnection.
9. The method of claim 8,
And the second semiconductor chip in step S4 is mounted on the second substrate in a wire bonding structure.
KR1020130087055A 2013-07-24 2013-07-24 Integrated circuit package and method for manufacturing the same KR101550496B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020130087055A KR101550496B1 (en) 2013-07-24 2013-07-24 Integrated circuit package and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020130087055A KR101550496B1 (en) 2013-07-24 2013-07-24 Integrated circuit package and method for manufacturing the same

Publications (2)

Publication Number Publication Date
KR20150011893A true KR20150011893A (en) 2015-02-03
KR101550496B1 KR101550496B1 (en) 2015-09-04

Family

ID=52488124

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020130087055A KR101550496B1 (en) 2013-07-24 2013-07-24 Integrated circuit package and method for manufacturing the same

Country Status (1)

Country Link
KR (1) KR101550496B1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109727876A (en) * 2017-10-31 2019-05-07 台湾积体电路制造股份有限公司 Chip package and forming method thereof
KR20190062179A (en) * 2017-11-27 2019-06-05 파워테크 테크놀로지 인코포레이티드 Package structure and manufacturing method thereof
KR20190139490A (en) * 2018-06-08 2019-12-18 삼성전자주식회사 Semiconductor package, Package on Package device and method of fabricating the same
KR20200036771A (en) * 2018-09-27 2020-04-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Integrated circuit package and method
CN112951801A (en) * 2019-12-10 2021-06-11 爱思开海力士有限公司 Package-on-package comprising vertically stacked sub-packages with intervening bridges
US12074104B2 (en) 2018-09-27 2024-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages with ring-shaped substrates

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102568705B1 (en) 2018-10-05 2023-08-22 삼성전자주식회사 Semiconductor package, method for semiconductor package and method for re-distribution layer structure
KR102540829B1 (en) 2018-10-05 2023-06-08 삼성전자주식회사 Semiconductor package, method for semiconductor package and method for re-distribution layer structure
KR20210109258A (en) 2020-02-27 2021-09-06 삼성전자주식회사 Semiconductor package device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100327419A1 (en) * 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109727876A (en) * 2017-10-31 2019-05-07 台湾积体电路制造股份有限公司 Chip package and forming method thereof
KR20190062179A (en) * 2017-11-27 2019-06-05 파워테크 테크놀로지 인코포레이티드 Package structure and manufacturing method thereof
KR20190139490A (en) * 2018-06-08 2019-12-18 삼성전자주식회사 Semiconductor package, Package on Package device and method of fabricating the same
KR20200036771A (en) * 2018-09-27 2020-04-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Integrated circuit package and method
US11527474B2 (en) 2018-09-27 2022-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US12074104B2 (en) 2018-09-27 2024-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages with ring-shaped substrates
CN112951801A (en) * 2019-12-10 2021-06-11 爱思开海力士有限公司 Package-on-package comprising vertically stacked sub-packages with intervening bridges

Also Published As

Publication number Publication date
KR101550496B1 (en) 2015-09-04

Similar Documents

Publication Publication Date Title
US8941225B2 (en) Integrated circuit package and method for manufacturing the same
KR101550496B1 (en) Integrated circuit package and method for manufacturing the same
US9502335B2 (en) Package structure and method for fabricating the same
US10199320B2 (en) Method of fabricating electronic package
US10916533B2 (en) Semiconductor package
TWI482261B (en) Three-dimensional system-in-package package-on-package structure
TWI496270B (en) Semiconductor package and method of manufacture
CN108766940B (en) Stress compensation layer for 3D packaging
US9847284B2 (en) Stacked wafer DDR package
US20200343163A1 (en) Semiconductor device with through-mold via
TW201304018A (en) Stacked semiconductor package and manufacturing method thereof
US20230099787A1 (en) Semiconductor package and method of fabricating the same
KR101474189B1 (en) Integrated circuit package
KR20150045095A (en) Interposer, method for manufacturing the same and integrated circuit package with the interposer
KR101685068B1 (en) System in package and method for manufacturing the same
US20130256915A1 (en) Packaging substrate, semiconductor package and fabrication method thereof
CN109411418B (en) Electronic package and manufacturing method thereof
KR100673379B1 (en) Stack package and manufacturing method thereof
US10269774B2 (en) Semiconductor device
US20080237831A1 (en) Multi-chip semiconductor package structure
KR101432486B1 (en) Method for manufacturing of integrated circuit package
KR20090043945A (en) Stack package
KR101607989B1 (en) Package on package and method for manufacturing the same
KR101573311B1 (en) Semiconductor device and method for manufacturing the same
KR20110001182A (en) Fabricating method for semiconductor package

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E90F Notification of reason for final refusal
E701 Decision to grant or registration of patent right
FPAY Annual fee payment

Payment date: 20180801

Year of fee payment: 4