KR20110001182A - Fabricating method for semiconductor package - Google Patents

Abstract

PURPOSE: A semiconductor package manufacturing method is provided to improve the productivity by preventing the process defect by restraining the twisting of a wafer due to application of the bending prevention layer. CONSTITUTION: A first wafer(110) and a second wafer(120) in bare state is prepared. The first wafer is back grinded with the desired thickness. A bending prevention layer(130) is interposed on the first wafer. The first wafer is attached on the second wafer. A protective layer(140) is formed on the first wafer. The second wafer is eliminated.

Description

Fabrication Method for Semiconductor Package

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a manufacturing method of a semiconductor package capable of preventing process defects caused by warping of a wafer or semiconductor chip manufactured in a thin shape.

Each wafer contains hundreds to thousands of semiconductor chips printed with the same electrical circuit. Since the semiconductor chip itself cannot transmit or receive a signal from the outside, the semiconductor package provides an electrical connection to the semiconductor chip and a sealed package to withstand external shocks so as to have a physical function and shape.

In recent years, the thinning, high density and high mounting of semiconductor packages have emerged as important factors in order to meet the demand of light and small, which makes the volume of electronic devices lighter and lighter due to high performance of electric / electronic products.

Currently, computers, laptops and mobile phones have increased chip capacities such as large RAMs and flash memories as the memory capacity increases, but packages tend to be smaller. Situation.

In order to respond to this trend of thin and short, there is a rapid demand for thinner and thinner semiconductor packages utilizing a narrow space.

In order to manufacture a thin semiconductor package, manufacturing a semiconductor chip with a thinner thickness must be preceded, but the situation is stagnant with respect to a technology for manufacturing a thin semiconductor chip.

The main problem is pointed out that when backgrinding the bottom of the wafer and then sawing individual semiconductor chips by sawing, warpage defects appearing in the semiconductor chips that are thinly formed. Such warpage failures make it difficult to proceed with subsequent processes for fabricating a semiconductor package.

This warpage defect is mainly caused by the protective layer protecting the active surface of the semiconductor chip is made of the semiconductor chip and the heterogeneous material. That is, as the thickness of the semiconductor chip becomes thinner and thinner, the protective layer causes distortion of the semiconductor chip due to the force acting on the protective layer to shrink the semiconductor chip due to residual stress.

The warpage defect of the semiconductor chip is more noticeable in the model of the wafer-level package or the rearranged wiring structure having the stacked structure on the upper surface of the active surface, which is urgently needed to solve this problem.

Embodiments of the present invention provide a method of manufacturing a semiconductor package capable of preventing warpage of a wafer manufactured in a thin form.

A method of manufacturing a semiconductor package according to an embodiment of the present invention includes preparing a first and second wafers in a bare state; Backgrinding the first wafer such that a desired thickness remains; Attaching the backgrind first wafer onto the second wafer via a warpage prevention layer; Forming an active layer on the backgrind first wafer, the active layer including a protective layer disposed on an uppermost portion of the wafer; And removing the second wafer so that the warpage prevention layer is exposed.

The anti-bending layer is made of a material having a similar bending property as the active layer including the protective layer.

The anti-bending layer is made of an inorganic material including at least one of polyimide, benzocyclobutene, and epoxy resin, or a metal material including at least one of aluminum, copper, gold, and lead.

The protective layer is characterized in that made of polyimide. Removing the second wafer to expose the warpage prevention layer may be performed by a backgrinding process.

Removing the second wafer using the backgrinding process may be performed such that a part of the thickness of the bending preventing layer is removed together.

After removing the second wafer, sawing the first wafer including the active layer including the protective layer and the warpage prevention layer into a plurality of semiconductor chips; Attaching the sawed semiconductor chip onto a substrate; Connecting the semiconductor chip and the substrate with a connection member; Encapsulating one surface of the substrate including the semiconductor chip and the connection member; And attaching an external connection terminal to the other surface of the substrate.

According to the present invention, even if the bottom surface of the wafer is removed by a backgrinding process in order to fabricate a thin semiconductor chip, the warpage of the wafer can be prevented by applying a warpage prevention layer. Therefore, it can respond actively to manufacture a thin semiconductor package.

(Example)

Hereinafter, a semiconductor package according to an embodiment of the present invention will be described with reference to the accompanying drawings.

1 and 2 are cross-sectional views of respective semiconductor packages according to the present invention. In particular, FIG. 1 illustrates a face down BGA package of a center pad, and FIG. 2 illustrates a face up BGA package of an edge pad, and the same reference numerals are used for the same name.

As shown in FIG. 1, the BGA package 105 having a center pad face down method according to the present invention is a substrate 100 and a face down method on the substrate 100. And a semiconductor chip 150 attached through an adhesive (not shown).

A protective layer 140 is formed on the upper surface of the semiconductor chip 150 to protect the active surface. In addition, the lower surface of the semiconductor chip 150 facing the upper surface is formed with a bending prevention layer 130 to protect the inactive surface.

An upper surface of the substrate 100 including the semiconductor chip 150 may further include an encapsulation member 190 made of an epoxy molding compound (EMC). In the center of the semiconductor chip 150 and the substrate 100, a connection member 116 electrically connecting bonding pads (not shown) of the semiconductor chip 150 and bond fingers (not shown) of the substrate 100. Is located.

In this case, an insulating member 160 molded of a resin material may be further formed to protect the connection member 116. The connection member 116 may be, for example, a metal wire. Alternatively, the connection member 116 may be a through electrode or a bump.

 In addition, external connection terminals 144 for inputting and outputting signals from the semiconductor chip 150 to the lower surface of the substrate 110 may be attached to the ball lands 142, respectively.

In addition, as shown in FIG. 2, the face-up BGA package 105 of the edge pad includes the substrate 100, the semiconductor chip 150, the connection member 116, the protective layer 140, and the anti-bending layer 130. ), And the like. In this case, the semiconductor chip 150 may be attached in a face-up manner through the substrate 100 and an adhesive (not shown).

The structural difference between the edge pad face up BGA package 105 and the center pad face down BGA package 105 described above with reference to FIG. 1 is that the anti-bending layer 130 may contact the substrate 100. Since there is a difference in that the semiconductor chip 150 is attached to the substrate 100 in a face-up manner, other components are the same as in FIG.

1 and 2 described above, the protective layer 140 and the bending prevention layer 130 is preferably formed of a material having similar characteristics, respectively. That is, the protective layer 140 may be formed of any one of inorganic materials including polyimide, benzocyclobutene, and epoxy resin. The warpage prevention layer 130 may be any one of the above-described inorganic materials, or metal materials including tin (Sn), aluminum (Al), copper (Cu), gold (Au), lead (Pb), or the like. It may be formed of any one of the compounds between the inorganic material and the metal material.

In this case, the warpage prevention layer 130 functions to prevent distortion due to shrinkage applied by the protective layer 140 to the semiconductor chip 150. That is, the anti-bending layer 130 acts opposite to the force that the protective layer 140 contracts the semiconductor chip 150 to cancel the force.

Therefore, the above-described configuration has a structural advantage that the bending of the semiconductor chip 150 can be minimized by the additional design of the anti-bending layer 130 even if the thickness of the semiconductor chip 150 becomes thinner. In this case, the thickness of the anti-bending layer 130 may vary depending on the thickness of the semiconductor chip 150, and the physical properties of the forming material may be variously adjusted.

In particular, when the anti-bending layer 130 is formed on the lower surface of the semiconductor chip 150, a wafer level package (WLP) having a laminated structure on the active surface or an additional layer on the active surface by a rearrangement process An excellent effect can be expected in preventing warpage of a semiconductor chip provided with a redundancy layer (RDL).

Hereinafter, a method of manufacturing a semiconductor package according to the present invention will be described.

3A to 3D are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to the present invention in order of process.

As shown in FIG. 3A, a first wafer 110 and a second wafer 120 in a bare state are prepared. Next, a backgrinding process is performed on the first wafer 110 so that a desired thickness remains, thereby removing some thicknesses of the rear surface of the first wafer 110.

In the above-described process, the first wafer 100 may have a thickness thinner than that of the second wafer 120.

Next, the back-grinded first wafer 110 is attached onto the second wafer 120 via the warpage prevention layer 130.

As the warpage prevention layer 130, an inorganic material including at least one of polyimide, benzocyclobutene, and an epoxy resin, or a metal material including at least one of aluminum, copper, gold, and lead may be used.

As shown in FIG. 3B, an active layer (not shown) including a passivation layer 140 disposed on an uppermost surface of the backgrinded first wafer 110 is formed. The active layer may include a transistor, a resistor, a capacitor, and the like.

The protective layer 140 is formed to protect the active surface of the first wafer 110, and any one of inorganic materials including polyimide, benzocyclobutene, and epoxy resin may be used.

As shown in FIG. 3C, the second wafer (120 of FIG. 3B) is removed to expose the warpage prevention layer 130. For example, the above-described backgrinding process may be used to remove the second wafer.

In this case, during the step of removing the second wafer using the backgrinding process, some thicknesses of the anti-bending layer 130 may be removed together.

Alternatively, although not shown in the drawings, not all of the second wafers may be removed, but may be backgrinded to leave some thicknesses of the second wafers.

In the above-described process, the protective layer 140 and the warpage prevention layer 130 are provided on the upper and lower surfaces of the first wafer 110, respectively. Therefore, the direction in which the protective layer 140 located on the top surface of the first wafer 110 contracts and the force in which the bending prevention layer 130 located on the bottom surface of the first wafer 110 contracts are opposite to each other. Since the forces acting on both sides of the first wafer 110 are in conflict with each other, the warpage of the first wafer 110 can be minimized.

Next, the first wafer 110 including the protective layer 130 and the warpage prevention layer 140 is sawed into a plurality of semiconductor chips (not shown).

As shown in FIG. 3D, the semiconductor chip 150 may be formed on the upper surface of the semiconductor chip 150, that is, the protective layer 140 may face the substrate 110 by an adhesive (not shown). ) Alternatively, the semiconductor chip 150 may be attached with the anti-bending layer 140 facing the substrate 110.

In this case, the protective layer 130 may further include an opening (not shown) at a position corresponding to the bonding pad (not shown) of the semiconductor chip 150.

  Next, a bonding pad provided in the center of the semiconductor chip 150 and a bond finger (not shown) provided in the substrate 100 are bonded through the connection member 116. The connection member 116 electrically connects the bonding pad and the bond finger through the opening of the protective layer 130. The connection member 116 may include a metal wire. Alternatively, the connection member 116 may be a through electrode or a bump.

Next, an insulating member 160 made of a resin material is formed on the bottom surface of the semiconductor chip 150 to protect the connection member 116. Next, the upper surface of the substrate 100 including the semiconductor chip 150 is sealed with the encapsulation member 190, and the external connection terminals 144 are connected to the ball lands 142 disposed on the lower surface of the substrate 100. Attach.

In the above-described process, instead of removing the second wafer after forming the protective layer 130, the plurality of semiconductor chips may be formed using the second wafer and the first wafer without removing the second wafer. Sawing at 150, attaching each semiconductor chip 150 to the substrate 100, and then bonding the substrate 100 and the semiconductor chip 150 through the connection member 116 to remove the second wafer. It is okay.

As described above, the semiconductor package according to the present invention can be produced.

Hereinbefore, the present invention has been illustrated and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications and variations can be made.

1 is a cross-sectional view showing a face-down BGA package of a center pad according to the present invention.

Figure 2 is a cross-sectional view showing a face-up BGA package of the edge pad according to the present invention.

3A to 3D are cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to the present invention in the order of processing.

Claims (7)

Providing first and second wafers in a bare state; Backgrinding the first wafer such that a desired thickness remains; Attaching the backgrind first wafer onto the second wafer via a warpage prevention layer; Forming an active layer on the backgrind first wafer, the active layer including a protective layer disposed on an uppermost portion of the wafer; And Removing the second wafer such that the anti-warp layer is exposed; Method of manufacturing a semiconductor package comprising a. The method of claim 1, wherein the anti-bending layer is made of a material having a similar bending property to an active layer including the protective layer. The method of claim 2, wherein the anti-bending layer is made of an inorganic material including at least one of polyimide, benzocyclobutene, and epoxy resin, or a metal material including at least one of aluminum, copper, gold, and lead. A method for manufacturing a semiconductor package, characterized in that. The method of claim 1, wherein the protective layer is made of polyimide. The method of claim 1, wherein the removing of the second wafer to expose the warpage prevention layer is performed by a backgrinding process. The method of claim 5, wherein the removing of the second wafer using the backgrinding process is performed such that a part of the thickness of the warp prevention layer is removed together. The method of claim 1, wherein after removing the second wafer: Sawing the first wafer including the active layer including the protective layer and the warpage prevention layer into a plurality of semiconductor chips; Attaching the sawed semiconductor chip onto a substrate; Connecting the semiconductor chip and the substrate with a connection member; Encapsulating one surface of the substrate including the semiconductor chip and the connection member; And Attaching an external connection terminal to the other surface of the substrate; The method of manufacturing a semiconductor package further comprising.

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