TWI402962B - 多晶片堆疊在導線架上之半導體封裝構造及其導線架 - Google Patents
多晶片堆疊在導線架上之半導體封裝構造及其導線架 Download PDFInfo
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Description
本發明係有關於半導體裝置,特別係有關於一種多晶片堆疊在導線架上之半導體封裝構造及其導線架。
按,半導體封裝領域中,導線架(leadframe)係可作為晶片載體。導線架是為一經沖裁或蝕刻以形成引腳之金屬片,其上可安裝一個或多個半導體晶片。利用複數個引腳將電信傳遞至一印刷電路板或其他外部電器件。一般導線架之封裝包括塑膠小尺寸封裝(PSOP)、薄型小尺寸封裝(TSOP),及窄間距小尺寸封裝(SSOP)。習用TSOP封裝可依外引腳之數量可進一步細分為TSOP32、TSOP40、TSOP48以及TSOP56等等封裝規格。隨著晶片堆疊的數量增加,因應晶片銲墊位置與引腳之位置與密度,而使得晶片堆疊結構須適應於不同腳數之TSOP封裝而有不同之堆疊方式。
如第1圖所示,為習知一種多晶片堆疊在導線架上之半導體封裝構造,為TSOP48封裝規格,故具有48個外引腳。如第1與2圖所示,該半導體封裝構造100主要包含一導線架之複數個引腳111、三個或三個以上晶片120、複數個銲線130以及一封裝體140。該些晶片120係設置在該些引腳111上,並具有複數個單側銲墊121,可利用複數個晶背貼附層122以黏接該些晶片120至該些引腳111。最下方之晶片120可增設複數個黏晶膠條150而黏貼在該些引腳111上,以作為後續封膠時之模流通道。該些單側銲墊121係排列在該晶片120主動面之其中一側邊。可利用複數個銲線130將該些單側銲墊121電性連接至該些引腳111之內端,複數個銲線131電性連接相鄰晶片之單側銲墊121。而該封裝體140係密封該晶片120與該些銲線130。該封裝體140係具有兩平行對稱之引腳側,以供該些引腳111之外端延伸而出,另具有一與該些引腳側垂直之無外引腳側142,並且該些引腳111之內端係朝向該無外引腳側142。
如第2與3圖所示,該些晶片120係堆疊在該些引腳111上,在有限的封裝空間,為因應該些單側銲墊121之位置與該些引腳111之密度,該些晶片120為Z字形堆疊,故上方堆疊之兩晶片遮蓋了下方堆疊之兩晶片之單側銲墊121,在封裝過程須進行二次黏晶與二次打線步驟,在量產上不符合經濟效益。並且雙晶片組之間的打線弧高需利用一覆線膠層160來支撐,並密封部份之銲線131,造成封裝高度提高且增加材料成本。
為了解決上述之問題,本發明之主要目的係在於提供一種多晶片堆疊在導線架上之半導體封裝構造及其導線架,使引腳腳位與封裝體的尺寸分別符合不同封裝規格,但在封測製程上可共同治具,而達成節省成本之效用。
本發明之次一目的係在於提供一種多晶片堆疊在導線架上之半導體封裝構造及其導線架,使所有堆疊晶片呈階梯狀堆疊,在製程上可以一次黏晶與打線,達到省時與省工之效果。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種多晶片堆疊在導線架上之半導體封裝構造,主要包含一導線架、三個或三個以上晶片、複數個銲線以及一封裝體。該導線架係具有複數個引腳,該些引腳的腳位係符合第一封裝規格。三個或三個以上晶片係設置於該些引腳上,並具有複數個單側銲墊。該些銲線係連接該些引腳之內端與該些單側銲墊。該封裝體係密封該些晶片與該些銲線,該封裝體係具有兩平行對稱之引腳側,以供該些引腳之外端延伸而出,其中由該些引腳側之兩端各延長有為整數倍引腳間隔之引腳空白長度,以使該封裝體的尺寸係符合第二封裝規格,並使得該封裝體在與該些引腳側同方向的截面中,該些晶片呈階梯狀堆疊並且該些晶片的該些單側銲墊皆不被相鄰的晶片所覆蓋。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述的半導體封裝構造中,該所述引腳空白長度係可等同兩個引腳間隔(lead pitch)。
在前述的半導體封裝構造中,該所述第一封裝規格係可為TSOP48,即在同一引腳側上的引腳數量為24,所述第二封裝規格係可為TSOP56,即該封裝體的尺寸為14mm×20mm。
在前述的半導體封裝構造中,該所述引腳空白長度係可為1mm。
在前述的半導體封裝構造中,該封裝體可另具有一與前述引腳側垂直之無外引腳側,其長度係可大於前述引腳側之長度,以使該些引腳之內端匯集朝向該無外引腳側。
本發明還揭示一種導線架,適用於一多晶片堆疊在導線架上之半導體封裝構造,該導線架係具有複數個引腳,該些引腳的腳位係符合第一封裝規格,該導線架內係定義有一模封區,以供形成一封裝體,該些引腳之外端係由該模封區延伸而出,該些引腳之兩側更配設有複數個虛引腳,未延伸至該模封區內,用以界定該模封區供該些引腳延伸的側邊各延長有為整數倍引腳間隔之引腳空白長度,以使該封裝體的尺寸係符合第二封裝規格。
由以上技術方案可以看出,本發明之多晶片堆疊在導線架上之半導體封裝構造,有以下優點與功效:
一、可藉由封裝體在引腳側之兩端各延長有為整數倍引腳間隔之引腳空白長度作為其中一技術手段,引腳腳位與封裝體的尺寸分別符合不同封裝規格,使客戶端之印刷電路板不需要重新設計,可將成品直接焊在原有之印刷電路板上,在封測製程上並可共同治具,而達成節省成本之效用。
二、可藉由封裝體在引腳側之兩端各延長有為整數倍引腳間隔之引腳空白長度作為其中一技術手段,封裝體在與引腳側同方向的截面中,晶片呈階梯狀堆疊並且晶片的單側銲墊皆不被相鄰的晶片所覆蓋,在製程上可以一次黏晶與打線,達到省時與省工之效果。此外,晶片間不需要使用習知覆線膠層來支撐,可節省成本。
以下將配合所附圖示詳細說明本發明之實施例,然應注意的是,該些圖示均為簡化之示意圖,僅以示意方法來說明本發明之基本架構或實施方法,故僅顯示與本發明有關之元件與組合關係,圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理,以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計,詳細之元件佈局可能更為複雜。
依據本發明之一具體實施例,一種多晶片堆疊在導線架上之半導體封裝構造及其導線架舉例說明於第4至11圖,其中第6圖為在引腳側之側視圖,第7圖為與引腳側同方向之翻轉截面示意圖,第9圖為所使用導線架之俯視圖,第10圖為所使用導線架在經封裝體密封後之俯視圖。該半導體封裝構造200主要包含一導線架210、三個或三個以上晶片220、複數個銲線230以及一封裝體240。
第9圖中模封區214為第10圖中封裝體240的形成區域。如第9與10圖所示,該導線架210係具有複數個引腳211,該些引腳211的腳位係符合第一封裝規格。在本實施例中,該第一封裝規格係可為TSOP48,即在同一引腳側上的引腳數量為24。每一引腳211係可具有一內端212與一外端213,其中內端212係被該封裝體240密封,外端213則顯露於該封裝體240之外。該些內端212係可彎折並朝向該封裝體240之一無外引腳側242。該些引腳211係可由銅、銅合金或藉以製造導線架的各種高導電性與高熱傳導之金屬材料所形成。在該封裝體240形成之後,可藉由去框步驟,用切腳機器將該導線架210和邊框切割分離,之後再進行該些引腳211之外端213彎折的成形動作。
請參閱第7與8圖所示,三個或三個以上晶片220係設置於該些引腳211上,並具有複數個單側銲墊221。該些單側銲墊221係排列在該晶片220主動面之其中一側邊。相鄰晶片220間可利用晶背貼附層222相黏貼。晶背貼附層222係可為樹脂、B階膠體、黏性膠片(Film)、環氧黏膠(Epoxy)、非導電膠或液態膠體。最下方之晶片220係可增設複數個黏晶膠條250而呈細長條狀排列並貼附在該些引腳211上,該些黏晶膠條250相鄰間之空隙可作為後續封膠時之模流通道。該些黏晶膠條250之厚度可約為100微米。
該些銲線230係連接該些引腳211之內端212與該些單側銲墊221,以形成封裝內部電性連接。可另有複數個銲線231電性連接相鄰晶片220之單側銲墊221。該些銲線230、231係可利用打線製程所形成,可為金線、鋁線或其他可撓曲之金屬線。具體而言,該些晶片220之主動面係朝上並以階梯狀交錯排列,以使該些單側銲墊221露出,故可完成黏晶堆疊作業之後在一次進行打線作業,達到省時、省工之功效,詳細技術手段容後說明。打線步驟可採用習知之正向打線(forward bonding)或逆向打線(reverse bonding),並可在打線前預先在該些單側銲墊221上設置複數個結線凸塊(stud bump),再打線形成之銲線231之尾端連接至該些單側銲墊221上結線凸塊,以增加銲線230之黏著力與穩定度。
該封裝體240係可為一種內含矽氧填充物的絕緣性熱固性樹脂,如環氧模封化合物(EMC,epoxy molding compound),可利用模封(或稱轉移成形)方法形成。該封裝體240係密封該些晶片220、該些銲線230、231與該些引腳211之一部位,以使該些內部元件與外界隔離而免受外界衝擊或污染。如第4與10圖所示,該封裝體240係具有兩平行對稱之引腳側241,以供該些引腳外端211延伸而出。該兩引腳側241係與該無外引腳側242垂直,該兩無外引腳側242之長度係可大於前述引腳側241之長度,以使該些引腳211之內端212匯集朝向該無外引腳側242(請同時參照第9與10圖)。此外,如第4與5圖所示,該些引腳211之外端213係可由該封裝體240之該引腳側241延伸並彎折成形,作為對外電性傳遞。該些引腳211之外端213係可彎折成海鷗腳(gull lead),或可彎折成其他形狀,如I形或J形。
值得注意的,如第4與6圖所示,該些引腳側241之兩端各延長有為整數倍引腳間隔之引腳空白長度S,以使該封裝體240的尺寸係符合第二封裝規格,並使得該封裝體240在與該些引腳側241同方向的截面中(見於第7圖),該些晶片220呈階梯狀堆疊並且該些晶片220的該些單側銲墊221皆不被相鄰的晶片220所覆蓋。
詳細而言,如第9與10圖所示,該導線架210內係定義有一模封區214,以供形成該封裝體240,該些引腳211之外端213係由該模封區214延伸而出。如第9與11圖之放大圖所示,該些引腳211之兩側更配設有複數個虛引腳215,未延伸至該模封區214內,其排列間隔同該些引腳211外露部位的引腳間隔,用以界定該模封區214供該些引腳211延伸的側邊各延長有為整數倍引腳211間隔之引腳空白長度S,以使該封裝體240的尺寸係符合第二封裝規格。
具體而言,上所述第一封裝規格係可為TSOP48,上所述第二封裝規格係可為TSOP56,特別在以往的TSOP48封裝規格中,無法呈階梯狀堆疊三個或三個以上的晶片,在有限的封裝空間只能兩兩成組的Z字形堆疊(如第2圖所示)。在本實施例中,該些引腳211的腳位係符合TSOP48之引腳腳位,引腳間距約為0.5mm;而該封裝體240的尺寸係符合TSOP56之封裝體尺寸,即該封裝體240的尺寸為14mm×20mm,而不是TSOP48之封裝體尺寸,即12mm×20mm。
在製程上,可取用一TSOP56之導線架,利用沖壓(stamping)或蝕刻(etching)方法,裁斷TSOP56多餘之引腳,而形成該些虛引腳215,所餘引腳的數目為48。較佳地,裁斷多餘之引腳之步驟可在去框步驟一起進行。在本實施例中,如第9圖所示,該導線架210位於模封區214四角隅之整數倍引腳係為截斷,而形成該些虛引腳215,可為每角隅截斷兩個引腳。TSOP56之導線架在每角隅截斷兩個引腳之後,剩餘48個引腳。並且該些引腳211的腳位係符合TSOP48之引腳腳位規格。在去框步驟之後,該些虛引腳215係隨邊框裁去而不留下,藉以定義出前述之引腳空白長度S。該所述引腳空白長度S係可為1mm。所述引腳空白長度S係可由兩個虛引腳215所界定。換言之,如第6與10圖所示,上述之引腳空白長度S係可等同兩個引腳間隔(lead pitch)。以引腳側之側視圖第6圖與習知第1圖比較下,本發明之封裝體240在引腳側241之兩邊各多了一段引腳空白長度S。故本發明之封裝體240相對於習知TSOP48之封裝體為大且符合其它封裝規格。
因此,在該引腳側241之兩端各延長有為整數倍引腳間隔之引腳空白長度S,而該些引腳211腳位與該封裝體240的尺寸係可分別符合TSOP48與TSOP56之封裝規格。故客戶端之印刷電路板不需要重新設計,可將成品直接焊在原有之印刷電路板上,在封測製程上並可共同治具,而達成節省成本之效用。
此外,由於該封裝體240在該引腳側241之兩端各延長有為整數倍引腳間隔之引腳空白長度S,該封裝體240在與該些引腳側241同方向的截面中,該些晶片220可呈階梯狀堆疊並且該些晶片220的該些單側銲墊221皆不被相鄰的晶片220所覆蓋,在製程上可以一次黏晶與打線,達到省時與省工之效果。另,該些晶片220間不需要使用習知覆線膠層來支撐,可進一步節省成本。
以上所述,僅是本發明的較佳實施例而已,並非對本發明作任何形式上的限制,雖然本發明已以較佳實施例揭露如上,然而並非用以限定本發明,任何熟悉本項技術者,在不脫離本發明之技術範圍內,所作的任何簡單修改、等效性變化與修飾,均仍屬於本發明的技術範圍內。
S...引腳空白長度
100...半導體封裝構造
111...引腳
120...晶片
121...單側銲墊
122...晶背貼附層
130...銲線
131...銲線
140...封裝體
141...引腳側
142...無外引腳側
150...黏晶膠條
160...覆線膠層
200...半導體封裝構造
210...導線架
211...引腳
212...內端
213...外端
214...模封區
215...虛引腳
220...晶片
221...單側銲墊
222...晶背貼附層
230...銲線
231...銲線
240...封裝體
241...引腳側
242...無外引腳側
250...黏晶膠條
第1圖:為一種習知半導體封裝構造在一引腳側之側視圖。
第2圖:為習知半導體封裝構造與引腳側同方向之翻轉截面示意圖。
第3圖:為第2圖結構在未封膠前之局部放大示意圖。
第4圖:為依據本發明之一具體實施例的半導體封裝構造之俯視圖。
第5圖:為依據本發明之一具體實施例的半導體封裝構造在一非引腳側之前視圖。
第6圖:為依據本發明之一具體實施例的一種多晶片堆疊在導線架上之半導體封裝構造在一引腳側之側視圖。
第7圖:為依據本發明之一具體實施例的半導體封裝構造與引腳側同方向之翻轉截面示意圖。
第8圖:為第7圖結構在未封膠前之局部放大示意圖。
第9圖:為依據本發明之一具體實施例的半導體封裝構造所使用之導線架之俯視圖。
第10圖:為依據本發明之一具體實施例的半導體封裝構造使用之導線架在經封裝體密封後之俯視圖。
第11圖:為第10圖之局部放大示意圖。
S...引腳空白長度
200...半導體封裝構造
211...引腳
213...外端
240...封裝體
242...無外引腳側
Claims (5)
- 一種導線架,適用於一多晶片堆疊在導線架上之半導體封裝構造,該導線架係具有複數個引腳,該些引腳的腳位係符合第一封裝規格,該導線架內係定義有一模封區,以供形成一封裝體,該些引腳之外端係由該模封區延伸而出,該些引腳之兩側更配設有複數個虛引腳,未延伸至該模封區內,用以界定該模封區供該些引腳延伸的側邊各延長有為整數倍引腳間隔之引腳空白長度,以使該封裝體的尺寸係符合第二封裝規格。
- 根據申請專利範圍第1項之導線架,其中所述引腳空白長度係由兩個虛引腳所界定。
- 根據申請專利範圍第2項之導線架,其中所述第一封裝規格係為TSOP48,即在同一引腳側上的引腳數量為24,所述第二封裝規格係為TSOP56,即該模封區的尺寸為14mm×20mm。
- 根據申請專利範圍第3項之導線架,其中所述引腳空白長度係為1 mm。
- 根據申請專利範圍第1項之導線架,其中該模封區係具有一未有該些引腳延伸出之無外引腳側,其長度大於供該些引腳延伸的側邊之長度,以使該些引腳之內端匯集朝向該無外引腳側。
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