201112383 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於一種多晶 片堆疊在導線架上之半導體封裝構造及其導線架。 【先前技術】 曰按’半導體封裝領域中，導線架（leadframe)係可作為 s片载體。導線架是為一經沖裁或蝕刻以形成引腳之金 屬片’其上可安裝一個或多個半導體晶片。利用複數個 引腳將電信傳遞至-印刷電路板或其料部件… 般導㈣之封I包括塑料尺寸封裝（psQi>)、薄型小尺 寸封裝（tsop) ’及窄間距小尺寸封裝（ss〇p) ms〇p 封裝可依外㈣之數量可進—步細分為TSQp32、Ts〇p 4〇、TSOP48以及TS〇p56等等封農規格。隨著晶片堆疊 的數量增加’因應晶片銲墊位置與引腳之位置與密度， 而使得晶片堆叠結構須適應於不同腳數之⑽ 有不同之堆疊方式。 如第1圖所示，為習知—種多晶片堆疊在導線架上 +導體封裝構造，為TSOP48封農規格故具有“個 引腳。如第…圖所示，該半導體封裝構造1〇〇主 包含：導線架之複數個引腳U1、三個或三個以上晶 匕〇、複數個銲線130以及一封裝體14〇。該些晶片】 係設置在該些引腳111上’並具有複數個單側銲塾12: 可利用複數個晶背貼附層122以黏接該些晶片12〇至 Μ腳mm之晶片12G可增設複數個黏晶膠 201112383 150而黏貼在該些引腳lu上，以作為後續封膠時之模 流通道。該些單側銲墊121係排列在該晶片12〇主動面 之其中叫則邊。可利用複數個銲、線13〇將該些單側鲜塾 121電性連接至該些引腳1U之内端，複數個銲線ΐ3ι 電性連接相鄰晶片之單側銲墊121。而該封裝體14〇係 密封該晶片120與該些銲線13(^該封裝體14〇係具有 兩平行對稱之引腳侧，以供該些引腳lu之外端延伸而 出另具有一與該些引腳侧垂直之無外引腳側142，並 且該些引腳111之内端係朝向該無外引腳側142。 如第2與3圖所示，該些晶片1 2〇係堆疊在該些引腳 ui上，在有限的封裝空間，為因應該些單側銲墊121 之位置與該些引腳111之密度，該些晶片120為Z字形 堆疊，故上方堆疊之兩晶片遮蓋了下方堆疊之兩晶片之 單側銲墊121，在封裝過程須進行二次黏晶與二次打線 步驟，在量產上不符合經濟效益。並且雙晶片組之間的 打線弧高需利用一覆線膠層160來支撐，並密封部份之 鮮線131 ’造成封裝高度提高且增加材料成本。 【發明内容】 為了解決上述之問題’本發明之主要目的係在於提供 一種多晶片堆疊在導線架上之半導體封裝構造及其導線 架’使弓丨腳腳位與封裝體的尺寸分別符合不同封裝規 格’但在封測製程上可共同治具，而達成節省成本之效 用。 本發明之次一目的係在於提供一種多晶片堆疊在導 201112383 線架上之半導體封裝構造及其導線架，使所有堆疊晶片 呈階梯狀堆疊，在製程上可以—次黏晶與打線達到省 時與省工之效果。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種多晶片堆疊在導線架上之 半導體封裝構造’主要包含一導線架、三個或三個以上 晶片、複數個銲線以及-封裝體。該導線架係具有複數 個引腳’該些引腳的腳位係符合第_封裝規格。三個或 三個以上晶片係設置於該些引腳上，並具有複數個單側 銲墊。該些銲線係連接該些引腳之内端與該些單側銲 塾。該封裝體係密封該些晶片與該些銲線，該封裝體係 具有兩平行對稱之引腳側，以供該些引腳之外端延伸而 出’其中由該些引腳側之兩端各延長有為整數倍引腳間 隔之引腳空白長度，以使該封裝體的尺寸係符合第二封 裝規格，並使得該封裝體在與該些弓丨腳^向的截面 中，該些晶片呈階梯狀堆疊並且該些晶片的該些單側鲜 塾皆不被相鄰的晶片所覆蓋。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的半導體封裝構造中，該所述引腳空白長度係 可等同兩個引腳間隔（lead pitch)。 在前述的半導體封裝構造中，該所述第一封裝規格係 可為TSOP48，即在同一引腳側上的引腳數量為24，所 述第二封裝規格係可為TSOP56，即該封裝體的尺寸為 201112383 14mm x 20mm。 在前述的半導體封裝構造中，該所述弓i腳空白長度係 可為1 mm。 在則述的半導體封裝構造中，該封裝體可另具有一與 前述引腳側垂直之無外引腳側，其長度係可大於前述引 腳側之長度U使該些引腳之内端匯集朝向該無外引腳 側0BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor package structure in which a polycrystalline wafer is stacked on a lead frame and a lead frame thereof. [Prior Art] In the field of semiconductor packaging, a leadframe can be used as a s-chip carrier. The lead frame is a metal piece that has been stamped or etched to form a lead onto which one or more semiconductor wafers can be mounted. The use of a plurality of pins to transfer telecommunications to the printed circuit board or its components... The package (I) includes a plastic package (psQi>), a small package (tsop) and a narrow pitch package (ss〇) p) The ms〇p package can be further subdivided into TSQp32, Ts〇p 4〇, TSOP48 and TS〇p56 according to the number of external (4). As the number of wafer stacks increases, the wafer stack structure must accommodate different numbers of pins (10) depending on the position of the wafer pads and the location and density of the pins. As shown in Fig. 1, it is a conventional type of multi-wafer stacked on a lead frame + a conductor package structure, which has a "pin" for the TSOP48 enclosure specification. As shown in Fig. 1, the semiconductor package structure is The main body includes: a plurality of pins U1, three or more wafers, a plurality of bonding wires 130, and a package body 14 of the lead frame. The chips are disposed on the pins 111 and have A plurality of single-side soldering pads 12: a plurality of wafer backing layers 122 can be used to bond the wafers 12 to 10 mm of the wafers 12G. A plurality of adhesives 201112383 150 can be added and adhered to the pins. The upper side solder pads 121 are arranged in the inner side of the active surface of the wafer 12, and the plurality of solders and lines 13 can be used to make the single sides fresh. The 塾121 is electrically connected to the inner ends of the pins 1U, and the plurality of bonding wires ΐ3 ι electrically connect the one-side pads 121 of the adjacent wafers, and the package 14 seals the wafers 120 and the bonding wires 13 (^ The package body 14 has two parallel symmetrical pin sides for extending the outer ends of the pins lu There is an outer lead side 142 that is perpendicular to the pin sides, and the inner ends of the pins 111 face the outer lead side 142. As shown in Figures 2 and 3, the wafers 1 2〇 Stacked on the pins ui, in a limited package space, the wafers 120 are zigzag stacked due to the position of the single-sided pads 121 and the density of the pins 111, so the upper two stacked The wafer covers the single-sided pad 121 of the two wafers stacked underneath, and the secondary bonding and secondary bonding steps are required in the packaging process, which is not economical in mass production, and the arcing height between the two-chip groups is required. Supporting a layer of glued layer 160 and sealing a portion of the fresh line 131' results in an increase in package height and an increase in material cost. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a multi-wafer stack. The semiconductor package structure on the lead frame and the lead frame thereof enable the dimensions of the bow and the foot and the size of the package to meet different package specifications, respectively, but the fixture can be jointly cured on the sealing and testing process, thereby achieving cost-saving utility. Second order The system is to provide a multi-wafer semiconductor package structure and lead frame stacked on the 201112383 wire frame, so that all stacked chips are stacked in a step-like manner, and the process can save time and labor. The object of the present invention and the technical problem thereof are achieved by the following technical solutions. The present invention discloses a semiconductor package structure in which a multi-wafer is stacked on a lead frame, which mainly comprises a lead frame, three or more wafers, and a plurality of a bonding wire and a package. The lead frame has a plurality of pins. The pins of the pins conform to the first package specification. Three or more chip sets are disposed on the pins, and have A plurality of single-sided pads are connected to the inner ends of the pins and the one-side pads. The package system seals the wafers and the bonding wires, the package system has two parallel symmetrical pin sides for the outer ends of the pins to extend out, wherein each of the two sides of the pins are extended There is a pin blank length which is an integer multiple of the pin spacing, so that the size of the package conforms to the second package specification, and the package is stepped in the cross section with the legs. The stacks are stacked and the single side fresh slabs of the wafers are not covered by adjacent wafers. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the aforementioned semiconductor package construction, the pin blank length may be equivalent to two lead pitches. In the foregoing semiconductor package structure, the first package specification may be TSOP48, that is, the number of pins on the same pin side is 24, and the second package specification may be TSOP56, that is, the package body The size is 201112383 14mm x 20mm. In the aforementioned semiconductor package construction, the length of the bow may be 1 mm. In the semiconductor package structure described above, the package body may have an outer lead side perpendicular to the pin side, and the length may be greater than the length U of the pin side to bring the inner ends of the pins together. Towards the no-outer side 0
本發明還揭示一種導線架，適用於—多晶片堆疊在導 線架上之半導體封裝構造，料線架係具有複數個引 腳’該些引腳的腳位係符合第—封裝規格，該導線架内 係定義有—模封區，以供形成—封襄體，該些引腳之外 端係由該模封區延伸而丨，該些引腳之兩侧更配設有複 數個虛引腳，未延伸至該模封區内，用以界定該模封區 供：些弓丨腳延伸的侧邊各延長有為整數倍引腳間隔之引 白長度，以使該封裝體的尺寸係符合第二封裝規格。 由以上技術方案可以看出，本發明之多晶片堆疊在導 線架之半導體封裝構造，有以下優點與功效： 可藉由封裝體在引腳狀兩端各延長有&整數倍引 腳間隔之引腳空白長度作為其中一技術手段，引腳 腳位與封裝體的尺寸分別符合不同封裝規格使客 戶端之印刷電路板不需要重新設計，可將成品直接 在原有之印刷電路板上，在封測製程上並可共同 治具，而達成節省成本之效用。 可藉由封裝體在引腳側之兩端各延長有為整數倍引 201112383 腳間隔之引腳空白長度作為其中一技術手段，封装 體在與引腳侧同方向的截面中，晶片呈階梯狀堆叠 並且晶片的單侧鲜塾皆不被相鄰的晶片所覆蓋，在 製程上可以一次黏晶與打線，達到省時與省工之效 果。此外，晶片間不需要使用習知覆線膠層來支樓， 可節省成本。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本發 明有關之元件與組合關係，圖中所顯示之元件並非以實 際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比 例與其他相關尺寸比例或已誇張或是簡化處理以提供 更清楚的描述。實際實施之數目、形狀及尺寸比例為一 種選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之一具體實施例，一種多晶片堆疊在導線 架上之半導體封裝構造及其導線架舉例說明於第4至u 圖’其中第6圖為在引腳侧之側視圖，第7圖為與引腳 侧同方向之翻轉截面示意圖，第9圖為所使用導線架之 俯視圖，帛10 ®為所使用導㈣在經封裝體密封後之俯 視圖。該半導體封裝構》20〇主要包含-導線架210、 一個或二個以上晶片220、複數個銲線230以及一封裝 體 240 〇 第圖中模封區214為第10圖中封裝體240的形成 201112383 區域。如第9與10圖所示，該導線架210係具有複數個 引腳211’該些引腳211的腳位係符合第一封裝規格。 在本實施例中，該第一封裝規格係可為TSOP48，即在同 一引腳側上的引腳數量為24。每一引腳211係可具有一 内端212與一外端213，其中内端212係被該封裝體240The invention also discloses a lead frame suitable for a semiconductor package structure in which a multi-wafer is stacked on a lead frame, the material line frame has a plurality of pins, and the pins of the pins conform to the first package specification, and the lead frame The internal system defines a die-sealing area for forming a sealing body, and the outer ends of the pins are extended by the molding area, and the plurality of dummy pins are further disposed on both sides of the pins. , extending into the mold sealing area, for defining the molding area for: the sides of the extension of the arches are extended by an integral multiple of the lead length of the lead spacing, so that the size of the package is consistent Second package specification. It can be seen from the above technical solution that the multi-wafer stack of the present invention is stacked in the semiconductor package structure of the lead frame, and has the following advantages and effects: It can be extended by the package at both ends of the pin shape with an integer multiple of the pin spacing. As a technical means, the pin blank length and the size of the package respectively conform to different package specifications, so that the printed circuit board of the client does not need to be redesigned, and the finished product can be directly on the original printed circuit board. The cost can be achieved by measuring the process and jointly curing the tool. As a technical means, the length of the pin gap of the 201112383 pin spacing can be extended by the package at the two ends of the pin side. The package is stepped in the same direction as the pin side. Stacking and one-side fresh enamel of the wafer are not covered by adjacent wafers, and the process can be bonded and lined at one time, thereby achieving the effect of saving time and labor. In addition, there is no need to use a conventional cover tape layer between the wafers to support the building, which can save costs. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which Therefore, only the components and combinations related to the present invention are shown. The components shown in the drawings are not drawn in proportion to the actual number, shape, and size of the actual implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. According to an embodiment of the present invention, a semiconductor package structure in which a multi-wafer is stacked on a lead frame and a lead frame thereof are illustrated in FIGS. 4 to u. FIG. 6 is a side view on the pin side, FIG. A schematic view of the inverted section in the same direction as the pin side, Figure 9 is a top view of the lead frame used, and 帛10® is the top view of the used guide (4) after being sealed by the package. The semiconductor package structure comprises: a lead frame 210, one or more wafers 220, a plurality of bonding wires 230, and a package body 240. The molding region 214 in the figure is the formation of the package body 240 in FIG. 201112383 area. As shown in Figures 9 and 10, the leadframe 210 has a plurality of pins 211' which are compliant with the first package specification. In this embodiment, the first package specification can be TSOP48, i.e., the number of pins on the same pin side is 24. Each pin 211 can have an inner end 212 and an outer end 213, wherein the inner end 212 is bound by the package 240
密封，外端2 1 3則顯露於該封裝體24〇之外。該些内端 212係可彎折並朝向該封裝體24〇之一無外引腳侧242。 該些引腳211係可由銅、銅合金或藉以製造導線架的各 種高導電性與高熱傳導之金屬材料所形成。在該封裝體 240形成之後，可藉由去框步驟，用切腳機器將該導線 架210和邊框切割分離，之後再進行該些引腳2ιι之外 端213弯折的成形動作。 請參閱第7與8圖所示，三個或三個以上晶片22〇 係設置於該些引腳211上，並具有複數個單側銲墊221。 該些單側銲塾22i係排列在該晶片22〇主動面之其中一 侧邊。相鄰晶Ho間可利用晶背貼附層222相黏貼。 晶背貼附"2係、可為樹脂、B階膠體、黏性膠片 (Film)、環氧黏膝（EpOXy)、非導雷 ” 升等電膠或液態膠體。最下 方之晶片220係可增設複數個黏曰 ’黏晶膠條250而呈細長條 狀排列並貼附在該些引腳2丨丨卜 上，該些黏晶膠條250相 鄰間之空隙可作為後續封膠時 K模流通道。該些黏晶膠 條2 50之厚度可約為ι〇〇微米。 該些銲 單側銲墊 線230係連接該些5丨腳211 22i ’以形成封裝内部電性 之内端212與該些 連接。可另有複數 201112383 ， 個銲線231電性連接相鄰晶片220之單侧銲墊221。該 些銲線230、231係可利用打線製程所形成，可為金線、 鋁線或其他可撓曲之金屬線a具體而言，該些晶片22〇 之主動面係朝上並以階梯狀交錯排列，以使該些單侧銲 墊221露出，故可完成黏晶堆疊作業之後在一次進行打 線作業，達到省時、省工之功效，詳細技術手段容後說 明。打線步驟可採用習知之正向打線（f〇rward b〇nding) 鲁 或逆向打線（reverse bonding) ’並可在打線前預先在該些 單側銲塾221上設置複數個結線凸塊（stud bump)，再打 線形成之銲線23 1之尾端連接至該些單侧銲墊22 i上結 線凸塊，以增加銲線230之黏著力與穩定度。 該封裝體240係可為一種内含石夕氧填充物的絕緣性 熱固性樹脂’如環氧模封化合物（EMC，epoxy m〇lding compound) ’可利用模封（或稱轉移成形）方法形成。該封 裝體240係密封該些晶片22〇、該些銲線230、231與該 _ 些引腳2 11之一部位，以使該些内部元件與外界隔離而 免受外界衝擊或污染。如第4與10圖所示，該封裝體 240係具有兩平行對稱之引腳側24 1，以供該些引腳外端 211延伸而出。該兩引腳側241係與該無外引腳侧242 垂直，該兩無外引腳側242之長度係可大於前述引腳側 241之長度，以使該些引腳211之内端212匯集朝向該 無外引腳側242(請同時參照第9與10圖）。此外，如第 4與5圖所示，該些引腳211之外端213係可由該封裝 體'240之該引腳侧24 1延伸並彎折成形’作為對外電性 201112383 傳遞。該些211之外端213料f折成㈣mguU lead) ’或可彎折成其他形狀，如I形或】形。 該些引腳側241 值知注意的，如第4與6圖所示 之兩端各延長有為整數倍引腳間隔之引腳空白長度§， 以使該封m4G的尺寸係符合第二封裝規格，並使得 該封裝體240在與該些引腳側241同方向的截面中（見於 第7圖），該些晶片220呈階梯狀堆疊並且該些晶片22〇Sealed, the outer end 2 1 3 is exposed outside the package 24 〇. The inner ends 212 are bendable and face one of the package bodies 24 without the outer pin side 242. The pins 211 are formed of copper, a copper alloy or various highly conductive and highly thermally conductive metal materials from which the lead frame is fabricated. After the package body 240 is formed, the lead frame 210 and the frame can be cut and separated by a cutting machine by a frame removing step, and then the forming operation of bending the outer ends 213 of the pins 2 ι is performed. Referring to Figures 7 and 8, three or more wafers 22 are disposed on the pins 211 and have a plurality of single-sided pads 221. The one-sided solder fillets 22i are arranged on one of the sides of the active surface of the wafer 22. The adjacent crystals Ho can be adhered by the crystal back adhesion layer 222. Crystal back attached " 2 series, can be resin, B-stage colloid, adhesive film (Film), epoxy knee (EpOXy), non-guided lightning, etc., or liquid colloid. The bottom of the 220 series A plurality of adhesive viscous glue strips 250 may be added and arranged in a slender strip shape and attached to the pins 2, and the gap between the adjacent adhesive strips 250 may be used as a subsequent sealing. The K-molding channel, the thickness of the adhesive strips 2 50 can be about ι 〇〇. The solder single-sided pad lines 230 are connected to the 5 feet 211 22i ' to form the internal electrical properties of the package. The terminal 212 is connected to the plurality of terminals. The plurality of bonding wires 231 are electrically connected to the one-side pads 221 of the adjacent wafers 220. The bonding wires 230 and 231 can be formed by a wire bonding process, and can be gold wires. Specifically, the aluminum wires or other flexible metal wires a specifically have the active faces of the wafers 22 facing upward and staggered in a stepped manner so that the single-sided pads 221 are exposed, so that the die-bonding can be completed. After the stacking operation, the wire-laying operation is performed once, which saves the time and labor saving effect, and the detailed technical means is explained later. The step may be a conventional forward line (f〇rward b〇nding) or reverse bonding ' and may be provided with a plurality of knot bumps on the one side solder 221 before the wire is wired. The end of the bonding wire 23 1 formed by the re-wiring is connected to the bonding bumps on the one-side pads 22 i to increase the adhesion and stability of the bonding wires 230. The package 240 can be an embedded stone. An insulating thermosetting resin such as an epoxy molding compound (EMC) can be formed by a die-sealing method, or a package forming method, in which the package 240 is sealed. The soldering wires 230, 231 and one of the pins 21 to isolate the internal components from the outside from external impact or contamination. As shown in Figures 4 and 10, the package 240 There are two parallel symmetrical pin sides 24 1 for extending the pin outer ends 211. The two pin sides 241 are perpendicular to the outerless pin side 242, and the two outer pin sides 242 The length can be greater than the length of the aforementioned pin side 241 to make the inner end 212 of the pins 211 The set faces the outer lead side 242 (please refer to FIGS. 9 and 10 at the same time). Further, as shown in FIGS. 4 and 5, the outer ends 213 of the pins 211 may be derived from the package '240. The foot side 24 1 extends and is bent and formed 'as external electrical conductivity 201112383. The outer end 213 of the 211 material f is folded into (four) mguU lead) ' or can be bent into other shapes, such as an I shape or a shape. The value of the foot side 241 is noted. For example, the pin blank length § is an integer multiple of the pin spacing, as shown in the fourth and sixth figures, so that the size of the m4G is in accordance with the second package specification, and In the cross section of the package body 240 in the same direction as the pin sides 241 (see FIG. 7), the wafers 220 are stacked in a stepwise manner and the wafers 22 are folded.
的該些單侧銲墊221皆不被相鄰的晶片22〇所覆蓋。 詳細而言，如第9與1〇圖所示，該導線架21〇内係 定義有—模封區214,以供形成該封裝體24〇，該些引腳 211之外端213係由該模封區214延伸而出。如第9與 11圖之放大圖所示，該些引腳211之兩側更配設有複數 個虛引腳215，未延伸至該模封區214内，其排列間隔 同該些引腳2 11外露部位的引腳間隔，用以界定該模封 區214供該些引腳211延伸的側邊各延長有為整數倍引 腳211間隔之引腳空白長度s，以使該封裝體240的尺 寸係符合第二封裝規格。 具體而s ’上所述第一封裝規格係可為TS〇p48，上 所述第二封裝規格係可為TS〇P56，特別在以往的 TSOP48封裝規格中，無法呈階梯狀堆疊三個或三個以上 的晶片，在有限的封裝空間只能兩兩成組的z字形堆疊 (如第2圖所示）。在本實施例中，該些引腳2ΐι的腳位 係符合TSOP48之引腳腳位，引腳間距約為〇 5mm，·而 該封裝體240的尺寸係符合TS〇p56之封裝體尺寸，即 10 201112383 該封裝體240的尺寸為14mm x 20mm，而不是Ts〇p48 之封裝體尺寸，即12mm x 20mm。 在製程上，可取用一 TSOP56之導線架，利用沖壓 (stamping)或蝕刻（etching)方法，裁斷TS〇p56多餘之引 腳，而形成該些虛引腳215,所餘引腳的數目為48。較 佳地，裁斷多餘之引腳之步驟可在去框步驟一起進行。 在本實施例中，如第9圖所示，該導線架2丨〇位於模封 區214四角隅之整數倍引腳係為截斷，而形成該些虛引 腳215,可為每角隅截斷兩個引腳。tSOP56之導線架在 每角隅截斷兩個引腳之後，剩餘48個引腳。並且該些引 腳211的腳位係符合TSOP48之引腳腳位規格。在去框 步驟之後’該些虛引腳215係隨邊框裁去而不留下，藉 以疋義出刖述之引腳空白長度S。該所述引腳空白長度s 係可為1 mm。所述引腳空白長度s係可由兩個虛引腳 215所界定。換言之，如第6與10圖所示，上述之引腳 工白長度s係可等同兩個引腳間隔（丨ead pitch)。以引腳 侧之側視圖第6圖與習知第1圖比較下，本發明之封裂 體240在引腳側241之兩邊各多了一段引腳空白長度 S。故本發明之封裝體240相對於習知TSOp48之封裝體 為大且符合其它封裝規格。 因此，在該引腳侧241之兩端各延長有為整數倍引腳 間隔之引腳空白長度S’而該些引腳211腳位與該封裳 體240的尺寸係可分別符合TSOP48與TSOP56之封裳 規格。故客戶端之印刷電路板不需要重新設計，可將成 201112383 品直接焊在原有之印刷電路板上，在封測製程上並可共 同治具’而達成節省成本之效用。 此外’由於該封裝體240在該引腳側241之兩端各延 長有為整數倍引腳間隔之引腳空白長度S，該封裝體24〇 在與該些引腳側241同方向的截面中，該些晶片220可 呈階梯狀堆疊並且該些晶片22〇的該些單側銲墊221皆 不被相鄰的晶片220所覆蓋，在製程上可以一次黏晶與 打線，達到省時與省工之效果。另，該些晶片22〇間不 需要使用習知覆線膠層來支撐，可進一步節省成本。 以上所述，僅是本發明的較佳實施例而已，並非對本 發明作任何形式上的限制，雖然本發明已以較佳實施例 揭露如上，然而並非用以限定本發明，任何熟悉本項技 術者在不脫離本發明4技術範圍内，所作的任何簡單 修改、等效性變化與修飾，均仍屬於本發明的技術範圍 内。 【圖式簡單說明】 第1.圖：為一種習知半導體射奘播、也士 干导體封裝構造在一引腳侧之侧視 圖。 第2圖·為習知半導體封獎播生饱 封裝構也與弓丨腳側同方向之翻轉 截面示意圖。 第3圖：為第2圖結構在未封膠前 、局部放大不意圖。 第4圖.為依據本發明之一且體眚分 八體貫施例的半導體封裝構 造之俯視圖。 第5圖.為依據本發明之一且體眚始， 八貫施例的半導體封裝構 12 201112383 造在一非引腳侧之前視圖。 第ό圖··為依據本發明之一具體實施心-種彡晶片堆 憂在導線架上之半導體封敦攝造在—引腳侧之 側視圖。 第7圖：為依據本發明之-具體實^的半導體封裝構 造與引腳側同方向之翻轉截砣_也向 %甸不意圖。None of the one-sided pads 221 are covered by adjacent wafers 22A. In detail, as shown in FIGS. 9 and 1 , the lead frame 21 defines a die seal region 214 for forming the package body 24 , and the outer ends 213 of the pins 211 are The molding area 214 extends out. As shown in the enlarged views of the ninth and eleventh figures, the two sides of the pins 211 are further provided with a plurality of dummy pins 215, which are not extended into the die seal region 214, and are arranged at intervals corresponding to the pins 2 The pin spacing of the exposed portion is used to define the die pad 214 for extending the side edges of the pins 211 to have a pin blank length s that is an integer multiple of the pin 211 spacing, so that the package body 240 is The dimensions are in accordance with the second package specification. Specifically, the first package specification may be TS〇p48, and the second package specification may be TS〇P56. In the conventional TSOP48 package specification, three or three steps cannot be stacked in a stepwise manner. More than one wafer can only be stacked in groups of zigzags in a limited package space (as shown in Figure 2). In this embodiment, the pins of the pins 2ΐ are in accordance with the pin positions of the TSOP48, and the lead pitch is about mm5 mm, and the size of the package 240 conforms to the package size of TS〇p56, that is, 10 201112383 The size of the package 240 is 14mm x 20mm instead of the package size of Ts〇p48, ie 12mm x 20mm. In the process, a TSOP56 lead frame can be used, and the redundant pins of the TS〇p56 are cut by stamping or etching, and the dummy pins 215 are formed, and the number of remaining pins is 48. . Preferably, the step of cutting the excess pins can be performed in a deframed step. In this embodiment, as shown in FIG. 9, the lead frame 2 is located at an integral multiple of the corner of the die pad 214, and the pin is cut off, and the dummy pins 215 are formed, which can be cut off for each corner. Two pins. The lead frame of the tSOP56 has two pins remaining after each corner is cut off by two pins. And the pins of these pins 211 are in accordance with the pinout specifications of TSOP48. After the deblocking step, the dummy pins 215 are cut away from the frame without leaving, so that the pin blank length S is described. The pin blank length s can be 1 mm. The pin blank length s can be defined by two dummy pins 215. In other words, as shown in Figures 6 and 10, the above-mentioned pin length s can be equivalent to two pin spacings (丨ead pitch). The cracker 240 of the present invention has a length of pin blank S on each side of the pin side 241 in comparison with the side view of the pin side, Fig. 6, in comparison with the conventional Fig. 1. Therefore, the package 240 of the present invention is large compared to the conventional TSOp48 package and conforms to other package specifications. Therefore, a pin blank length S′ which is an integer multiple of the pin spacing is extended at both ends of the pin side 241, and the pins 211 and the size of the sealing body 240 can respectively conform to TSOP48 and TSOP56. The cover size. Therefore, the printed circuit board of the client does not need to be redesigned, and the 201112383 product can be directly soldered to the original printed circuit board, and the cost can be achieved by combining the fixtures on the packaging and testing process. In addition, since the package body 240 is extended at both ends of the pin side 241 by a pin blank length S which is an integral multiple of the pin spacing, the package body 24 is in a cross section in the same direction as the pin sides 241. The wafers 220 can be stacked in a stepped manner, and the single-sided pads 221 of the wafers 22 are not covered by the adjacent wafers 220. The process can be bonded and lined at one time, saving time and province. The effect of the work. In addition, the wafers 22 are not required to be supported by a conventional coating layer, which further saves cost. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made by the present invention within the technical scope of the present invention are still within the technical scope of the present invention. [Simple description of the drawing] Fig. 1. A side view of a conventional semiconductor firing sling, a dry conductor package structure on one pin side. Fig. 2 is a schematic cross-sectional view of the conventional semiconductor package with the package encapsulation in the same direction as the side of the bow. Figure 3: For the structure of Figure 2, before the unsealing, partial enlargement is not intended. Fig. 4 is a plan view showing the structure of a semiconductor package in accordance with one embodiment of the present invention. Fig. 5 is a front view of a non-pin side of a semiconductor package 12 201112383 in accordance with one embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS A side view of a semiconductor package mounted on a lead frame is shown in the side of the pin-side. Fig. 7 is a diagram showing the flip-flop of the semiconductor package structure in the same direction as the pin side according to the present invention.
第8圖：為第7圖結構在未封膠前之局部放大示意圖。 第9圖·•為依據本發明之一具體實施例的半導體封裝構 造所使用之導線架之俯視圖。 第1〇圖：為依據本發明之一具體實施例的半導體封裝構 造使用之導線架在經封裝體密封後之俯視圖。 第11圖：為第10圖之局部放大示意圖。 【主要元件符號說明】 s 引腳空白長度 100半導體封裝構造 111引腳 120 晶片 121 122 晶背貼附層 130 銲線 131 140 封裝體 141 142 無外引腳侧 150 黏晶膠條 160 200 半導體封裝構造 210 導線架 211 單側銲墊 銲線 弓丨腳側 覆線膠層 弓丨腳 212 内端 13 201112383 • 213外端 214模封區 215虛引腳 . 220晶片 222晶背貼附層 221單侧銲墊 230銲線 240封裝體 231 銲線 241引腳側 250黏晶膠條 242無外引腳侧 • • 14Figure 8 is a partial enlarged view of the structure of Figure 7 before unsealing. Fig. 9 is a plan view of a lead frame used in a semiconductor package structure in accordance with an embodiment of the present invention. Fig. 1 is a plan view showing a lead frame used for a semiconductor package structure according to an embodiment of the present invention after being sealed by a package. Figure 11 is a partial enlarged view of Fig. 10. [Main component symbol description] s Pin blank length 100 Semiconductor package structure 111 pin 120 Wafer 121 122 Crystal back attach layer 130 Solder wire 131 140 Package 141 142 No external pin side 150 Adhesive strip 160 200 Semiconductor package Construction 210 lead frame 211 single-side pad welding wire bow foot side cover line rubber layer bow foot 212 inner end 13 201112383 • 213 outer end 214 mold sealing area 215 virtual pin. 220 wafer 222 crystal back attached layer 221 single Side pad 230 bond wire 240 package 231 bond wire 241 pin side 250 adhesive strip 242 no outer pin side • • 14