TWI628761B - 一種封裝結構及其製造方法 - Google Patents

一種封裝結構及其製造方法 Download PDF

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TWI628761B
TWI628761B TW105136146A TW105136146A TWI628761B TW I628761 B TWI628761 B TW I628761B TW 105136146 A TW105136146 A TW 105136146A TW 105136146 A TW105136146 A TW 105136146A TW I628761 B TWI628761 B TW I628761B
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Taiwan
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conductive pattern
conductive element
conductive
metal blocks
metal
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TW105136146A
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English (en)
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TW201707171A (zh
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呂保儒
陳大容
林逸程
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乾坤科技股份有限公司
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Abstract

一種在金屬架上形成傳導圖案之電性連結堆疊架之製造方法及具有該金屬架之封裝結構。在一具體實施中，該電性連結堆疊架係在一金屬架形成一凹洞以及於此凹洞中結合一傳導元件之方法製作。在另一具體實施中，該電性連結堆疊架係在一導線架的上表面或下表面或上下表面分別形成該傳導圖案。該封裝結構具有使用該方法之導線架。

Description

一種封裝結構及其製造方法
本發明係有關一種封裝結構，特別指一種電性連結金屬架之製造方法與具有該金屬架之封裝結構。
導線架(lead frame)是一種被應用在積體電路(IC)封裝的材料，其具有不同的型式，例如四邊引腳扁平式封裝(QFP)、薄小外型封裝(TSOP)、小外型晶體管(SOT)或J型引腳小外型封裝(SOJ)。藉由組裝和互相連結一半導體元件至一導線架來構成封膠 (Molding) 的半導體元件，此結構常常使用塑性材料封膠。一導線架由金屬帶狀物(metal ribbon)構成，且具有一槳狀物(paddle)(亦為已知的晶粒槳狀物(die paddle), 晶粒附加標籤(die-attach tab), or 島狀物(island))， 一半導體元件設在該槳狀物上。前述導線架具有複數個導線(Lead) 不與該槳狀物重疊排列。
傳統上，積體電路晶片係使用晶粒結合(die bond)的方式設置在導線架上。前述晶粒結合的製造程序包含很多步驟 : 打線 (wire bond) 、積體電路晶片封膠、切單後測試等等。藉由整合或封裝導線架和其他元件，例如電感或電容，可以製造不同的產品。因為製程容易、成熟且信賴性良好，為目前最主要製程之一。然而，這種傳統製程有很多的缺點，其包含: a. 製程成本高，且須使用模具來完成封膠，因此增加模具開發的成本； b. 設計面積只能平面而缺乏說設計彈性，產品無法縮小。c. 只能封裝成單顆元件，並不具模組化的能力。
因此，本發明提出了一個堆疊架及其製程方法來克服上面提到的缺點。
本發明之一目的係提供一個電性連結堆疊架(stack frame)結構的製造方法，藉由移除一金屬基板的至少一部分，以令該金屬基板形成一具有多個接腳的金屬架(metallic frame)，並在該金屬架上形成一具有電性連結之傳導圖案，藉由該電性連結與該接腳(pin)連接。
本發另一目的係提供一電性連結導線架(lead frame)封裝結構之製造方法。在導線架上形成一傳導圖案用以形成多個電性連結以連接該多個接腳。
本發明再一目的係提供一種具有較佳的散熱和電傳導的特性的金屬架之電性連結堆疊架結構。
為達上述目的，本發明提出一較佳實施係為在金屬架上形成一凹洞，且於凹洞中結合至少一傳導元件，藉由已知的技術，例如打線(wire bond)、金球結合(gold-ball bond)、導線(藉由薄膜製程、印刷製程或電鍍) 或其結合，使傳導元件的輸入/輸出端可以電性連結該傳導層。
此結構可以使用在積體電路封裝。在此封裝結構中，一第一傳導元件主要封入在金屬架中，而不是用塑性材料封膠；且藉由表面黏著技術(SMT) 的技術，在金屬架上放置一第二傳導元件。前述第一傳導元件和第二傳導元件可以是主動元件，例如積體電路晶片(IC chip)、金屬氧化層場效電晶體、絕緣闡雙極電晶體(IGBT)或二極體等等，或是被動元件，例如電阻、電容或電感等等。
第一傳導元件和第二傳導元件直接電性連結至金屬架(或接腳)，所以不需要額外的印刷電路板作為連結用。另外，利用點膠(dispensing)或塗膠(gluing)取代封膠用以保護第一傳導元件。因此，不需要額外的模具開發進而可以節省時間和成本，也較容易設計。因此和在傳統積體電路封裝結構中使用的導線架和封膠比較，本發明的結構可以製作元件間最短的電路路徑，故結構的整體的阻抗降低且電性效率增加。
本發明的另一個較佳實施為另一種電性連結結構，係將前述的製造方法實現在金屬架的上下表面。
本發明也揭露了形成一填充層填入金屬架的至少一空隙，填充層可以是高分子材料層，不僅可以填入金屬架的空隙也可以覆蓋金屬架。因此，在金屬架上也可以圖形化高分子材料層以令傳導層可以接觸高分子材料層。因此，整個製程成本可以降低。
在參閱圖式及接下來的段落所描述之實施方式之後，該技術領域具有通常知識者便可瞭解本發明之其它目的，以及本發明之技術手段及實施態樣。
本發明的詳細說明於隨後描述，這裡所描述的較佳實施例是作為說明和描述的用途，並非用來限定本發明之範圍。
本發明揭露一種堆疊架(stack frame)的製造方法。堆疊架係指一框架，該框架上面係可結合某物，並經由這樣的結合產生更多的功能。
請參閱第1圖係為一種堆疊架之製造方法，其藉由下列步驟達成，該步驟包含: 步驟11 : 提供一金屬基板； 步驟12 : 藉由移除該金屬基板的一個或多個部分，令該金屬基板形成一具有多個接腳(pin)的金屬架(metallic frame)； 步驟13 : 在該金屬架上形成一具有電性連結之傳導圖案，並藉由該電性連結與該接腳連接。 在步驟 11中，金屬基板可以由任何適當的材料製成，例如金屬材料。金屬材料包含銅、銀、錫或其結合，但並不侷限。 在步驟 12中，移除金屬基板的一個或多個部分以令該金屬基板形成一具有多個接腳的金屬架。所述的金屬架具有複數個接腳作為輸入/輸出端，而且在接腳的下方放置有墊片 (pad) 作為外部的電性連結。金屬基板可以是導線架或是任何其他相等的結構。在一具體實施中，金屬架可以無空隙存在或是具有至少一個空隙。金屬架的外觀和形狀係依墊片的佈局(Layout) 而定，且金屬架的接腳經由墊片電性連結至印刷電路板或另一個傳導元件（例如積體電路晶片(IC chip) 、金屬氧化層場效電晶體、絕緣闡雙極電晶體 (IGBT) 、二極體、電阻、扼流線圈 (choke) 或電容等）。 在步驟 13中，藉由已知的技術，例如薄膜製程、印刷製程、電射鑽孔或其結合，在金屬架上形成一傳導圖案，該傳導圖案包含多個電性連結，並藉由該電性連結與前述的接腳連接。在另一具體實施中，該金屬架上亦可形成複數個傳導層構成的傳導圖案。
第2A圖和第2B圖分別為無空隙金屬架31的上視圖以及至少一個空隙33金屬架32的上視圖。具有多個接腳34的金屬架可以有任何適當的外觀和形狀以便用於之後的製程。第2C圖和第2D圖分別為無空隙金屬架31之剖面示意圖以及至少一個空隙33金屬架32之剖面示意圖。關於第2A圖和第2C圖，其中第2C圖中A-A’部分取自沿著在第2A圖中線A-A’。關於第2B圖和第2D圖，其中第2D圖中B-B’部分取自沿著在第2B圖中線B-B’。前述金屬架31、32的較佳結構和製造方法將在下面的實施例中描述。
第一實施例
第3A圖係為無空隙電性連結金屬架結構100之剖面示意圖。在一具體實施中，結構100包含了一無空隙金屬架101、一介電層102和一傳導層103，其中該介電層102配置在金屬架101的上方，該傳導層103形成於介電層102上和填充於介電層102內部的貫穿孔。結構100可以包含任何其他作為電性連結的相等結構，且此結構可以藉由任何適當的製程及任何適當的材料製成。在另一具體實施中，如第3B圖所示，該金屬架101具有一凹洞118，且藉由傳統的技術(例如銀膠119)於凹洞118中結合一傳導元件111 (例如積體電路晶片、金屬氧化層場效電晶體、絕緣闡雙極電晶體、二極體、電阻、扼流線圈或電容)。前述的凹洞118的設置係以不同的形式實現，例如，該凹洞形成在金屬架的內部； 或該凹洞具有一邊和金屬架的一邊對齊； 或該凹洞具有兩邊和金屬架的兩邊對齊。再者，在一具體實施中，前述金屬架係為複數個次金屬架(sub metallic frame)結合構成，然後在該金屬架上形成該凹洞。另外，在一具體實施中，藉由已知的技術，例如打線、金球結合、導線(藉由薄膜製程、印刷製程或電鍍) 或其結合，於該凹洞118中結合至少一傳導元件111，將傳導元件111的輸入/輸出端電性連結於傳導層103。另外，在一具體實施中，傳導元件111的上表面112和金屬架101的上表面113位在同一水平。在另一具體實施中，如第3C圖所示，前述的製造方法係可實現在該金屬架101的上表面113和下表面114，且上述描述的技術特徵也可以適用在第3C圖的結構。
第3D圖係為一個產品結構150之示意圖，其元件與結構大致與第3A圖相同，第3D圖與第3A圖差異在於結構150具有一第一傳導元件105，且在該傳導層103上形成一第一墊片104，以令該傳導元件105放置在第一墊片104上，前述傳導元件105例如為積體電路晶片、金屬氧化層場效電晶體、絕緣闡雙極電晶體、二極體、電阻、扼流線圈或電容等等。一第二墊片106形成在該金屬架101的接腳下方，該第二墊片106可以由任何傳導材料製成，例如錫、鎳或金等等。結構150可以放置在印刷電路板上或是電性連結於另一個傳導元件(未顯示) (例如積體電路晶片、金屬氧化層場效電晶體、絕緣闡雙極電晶體、二極體、電阻、扼流線圈或電容)以便於該第一傳導元件105可以經由一傳導路徑電性連結於印刷電路板或另一個傳導元件(未顯示)。前述傳導路徑的構成包含了第一片墊104、傳導層103、金屬架101 (或接腳) 和第二墊片106。惟要申明者，電性連接方式並不僅侷限於前述方式，其係根據不同種類的產品和金屬架的製程而有不同的電性連接變化。
第二實施例
第4A圖係為有空隙電性連結之金屬架結構200之剖面示意圖。如圖所示該結構200包含：一具有至少一空隙221的金屬架201、一介電層202及一傳導層203。該金屬支架201的至少一空隙221中填入一填充層222。該介電層202設置在金屬架201的上方。該傳導層203形成於介電層202上和填充於介電層202內部的貫穿孔。結構200可以包含任何其他作為電性連結的相等結構，且此結構可以藉由任何適當的製程及材料製成。在另一具體實施中，如第4B圖所示，金屬架201形成有一凹洞218，且藉由習知的技術於凹洞218中(例如銀膠219) 結合一傳導元件211(例如積體電路晶片、金屬氧化層場效電晶體、絕緣闡雙極電晶體、二極體、電阻、扼流線圈或電容)。前述凹洞218係可利用各種不同的方法設置，例如，該凹洞形成在金屬架的內部，或該凹洞具有一邊和金屬架的一邊對齊，或該凹洞具有兩邊和金屬架的兩邊對齊。再者，在一具體實施中，前述金屬架係為複數個次金屬架(sub metallic frame)結合構成，然後在該金屬架上形成該凹洞。在一個具體實施中，藉由已知的技術，例如打線、金球結合、導線(藉由薄膜製程、印刷製程或電鍍) 或其結合，於該凹洞218中結合至少一傳導元件211，並令該傳導元件211的輸入/輸出端電性連結該傳導層203。在一具體實施中，該傳導元件211的上表面212和金屬架201的上表面213位在同一水平。在另一具體實施中，如第4C圖所示，前述的製造方法係可實現在該金屬架201的上表面213和下表面214。
請復參閱第3A圖，其與第4A圖的差異在於該第3A圖結構100係為無空隙存在的金屬架結構100； 第4A圖係為具有至少一空隙221之金屬架結構200，此空隙221可以被填充層222所填充。在一具體實施中，該填充層222可以填入金屬架201的至少一空隙221而且覆蓋金屬架201。前述填充層222包含任何適當的材料，例如高分子材料等，所述的高分子材料包含了光阻。
在一具體實施中，金屬架201下方具有一支撐層(未顯示)，例如聚硫亞氨膜(PI film)，該支撐層可以支撐填充層222。在整個製程的最後部分，該支撐層可以被移除。再者，在另一具體實施中，則不需要該支撐層。
在另一具體實施中，如第4D圖所示，該填充層和介電層可以是同一層223。在一具體實施中，同一層223為高分子材料層(例如光阻或是負光阻)，該高分子材料層不僅可以填充金屬架的空隙也可以藉由一些已知的技術，例如黃光製程、雷射鑽孔或者等等，在金屬架上圖形化以便於傳導層203可以接觸高分子材料層。因此，整個製程成本可以降低。此外，前面第4B圖和第4D圖描述的技術特徵也可以適用在第4C圖的結構。
如第4E圖所示，為另一個結構250之示意圖，如圖所示該結構250具有一第一傳導元件205在第4A圖的結構200上。該第一墊片204係形成在傳導層203上以令該第一傳導元件205 (例如積體電路晶片、金屬氧化層場效電晶體、絕緣闡雙極電晶體、二極體、電阻、扼流線圈或電容) 設置在該第一墊片204上。該第二墊片206係形成在金屬架201的接腳下方，該第二墊片206可以由任何傳導材料製成，例如錫、鎳或金等等。結構250可以設置在印刷電路板上或是電性連結於另一個傳導元件 (未顯示) (例如積體電路晶片、金屬氧化層場效電晶體、絕緣闡雙極電晶體、二極體、電阻、扼流線圈或電容) 以使第一傳導元件205經由一傳導路徑電性連結於印刷電路板或另一個傳導元件 (未顯示) 。前述的傳導路徑的構成係包含：第一墊片204、傳導層203、金屬架201(或接腳)和第二墊片206。惟要申明者，電性連接方式並不僅侷限於前述，其係根據不同種類的產品和金屬架的製程而有不同的變化。
下面的實施例揭露了一種封裝結構及其製造方法。在這個實施例中，金屬架是一個導線架(lead frame)，而且導線架為此封裝結構的主要組成要素。
第三實施例
第5A圖係為封裝結構300的剖面示意圖。如圖所示該封裝結構300包含了一導線架301、一填充層306、一第一傳導元件304、一傳導圖案312、一保護層311、一傳導墊313和至少一第二傳導元件314。該導線架301具有複數接腳315作為輸入/輸出端，而且墊片318放置在接腳315的下方作為外部的電性連結。且導線架301的外觀和形狀係依墊片的佈局 (layout) 而定，結構300的接腳315經由墊片318電性連結至印刷電路板或另一個傳導元件 (未顯示) ，例如積體電路晶片、金屬氧化層場效電晶體、絕緣闡雙極電晶體、二極體、電阻、扼流線圈或電容等。在一具體實施中，該導線架301係為無空隙存在或具有至少一個空隙。前述的結構300可以包含作為封裝結構的任何其他的相等結構，且此結構可以藉由任何適當的製程及任何適當的材料製成。前述導線架301可以由銀、銅、錫或其結合製成。藉由已知的技術，例如薄膜製程、印刷製程、雷射鑽孔或其結合，在導線架301上形成該傳導圖案312。該傳導圖案包含多個電性連結，並藉由該等電性連結與前述的接腳315連接。在另一具體實施中，該導線架301上亦可形成複數個傳導層構成的傳導圖案。
導線架的結構係為有空隙的結構，或為無空隙的結構。這兩種結構的差異僅在於空隙的有無。后述描述的較佳結構及製造方法係有關於具有至少一空隙之導線架之薄膜製程。
第5B圖至第5H圖係為製造該封裝結構300的剖面示意圖。
如第5B圖所示，在具有至少一空隙302的導線架301形成一凹洞303。該凹洞303可用已知的方法形成，例如蝕刻或表面粗化。且該凹洞303係可以許多不同的方式設置，例如，該凹洞形成在導線架的內部；或凹洞具有一邊和導線架的一邊對齊； 或凹洞具有兩邊和導線架的兩邊對齊。再者，在一具體實施中，前述的導線架係為複數個次導線架(sub lead frame)結合構成，然後在該次導線架上形成該凹洞。
接著，如第5C圖所示，係可將至少一傳導元件304結合在該凹洞303中，並藉由已知的技術(例如銀膠305) 於凹洞303中結合一第一傳導元件304，例如積體電路晶片、金屬氧化層場效電晶體、絕緣闡雙極電晶體或二極體。在一具體實施中，至少一第一傳導元件結合於該凹洞303中。
接著，如第5D圖所示，填充層306填入導線架301的至少一空隙302。在一個實施範例中，填充層306可以填入導線架301的至少一空隙302而且覆蓋導線架301。一支撐層（例如聚硫亞氨膜(PI film)）設置在導線架301的下方，用以支撐填充層306。在整個製程的最後部分，該支撐層可以被移除。前述填充層306包含任何適當的材料，例如高分子材料等等，該高分子材料包含了光阻。在一具體實施中，該支撐層是不必要的。在一具體實施中，該填充層306是一個高分子材料層(例如光阻或負光阻)，該高分子材料層不僅可以填充該導線架301的空隙302中，也可以藉由一些已知的技術，例如黃光製程、雷射鑽孔等等，在導線架301上圖形化使得傳導圖案312可以接觸高分子材料層。
請參閱第5E圖，藉由一些已知的技術，例如黃光製程、雷射鑽孔等等，圖形化一高分子材料層(例如光阻或負光阻)使露出第一傳導元件304的輸入/輸出端。接著在導線架301上形成傳導圖案312，傳導圖案312將敘述於後。
接著如第5F圖及第5Ｉ圖所示，濺鍍一薄銅層308於填充層306、部分導線架的接腳315以及第一傳導元件304的輸入/輸出端之上。該薄銅層308和一厚銅層310（如第5I圖所示）結合成一傳導圖案312（如第5A圖所示）而完成兩組電性連結。第一組電性連結係連結部份導線架的接腳315和第一傳導元件304的輸入/輸出端。第二組電性連結係連結第二傳導元件314（如第5A圖所示）和第一傳導元件304的輸入/輸出端。薄銅層308用來接觸第一傳導元件304的輸入/輸出端，減少第一傳導元件304的輸入/輸出端與傳導圖案312間的電阻。
請繼續參閱第5F圖及第5I圖，在部份的薄銅層308上圖形化一光阻層309(例如正光阻)，使得其餘部份的薄銅層308裸露出來。然後使用已知的方法，例如電鍍法，形成一厚銅層310於裸露出的薄銅層308之上。因此，一薄銅層308和一厚銅層310（在第5I圖顯示）結合成一傳導圖案312（如第5A圖所示）而完成上述兩個組電性連結。
在一具體實施中，第一傳導元件304的輸入/輸出端可以藉由已知的技術，例如打線、金球結合、導線(藉由薄膜製程、印刷製程或電鍍形成) 或其結合，電性連結於傳導圖案312（如第5A圖所示）。第5G圖及第5H圖說明了藉由打線316或金球結合317的方式而形成在第一傳導元件304的輸入/輸出端與傳導圖案312（如第5A圖所示）之間電性連結。
接著，如第5J圖及第5A圖所示，移除了光阻層309。在一具體實施中，該厚銅層310可以被薄化成適當厚度。然後，選擇性地圖形化一保護層311使部份傳導圖案312露出，並在露出的傳導圖案312上藉由已知的製程例如印刷、銲接等，形成第一墊片313用以連結第二傳導元件314（例如扼流線圈、電容或電阻等）。然後在導線架301之下形成第二墊片318用以進一步連結印刷電路板，該第二墊片318可由任何導電的材料組成，例如錫、鎳/銅合金等等。第5A圖係為本發明具體實施例之產品結構300。
第5K圖及第5L圖係為第5A圖產品結構300的上視圖及下視圖。同時參考第5A圖及第5K圖，第5A圖的C-C’部份係沿著5K圖的線C-C’而來。同時參考第5A圖及第5L圖，第5A圖的C-C’部份係沿著5L圖的C-C’而來。如第5K圖所示，產品結構300的上視圖主要包含第5A圖中的導線架301和第二傳導元件314。如第5L圖所示，產品結構300的下視圖主要包含第5A圖中的導線架301和第二墊片318。第一傳導元件304(未顯示) 埋置在產品結構300中。惟要申明者，電性連接方式並不僅侷限於前述，其係根據不同種類的產品和導線架的製程而有不同的變化
從上述實施例描述而知本發明的結構和製造方法可以提供很多的優點，包含： 1. 金屬架由金屬構成且其有較佳的散熱和電傳導的特性。 2. 在金屬架上形成的凹洞以及使用已知的技術形成傳導圖案，例如薄膜製程、印刷製程或電鍍，可以做出小尺寸的堆疊結構用以電性連結其他的傳導元件。 3. 多方面的應用，包含主動元件，例如積體電路晶片、金屬氧化層場效電晶體、絕緣闡雙極電晶體或二極體，以及被動元件，例如電阻、電感或電感。
雖然本發明以前述之較佳實施例揭露如上，然其並非用以限定本發明，任何熟習相像技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準。
11 ～13．．．步驟
31．．．無空隙金屬架
32．．．有空隙金屬架
33、221、302．．．空隙
34、315．．．接腳
100．．．無空隙電性連結金屬架結構
150、250．．．產品結構
200．．．有空隙電性連結金屬架結構
300．．．封裝結構
101、201．．．金屬架
102、202．．．介電層
103、203．．．傳導層
104、204．．．第一墊片
106、206、318．．．第二墊片
112、212．．．傳導元件上表面
113、213．．．金屬架上表面
114、214．．．金屬架下表面
118、218、303．．．凹洞
119、219、305．．．銀膠
111、105、211、205、304、314．．．傳導元件
150、250．．．產品結構
222、306．．．填充層
300．．．封裝結構
301．．．導線架
308．．．薄銅層
309．．．光阻層
310．．．厚銅層
311．．．保護層
312．．．傳導圖案
313．．．傳導墊
316．．．打線
317．．．金球結合
第1圖為一種製造電性連結堆結構的方法製程程序圖； 第2A圖為無空隙之金屬架的上視圖； 第2B圖為具有至少一空隙之金屬架的上視圖； 第2C圖係為無空隙之金屬架的剖面示意圖； 第2D圖 係為具有至少一空隙之金屬架的剖面示意圖； 第3A圖係為無空隙電性連結金屬架結構之剖面示意圖； 第3B圖係為在無空隙電性連結金屬架結構中具有傳導元件結合於一凹泂之剖面示意圖； 第3C圖係為本發明之製造方法應用在無空隙電性連結金屬架結構之剖面示意圖； 第3D圖係為一產品結構，此產品結構具有至少一第一傳導元件形成在第3A圖的結構上； 第4A圖係為具有至少一空隙之電性連結金屬架結構的剖面示意圖； 第4B圖係為具有至少一空隙之電性連結金屬架結構具有一傳導元件結合於一凹泂的剖面示意圖； 第4C圖係為本發明之製造方法應用在具有一空隙電性連結金屬架結構的上、下表面之剖面示意圖； 第4D圖係為另一個具有至少一空隙之電性連結金屬架結構的剖面示意圖； 第4E圖係為說明產品結構，此產品結構具有至少一第一傳導元件在第4A圖的結構上之示意圖； 第5A圖係為發明實施例封裝結構的剖面示意圖； 第5B圖到第5J圖係為製造本發明封裝結構的製程程序示意圖； 第5K圖係為第5A圖封裝結構之上視圖； 第5L圖係為第5A圖封裝結構之下視圖。

Claims (21)

  1. 一種封裝結構，包含：一導線架，具有複數個由金屬製成之金屬區塊，其中每兩個相鄰的金屬區塊之間具有空隙，其中每兩個相鄰的金屬區塊之間不具有傳導元件；一絕緣層設置在所述複數個金屬區塊上並延伸填入所述空隙，其中至少一導孔設置在所述絕緣層中；以及至少一傳導圖案層，設置在所述絕緣層上方，其中所述至少一傳導圖案層包含一傳導圖案，所述傳導圖案通過所述至少一導孔電性連結所述導線架。
  2. 如申請專利範圍第1項所述之封裝結構，更包含一第一傳導元件，設置在該導線架上，所述傳導圖案電性連結所述第一傳導元件之一第一端子至所述導線架。
  3. 如申請專利範圍第2項所述之封裝結構，其中該第一傳導元件包含一金屬氧化層場效電晶體(MOSFET)之積體電路。
  4. 如申請專利範圍第1項所述之封裝結構，更包含一第二傳導元件，設置在所述至少一傳導圖案層之上方，且該至少一傳導圖案層電性連結該第二傳導元件。
  5. 一種封裝結構，包含：一導線架，具有複數個由金屬製成之金屬區塊，其中每兩個相鄰的金屬區塊之間具有空隙；一絕緣層設置在所述複數個金屬區塊上並延伸填入所述空隙，其中至少一導孔設置在所述絕緣層中；以及至少一傳導圖案層，設置在所述絕緣層上方，其中所述至少一傳導圖案層包含一傳導圖案，所述複數個金屬區塊中之一第一金屬區塊被使用為一第一接腳，所述傳導圖案通過所述至少一導孔電性連結所述第一接腳之上表面，所述第一接腳之下表面，用以電性連結一外部電路。
  6. 一種封裝結構，包含：一導線架，具有複數個由金屬製成之金屬區塊，其中每兩個相鄰的金屬區塊之間具有被絕緣材料所填充之空隙；一凹洞，形成於該導線架中；一第一傳導元件，設置於該凹洞內；一絕緣層設置在所述複數個金屬區塊與該第一傳導元件之上方，其中至少一導孔設置在所述絕緣層中；以及至少一傳導圖案層，設置在所述絕緣層上方，其中所述至少一傳導圖案層包含一傳導圖案，其中所述傳導圖案通過所述至少一導孔電性連結所述第一傳導元件之一第一端子至所述導線架。
  7. 如申請專利範圍第6項所述之封裝結構，其中該第一傳導元件包含一金屬氧化層場效電晶體之積體電路。
  8. 如申請專利範圍第6項所述之封裝結構，更包含一第二傳導元件，設置在所述至少一傳導圖案層之上方，且該至少一傳導圖案層電性連結該第二傳導元件的一第二端子。
  9. 如申請專利範圍第6項所述之封裝結構，所述第一傳導元件之該第一端子設置在所述第一傳導元件之上表面，所述第一傳導元件之上表面與所述導線架之上表面實質上共平面。
  10. 一種封裝結構，包含：一導線架，具有複數個由金屬製成之金屬區塊，其中每兩個相鄰的金屬區塊之間具有一空隙；一凹洞，形成於該導線架之一第一金屬區塊中；一第一傳導元件，設置在該凹洞內；一絕緣層設置在所述複數個金屬區塊與該第一傳導元件之上方並延伸填入所述空隙，其中至少一導孔設置在所述絕緣層中；以及至少一傳導圖案層，設置在所述絕緣層上方，其中所述至少一傳導圖案層包含一傳導圖案，其中所述傳導圖案通過所述至少一導孔電性連結所述第一傳導元件之一第一端子至所述複數個金屬區塊中之一第二金屬區塊。
  11. 如申請專利範圍第10項所述之封裝結構，其中該第一傳導元件包含一金屬氧化層場效電晶體之積體電路。
  12. 如申請專利範圍第10項所述之封裝結構，更包含一第二傳導元件，設置在所述至少一傳導圖案層之上方，且該至少一傳導圖案層電性連結該第二傳導元件的一第二端子。
  13. 如申請專利範圍第10項所述之封裝結構，所述第一傳導元件之該第一端子設置在所述第一傳導元件之上表面，所述第一傳導元件之上表面與所述導線架之上表面實質上共平面。
  14. 一種封裝結構之製造方法，包含：形成複數個金屬區塊，其中每兩個相鄰的金屬區塊之間具有空隙，其中每兩個相鄰的金屬區塊之間不具有傳導元件；設置一絕緣層在所述複數個金屬區塊上並延伸填入所述空隙，其中至少一導孔設置在所述絕緣層中；以及設置至少一傳導圖案層在所述絕緣層上方，其中所述至少一傳導圖案層包含一傳導圖案，其中所述傳導圖案通過所述至少一導孔電性連結所述第一傳導元件之一第一端子至所述複數個金屬區塊中之一金屬區塊。
  15. 如申請專利範圍第14項所述之方法，更包含設置一第二傳導元件在所述至少一傳導圖案層之上方，其中該至少一傳導圖案層電性連結該第二傳導元件的一第二端子。
  16. 一種封裝結構之製造方法，包含：提供複數個金屬區塊，其中每兩個相鄰的金屬區塊之間具有一空隙；設置一絕緣層在所述複數個金屬區塊上並延伸以填入所述空隙，其中至少一導孔設置在所述絕緣層中；以及設置至少一傳導圖案層在所述絕緣層上方，所述至少一傳導圖案層包含一傳導圖案，其中所述複數個金屬區塊中之一第一金屬區塊被使用為一第一接腳，所述傳導圖案通過所述至少一導孔電性連結所述第一接腳之上表面，所述第一接腳之下表面，用以電性連結一外部電路。
  17. 如申請專利範圍第16項所述之方法，更包含設置一第二傳導元件在所述至少一傳導圖案層之上方，其中該至少一傳導圖案層電性連結該第二傳導元件。
  18. 一種封裝結構之製造方法，包含：將一金屬基板移除多個部分以形成複數個金屬區塊，其中每兩個相鄰的金屬區塊之間具有一空隙；設置一絕緣層在所述複數個金屬區塊上並延伸以填入所述空隙，其中至少一導孔設置在所述絕緣層中；以及設置至少一傳導圖案層在所述絕緣層上方，所述至少一傳導圖案層包含一傳導圖案，所述傳導圖案通過所述至少一導孔電性連結所述複數個金屬區塊中之一金屬區塊。
  19. 如申請專利範圍第18項所述之方法，更包含設置一第二傳導元件在所述至少一傳導圖案層之上方，其中該至少一傳導圖案層電性連結該第二傳導元件。
  20. 一種封裝結構之製造方法，包含：提供複數個金屬區塊，其中每兩個相鄰的金屬區塊之間具有一空隙；形成一凹洞在該導線架之一第一金屬區塊中；設置一第一傳導元件在該凹洞內；設置一絕緣層在所述複數個金屬區塊與該第一傳導元件之上方並延伸填入所述空隙，其中至少一導孔設置在所述絕緣層中；以及設置至少一傳導圖案層在所述絕緣層上方，其中所述至少一傳導圖案層包含一傳導圖案，其中所述傳導圖案通過所述至少一導孔電性連結所述第一傳導元件之一第一端子至所述複數個金屬區塊中之一第二金屬區塊。
  21. 一種封裝結構之製造方法，包含：將一金屬基板移除多個部分以形成複數個金屬區塊，其中每兩個相鄰的金屬區塊之間具有一空隙；形成一凹洞在該導線架之一第一金屬區塊中；設置一第一傳導元件，在該凹洞內；設置一絕緣層在所述複數個金屬區塊與該第一傳導元件之上方並延伸填入所述空隙，其中至少一導孔設置在所述絕緣層中；以及設置至少一傳導圖案層在所述絕緣層上方，其中所述至少一傳導圖案層包含一傳導圖案，其中所述傳導圖案通過所述至少一導孔電性連結所述第一傳導元件之一第一端子至所述複數個金屬區塊中之一第二金屬區塊。
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US20090283895A1 (en) * 2006-11-06 2009-11-19 Nec Corporation Semiconductor device and method for manufacturing the same

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