CN102842557B - 一种封装结构及其制造方法 - Google Patents

一种封装结构及其制造方法 Download PDF

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Publication number
CN102842557B
CN102842557B CN201210209819.XA CN201210209819A CN102842557B CN 102842557 B CN102842557 B CN 102842557B CN 201210209819 A CN201210209819 A CN 201210209819A CN 102842557 B CN102842557 B CN 102842557B
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transport element
lead frame
layer
conductive pattern
metal frame
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CN102842557A (zh
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吕保儒
陈大容
林逸程
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Qiankun Science and Technology Co Ltd
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Qiankun Science and Technology Co Ltd
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Abstract

一种在金属架上形成传导图案的电性连结堆迭架的制造方法及具有该金属架的封装结构。在一具体实施中，该电性连结堆迭架是在金属架形成一凹洞以及于此凹洞中结合传导元件的方法制作。在另一具体实施中，该电性连结堆迭架是在一导线架的上表面或下表面或上下表面分别形成该传导图案。该封装结构具有使用该方法的导线架。

Description

一种封装结构及其制造方法
技术领域
本发明涉及一种封装结构，特别涉及一种电性连结金属架的制造方法与具有该金属架的封装结构。
背景技术
导线架(leadframe)是一种被应用在集成电路(IC)封装的材料，其具有不同的型式，例如四边引脚扁平式封装(QFP)、薄小外型封装(TSOP)、小外型晶体管(SOT)或J型引脚小外型封装(SOJ)。藉由组装和互相连结半导体元件至导线架来构成封胶(molding)的半导体元件，此结构常常使用塑性材料封胶。导线架由金属带状物(metalribbon)构成，且具有桨状物(paddle)(亦为已知的晶粒桨状物(diepaddle),晶粒附加标签(die-attachtab),or岛状物(island))，半导体元件设在该桨状物上。前述导线架具有多个导线(lead)不与该桨状物重迭排列。
传统上，集成电路晶片是使用晶粒结合(diebond)的方式设置在导线架上。前述晶粒结合的制造程序包含很多步骤：打线(wirebond)、集成电路晶片封胶、切单后测试等等。藉由整合或封装导线架和其他元件，例如电感或电容，可以制造不同的产品。因为制程容易、成熟且信赖性良好，为目前最主要制程之一。然而，这种传统制程有很多的缺点，其包含：a.制程成本高，且须使用模具来完成封胶，因此增加模具开发的成本;b.设计面积只能平面而缺乏说设计弹性，产品无法缩小。c.只能封装成单颗元件，并不具模块化的能力。
因此，本发明提出了一个堆迭架及其制程方法来克服上面提到的缺点。
发明内容
本发明的目的在于提供一个电性连结堆迭架(stackframe)结构的制造方法，藉由移除金属基板的至少一部分，以令该金属基板形成具有多个引脚的金属架(metallicframe)，并在该金属架上形成具有电性连结的传导图案，藉由该电性连结与该引脚(pin)连接。
本发明另一目的在于提供一种电性连结导线架(leadframe)封装结构的制造方法。在导线架上形成传导图案用以形成多个电性连结以连接该多个引脚。
本发明再一目的是提供一种具有较佳的散热和电传导的特性的金属架的电性连结堆迭架结构。
为达上述目的，本发明提出一较佳实施，在金属架上形成一凹洞，且于凹洞中结合至少一传导元件，藉由已知的技术，例如打线(wirebond)、金球结合(gold-ballbond)、导线(藉由薄膜制程、印刷制程或电镀)或其结合，使传导元件的输入/输出端可以电性连结该传导层。
此结构可以使用在集成电路封装。在此封装结构中，第一传导元件主要封入在金属架中，而不是用塑性材料封胶;且藉由表面粘着技术(SMT)的技术，在金属架上放置第二传导元件。前述第一传导元件和第二传导元件可以是主动元件，例如集成电路晶片(ICchip)、金属氧化层场效电晶体、绝缘阐双极电晶体(IGBT)或二极体等等，或是被动元件，例如电阻、电容或电感等等。
第一传导元件和第二传导元件直接电性连结至金属架(或引脚)，所以不需要额外的印刷电路板作为连结用。另外，利用点胶(dispensing)或涂胶(gluing)取代封胶用以保护第一传导元件。因此，不需要额外的模具开发进而可以节省时间和成本，也较容易设计。因此和在传统集成电路封装结构中使用的导线架和封胶比较，本发明的结构可以制作元件间最短的电路路径，故结构的整体的阻抗降低且电性效率增加。
本发明的另一个较佳实施为另一种电性连结结构，是将前述的制造方法实现在金属架的上下表面。
本发明也公开了形成一填充层填入金属架的至少一空隙，填充层可以是高分子材料层，不仅可以填入金属架的空隙也可以覆盖金属架。因此，在金属架上也可以图形化高分子材料层以令传导层可以接触高分子材料层。因此，整个制程成本可以降低。
本发明的有益效果在于，本发明提出的电性连接堆迭架有较佳的散热和电传导的特性。另外，在金属架上形成的凹洞以及使用已知的技术形成传导图案，例如薄膜制程、印刷制程或电镀，可以做出小尺寸的堆迭结构用以电性连结其他的传导元件，具有多方面的应用。
附图说明
图1为一种制造电性连结堆结构的方法制程程序图；
图2A为无空隙的金属架的仰视图；
图2B为具有至少一空隙的金属架的仰视图；
图2C为无空隙的金属架的剖面示意图；
图2D为具有至少一空隙的金属架的剖面示意图；
图3A为无空隙电性连结金属架结构的剖面示意图；
图3B为在无空隙电性连结金属架结构中具有传导元件结合于凹洞的剖面示意图；
图3C为本发明的制造方法应用在无空隙电性连结金属架结构的剖面示意图；
图3D为一产品结构，此产品结构具有至少一第一传导元件形成在第3A图的结构上；
图4A为具有至少一空隙的电性连结金属架结构的剖面示意图；
图4B为具有至少一空隙的电性连结金属架结构具有一传导元件结合于一凹洞的剖面示意图；
图4C为本发明的制造方法应用在具有空隙电性连结金属架结构的上、下表面的剖面示意图；
图4D为另一个具有至少一空隙的电性连结金属架结构的剖面示意图；
图4E为说明产品结构，此产品结构具有至少一第一传导元件在第4A图的结构上的示意图；
图5A为发明实施例封装结构的剖面示意图；
图5B到图5J为制造本发明封装结构的制程程序示意图；
图5K为图5A封装结构的仰视图；
图5L为第5A图封装结构的俯视图。
附图标记说明：11～13-步骤；31-无空隙金属架；32-有空隙金属架；33、221、302-空隙；34、315-引脚；100-无空隙电性连结金属架结构；150、250-产品结构；200-有空隙电性连结金属架结构；300-封装结构；101、201-金属架；102、202-介电层；103、203-传导层；104、204-第一垫片；106、206、318-第二垫片；112、212-传导元件上表面；113、213-金属架上表面；114、214-金属架下表面；118、218、303-凹洞；119、219、305-银胶；111、105、211、205、304、314-传导元件；150、250-产品结构；222、306-填充层；300-封装结构；301-导线架；308-薄铜层；309-光阻层；310-厚铜层；311-保护层；312-传导图案；313-传导垫；316-打线；317-金球结合。
具体实施方式
本发明的详细说明于随后描述，这里所描述的较佳实施例是作为说明和描述的用途，并非用来限定本发明的范围。
本发明公开一种堆迭架(stackframe)的制造方法。堆迭架是指一框架，该框架上面可结合某物，并经由这样的结合产生更多的功能。
请参阅图1为一种堆迭架的制造方法，其通过下列步骤达成，该步骤包含：
步骤11：提供一金属基板；
步骤12：藉由移除该金属基板的一个或多个部分，令该金属基板形成具有多个引脚(pin)的金属架(metallicframe)；
步骤13：在该金属架上形成具有电性连结的传导图案，并藉由该电性连结与该引脚连接。
在步骤11中，金属基板可以由任何适当的材料制成，例如金属材料。金属材料包含铜、银、锡或其结合，但并不局限。
在步骤12中，移除金属基板的一个或多个部分以令该金属基板形成具有多个引脚的金属架。所述的金属架具有多个引脚作为输入/输出端，而且在引脚的下方放置有垫片(pad)作为外部的电性连结。金属基板可以是导线架或是任何其他相等的结构。在具体实施中，金属架可以无空隙存在或是具有至少一个空隙。金属架的外观和形状依垫片的布局(layout)而定，且金属架的引脚经由垫片电性连结至印刷电路板或另一个传导元件（例如集成电路晶片(ICchip)、金属氧化层场效电晶体、绝缘阐双极电晶体(IGBT)、二极体、电阻、扼流线圈(choke)或电容等）。
在步骤13中，利用已知的技术，例如薄膜制程、印刷制程、电射钻孔或其结合，在金属架上形成传导图案，该传导图案包含多个电性连结，并藉由该电性连结与前述的引脚连接。在另一具体实施中，该金属架上亦可形成多个传导层构成的传导图案。
图2A和图2B分别为无空隙金属架31的仰视图以及至少一个空隙33金属架32的仰视图。具有多个引脚34的金属架可以有任何适当的外观和形状以便用于之后的制程。图2C和图2D分别为无空隙金属架31的剖面示意图以及至少一个空隙33金属架32的剖面示意图。关于图2A和图2C，其中图2C中A-A’部分取自沿着在图2A中线A-A’。关于图2B和图2D，其中图2D中B-B’部分取自沿着在图2B中线B-B’。前述金属架31、32的较佳结构和制造方法将在下面的实施例中描述。
第一实施例
图3A为无空隙电性连结金属架结构100的剖面示意图。在一具体实施中，结构100包含了无空隙金属架101、介电层102和传导层103，其中该介电层102配置在金属架101的上方，该传导层103形成于介电层102上和填充于介电层102内部的贯穿孔。结构100可以包含任何其他作为电性连结的相等结构，且此结构可以藉由任何适当的制程及任何适当的材料制成。在另一具体实施中，如图3B所示，该金属架101具有凹洞118，且藉由传统的技术(例如银胶119)于凹洞118中结合传导元件111(例如集成电路晶片、金属氧化层场效电晶体、绝缘阐双极电晶体、二极体、电阻、扼流线圈或电容)。前述的凹洞118的设置以不同的形式实现，例如，该凹洞形成在金属架的内部;或该凹洞具有一边和金属架的一边对齐;或该凹洞具有两边和金属架的两边对齐。再者，在具体实施中，前述金属架为多个次金属架(submetallicframe)结合构成，然后在该金属架上形成该凹洞。另外，在一具体实施中，利用已知的技术，例如打线、金球结合、导线(通过薄膜制程、印刷制程或电镀)或其结合，于该凹洞118中结合至少一传导元件111，将传导元件111的输入/输出端电性连结于传导层103。另外，在一具体实施中，传导元件111的上表面112和金属架101的上表面113位在同一水平。在另一具体实施中，如图3C所示，前述的制造方法可实现在该金属架101的上表面113和下表面114，且上述描述的技术特征也可以适用在第3C图的结构。
图3D为一个产品结构150的示意图，其元件与结构大致与图3A相同，图3D与图3A差异在于结构150具有第一传导元件105，且在该传导层103上形成第一垫片104，以令该传导元件105放置在第一垫片104上，前述传导元件105例如为集成电路晶片、金属氧化层场效电晶体、绝缘阐双极电晶体、二极体、电阻、扼流线圈或电容等等。第二垫片106形成在该金属架101的引脚下方，该第二垫片106可以由任何传导材料制成，例如锡、镍或金等等。结构150可以放置在印刷电路板上或是电性连结于另一个传导元件(未显示)(例如集成电路晶片、金属氧化层场效电晶体、绝缘阐双极电晶体、二极体、电阻、扼流线圈或电容)以便于该第一传导元件105可以经由传导路径电性连结于印刷电路板或另一个传导元件(未显示)。前述传导路径的构成包含了第一片垫104、传导层103、金属架101(或引脚)和第二垫片106。惟要申明者，电性连接方式并不仅局限于前述方式，其根据不同种类的产品和金属架的制程而有不同的电性连接变化。
第二实施例
图4A为有空隙电性连结的金属架结构200的剖面示意图。如图所示该结构200包含：具有至少一空隙221的金属架201、介电层202及传导层203。该金属支架201的至少一空隙221中填入填充层222。该介电层202设置在金属架201的上方。该传导层203形成于介电层202上和填充于介电层202内部的贯穿孔。结构200可以包含任何其他作为电性连结的相等结构，且此结构可以藉由任何适当的制程及材料制成。在另一具体实施中，如图4B所示，金属架201形成有凹洞218，且利用现有的技术于凹洞218中(例如银胶219)结合传导元件211(例如集成电路晶片、金属氧化层场效电晶体、绝缘阐双极电晶体、二极体、电阻、扼流线圈或电容)。前述凹洞218可利用各种不同的方法设置，例如，该凹洞形成在金属架的内部，或该凹洞具有一边和金属架的一边对齐，或该凹洞具有两边和金属架的两边对齐。再者，在具体实施中，前述金属架为多个次金属架(submetallicframe)结合构成，然后在该金属架上形成该凹洞。在一个具体实施中，利用已知的技术，例如打线、金球结合、导线(通过薄膜制程、印刷制程或电镀)或其结合，于该凹洞218中结合至少一传导元件211，并令该传导元件211的输入/输出端电性连结该传导层203。在具体实施中，该传导元件211的上表面212和金属架201的上表面213位在同一水平。在另一具体实施中，如图4C所示，前述的制造方法可实现在该金属架201的上表面213和下表面214。
请再参阅图3A，其与图4A的差异在于图3A结构100为无空隙存在的金属架结构100;图4A为具有至少一空隙221的金属架结构200，此空隙221可以被填充层222所填充。在一具体实施中，该填充层222可以填入金属架201的至少一空隙221而且覆盖金属架201。前述填充层222包含任何适当的材料，例如高分子材料等，所述的高分子材料包含了光阻。
在一具体实施中，金属架201下方具有一支撑层(未显示)，例如聚硫亚氨膜(PIfilm)，该支撑层可以支撑填充层222。在整个制程的最后部分，该支撑层可以被移除。再者，在另一具体实施中，则不需要该支撑层。
在另一具体实施中，如图4D所示，该填充层和介电层可以是同一层223。在一具体实施中，同一层223为高分子材料层(例如光阻或是负光阻)，该高分子材料层不仅可以填充金属架的空隙也可以藉由一些已知的技术，例如黄光制程、雷射钻孔或者等等，在金属架上图形化以便于传导层203可以接触高分子材料层。因此，整个制程成本可以降低。此外，前面图4B和图4D描述的技术特征也可以适用在图4C的结构。
如图4E所示，为另一个结构250的示意图，如图所示该结构250具有第一传导元件205在图4A的结构200上。该第一垫片204形成在传导层203上以令该第一传导元件205(例如集成电路晶片、金属氧化层场效电晶体、绝缘阐双极电晶体、二极体、电阻、扼流线圈或电容)设置在该第一垫片204上。该第二垫片206形成在金属架201的引脚下方，该第二垫片206可以由任何传导材料制成，例如锡、镍或金等等。结构250可以设置在印刷电路板上或是电性连结于另一个传导元件(未显示)(例如集成电路晶片、金属氧化层场效电晶体、绝缘阐双极电晶体、二极体、电阻、扼流线圈或电容)以使第一传导元件205经由传导路径电性连结于印刷电路板或另一个传导元件(未显示)。前述的传导路径的构成包含：第一垫片204、传导层203、金属架201(或引脚)和第二垫片206。惟要申明者，电性连接方式并不仅局限于前述，其是根据不同种类的产品和金属架的制程而有不同的变化。
下面的实施例公开了一种封装结构及其制造方法。在这个实施例中，金属架是一个导线架(leadframe)，而且导线架为此封装结构的主要组成要素。
第三实施例
图5A为封装结构300的剖面示意图。如图所示该封装结构300包含导线架301、填充层306、第一传导元件304、传导图案312、保护层311、传导垫313和至少一第二传导元件314。该导线架301具有多引脚315作为输入/输出端，而且垫片318放置在引脚315的下方作为外部的电性连结。且导线架301的外观和形状依垫片的布局(layout)而定，结构300的引脚315经由垫片318电性连结至印刷电路板或另一个传导元件(未显示)，例如集成电路晶片、金属氧化层场效电晶体、绝缘阐双极三极管、二极管、电阻、扼流线圈或电容等。在一具体实施中，该导线架301为无空隙存在或具有至少一个空隙。前述的结构300可以包含作为封装结构的任何其他的相等结构，且此结构可以藉由任何适当的制程及任何适当的材料制成。前述导线架301可以由银、铜、锡或其结合制成。藉由已知的技术，例如薄膜制程、印刷制程、雷射钻孔或其结合，在导线架301上形成该传导图案312。该传导图案包含多个电性连结，并藉由该等电性连结与前述的引脚315连接。在另一具体实施中，该导线架301上亦可形成多个传导层构成的传导图案。
导线架的结构为有空隙的结构，或为无空隙的结构。这两种结构的差异仅在于空隙的有无。后述描述的较佳结构及制造方法是关于具有至少一空隙的导线架之薄膜制程。
图5B至图5H为制造该封装结构300的剖面示意图。
如图5B所示，在具有至少一空隙302的导线架301形成一凹洞303。该凹洞303可用已知的方法形成，例如蚀刻或表面粗化。且该凹洞303可以许多不同的方式设置，例如，该凹洞形成在导线架的内部;或凹洞具有一边和导线架的一边对齐;或凹洞具有两边和导线架的两边对齐。再者，在一具体实施中，前述的导线架系为多个次导线架(subleadframe)结合构成，然后在该次导线架上形成该凹洞。
接着，如图5C所示，可将至少一传导元件304结合在该凹洞303中，并藉由已知的技术(例如银胶305)于凹洞303中结合第一传导元件304，例如集成电路晶片、金属氧化层场效三极管、绝缘阐双极三极管或二极管。在一具体实施中，至少一第一传导元件结合于该凹洞303中。
接着，如图5D所示，填充层306填入导线架301的至少一空隙302。在一个实施范例中，填充层306可以填入导线架301的至少一空隙302而且覆盖导线架301。一支撑层（例如聚硫亚氨膜(PIfilm)）设置在导线架301的下方，用以支撑填充层306。在整个制程的最后部分，该支撑层可以被移除。前述填充层306包含任何适当的材料，例如高分子材料等等，该高分子材料包含了光阻。在一具体实施中，该支撑层是不必要的。在一具体实施中，该填充层306是一个高分子材料层(例如光阻或负光阻)，该高分子材料层不仅可以填充该导线架301的空隙302中，也可以藉由一些已知的技术，例如黄光制程、雷射钻孔等等，在导线架301上图形化使得传导图案312可以接触高分子材料层。
请参阅图5E，藉由一些已知的技术，例如黄光制程、雷射钻孔等等，图形化高分子材料层(例如光阻或负光阻)使露出第一传导元件304的输入/输出端。接着在导线架301上形成传导图案312，传导图案312将叙述于后。
接着如图5F及图5Ｉ所示，溅镀一薄铜层308于填充层306、部分导线架的引脚315以及第一传导元件304的输入/输出端之上。该薄铜层308和一厚铜层310（如图5I所示）结合成一传导图案312（如图5A所示）而完成两组电性连结。第一组电性连结是连结部份导线架的引脚315和第一传导元件304的输入/输出端。第二组电性连结是连结第二传导元件314（如图5A所示）和第一传导元件304的输入/输出端。薄铜层308用来接触第一传导元件304的输入/输出端，减少第一传导元件304的输入/输出端与传导图案312间的电阻。
请继续参阅图5F及图5I，在部份的薄铜层308上图形化光阻层309(例如正光阻)，使得其余部份的薄铜层308裸露出来。然后使用已知的方法，例如电镀法，形成厚铜层310于裸露出的薄铜层308之上。因此，薄铜层308和厚铜层310（在第5I图显示）结合成传导图案312（如图5A所示）而完成上述两个组电性连结。
在一具体实施中，第一传导元件304的输入/输出端可以藉由已知的技术，例如打线、金球结合、导线(藉由薄膜制程、印刷制程或电镀形成)或其结合，电性连结于传导图案312（如图5A所示）。图5G及图5H说明了藉由打线316或金球结合317的方式而形成在第一传导元件304的输入/输出端与传导图案312（如图5A所示）之间电性连结。
接着，如图5J及图5A所示，移除了光阻层309。在一具体实施中，该厚铜层310可以被薄化成适当厚度。然后，选择性地图形化保护层311使部份传导图案312露出，并在露出的传导图案312上藉由已知的制程例如印刷、焊接等，形成第一垫片313用以连结第二传导元件314（例如扼流线圈、电容或电阻等）。然后在导线架301之下形成第二垫片318用以进一步连结印刷电路板，该第二垫片318可由任何导电的材料组成，例如锡、镍/铜合金等等。图5A为本发明具体实施例的产品结构300。
图5K及图5L为图5A产品结构300的仰视图及下视图。同时参考图5A及图5K，图5A的C-C’部份沿着图5K的线C-C’而来。同时参考图5A及图5L，图5A的C-C’部份沿着5L图的C-C’而来。如图5K所示，产品结构300的仰视图主要包含图5A中的导线架301和第二传导元件314。如图5L所示，产品结构300的下视图主要包含图5A中的导线架301和第二垫片318。第一传导元件304(未显示)埋置在产品结构300中。惟要申明者，电性连接方式并不仅局限于前述，其根据不同种类的产品和导线架的制程而有不同的变化。
从上述实施例描述而知本发明的结构和制造方法可以提供很多的优点，包含：
1.金属架由金属构成且其有较佳的散热和电传导的特性。
2.在金属架上形成的凹洞以及使用已知的技术形成传导图案，例如薄膜制程、印刷制程或电镀，可以做出小尺寸的堆迭结构用以电性连结其他的传导元件。
3.多方面的应用，包含主动元件，例如集成电路芯片、金属氧化层场效三极管、绝缘阐双极三极管或二极管，以及被动元件，例如电阻、电感或电感。
以上说明对本发明而言只是说明性的，而非限制性的，本领域普通技术人员理解，在不脱离以下所附权利要求所限定的精神和范围的情况下，可做出许多修改，变化，或等效，但都将落入本发明的保护范围内。

Claims (22)

1.一种封装结构的制造方法，其特征在于，包含了下列步骤：
a.提供一具有多个引脚的导线架；
b.在该导线架形成一凹洞；
c.在该凹洞放置具有至少一第一输入或输出端的第一传导元件；
d.设置一介电层在所述导线架和所述第一传导元件上，其中至少一导孔设置在该介电层中；以及
e.在该介电层上形成传导图案层，其中该传导图案层延伸至所述至少一导孔中，该传导图案层包含了多个电性连结用以连结该多个引脚及通过所述至少一导孔以连接该第一传导元件的该至少一第一输入或输出端。
2.根据权利要求1所述的方法，其特征在于，进一步包含了下列步骤：
在该传导图案层上形成第一垫片；以及
利用连接该第一垫片与第二传导元件的至少一第二输入或输出端，以连结该第二传导元件至该导线架。
3.根据权利要求1所述的方法，其特征在于，所述导线架具有至少一空隙，且前述步骤e中形成该传导图案层包含了下列步骤：
形成一高分子材料层填入该导线架的该至少一空隙。
4.根据权利要求3所述的方法，其特征在于，于步骤e中形成该传导图案层进一步包含了下列步骤：
在该导线架的下方设置一支撑层用以支撑该高分子材料层。
5.根据权利要求4所述的方法，其特征在于，于步骤e中形成该传导图案层进一步包含了下列步骤：
在该高分子材料层上形成该介电层。
6.根据权利要求4所述的方法，其特征在于，所述支撑层包含聚硫亚氨膜。
7.根据权利要求3所述的方法，其特征在于，所述高分子材料层包含负光阻。
8.根据权利要求4所述的方法，其特征在于，进一步包含了下列步骤：
移除该支撑层；以及
在该导线架下形成第二垫片。
9.根据权利要求1所述的方法，其特征在于，所述第一传导元件包含积体电路晶片、金属氧化层场效电晶体、绝缘阐双极电晶体、二极体、扼流线圈、电容或电阻其中至少任一种。
10.根据权利要求2所述的方法，其特征在于，所述第二传导元件包含积体电路晶片、金属氧化层场效电晶体、绝缘阐双极电晶体、二极体、扼流线圈、电容或电阻其中至少任一种。
11.根据权利要求1所述的方法，其特征在于，所述传导图案层包含金属材料。
12.根据权利要求11所述的方法，其特征在于，所述金属材料包含了铜、银或锡其中至少任一种。
13.一种封装结构，其特征在于，包含：
导线架，具有多个引脚；
凹洞，形成在该导线架中；
第一传导元件，设在该凹洞内，且具有至少一第一输入或输出端，其中该导线架的上表面与所述第一传导元件的上表面实质上位于同一水平；
介电层设置在所述导线架和所述第一传导元件上，其中至少一导孔设置在该介电层中；以及
传导图案层，设在该介电层上，且包含多个电性连结用以连接该多个引脚及通过所述至少一导孔以连接该第一传导元件的该至少一第一输入或输出端。
14.根据权利要求13所述的封装结构，其特征在于，进一步包含具有至少一第二输入或输出端的第二传导元件，且该传导图案层进一步包含第一垫片用以连结该第二传导元件的该至少一第二输入或输出端。
15.根据权利要求13所述的封装结构，其特征在于，进一步包含第二垫片设在该导线架下用以连结印刷电路板。
16.根据权利要求13所述的封装结构，其特征在于，所述导线架具有至少一空隙，以及该封装结构进一步包含一填充层填入该导线架的该至少一空隙。
17.根据权利要求16所述的封装结构，其特征在于，所述填充层包含高分子材料。
18.根据权利要求17所述的封装结构，其特征在于，所述高分子材料包含负光阻。
19.根据权利要求13所述的封装结构，其特征在于，所述第一传导元件包含积体电路晶片、金属氧化层场效电晶体、绝缘阐双极电晶体、二极体、扼流线圈、电容或电阻其中至少任一种。
20.根据权利要求14所述的封装结构，其特征在于，所述第二传导元件包含积体电路晶片、金属氧化层场效电晶体、绝缘阐双极电晶体、二极体、扼流线圈、电容或电阻其中至少任一种。
21.根据权利要求1所述的方法，其特征在于，所述导线架包含多个次导线架。
22.根据权利要求13所述的封装结构，其特征在于，所述导线架包含多个次导线架。
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