1363413 九、發明說明： 【發明所屬之技術領域】 本發明係Μ於-種導線架及具有導線架之封裝構造，特別 是關於-種在晶片承座之底面形成至少二環狀凹槽 及具有導線架之封裝構造。 〜、 【先前技術】1363413 IX. Description of the Invention: [Technical Field] The present invention relates to a lead frame and a package structure having a lead frame, and more particularly to forming at least two annular grooves on the bottom surface of the wafer holder and having The package structure of the lead frame. ~, [prior art]
請參照第1圖所示種·半導體封裝構造，其包含： -導線架1卜-黏著層12、-半導體晶片13、複數條導線14 及-封裝雜I5。料翁η伽麵糾，並具有一晶片 承座hi及複數個引腳m，該晶片承座ln縫矩形^等 引腳112雜排列在該晶片承座⑴的周目。在組裝時，該半 導體晶片I3藉由該黏著層12固定在該晶片承座lu的上表 面，且該半導體晶片13具有複數個焊墊131，該等焊墊m 分別藉由該等導線14電性連接至該等引腳112。最後，利用 該封裝膠體15包覆保護該晶片承座lu、該黏著層12、該半 導體晶片13、該等導、線14以及該等引腳m的一部分藉此 即完成該半導體封裝構造之組裝。屬於此麵半導體封装 構造的實際應用涵蓋雙列直插式封裝(dual Mne package， DIP)、四方扁平封裝(qUad flat package，QFp)、小外形封裝細沾 outline package ’观成j型接腳小外形封裝(smau碰加 J-leaded package，SOJ)等等。 5 1363413 然而，該習用料體封裝構造在實際使用上仍具有下述問 題’例如：請參照第2騎示’某些·半導體封裝構造因應 客戶需求在出廠前必需進行可靠度測試，其中包含—加熱回焊 _〇w_m修麵驟是彻約鮮⑽高溫加熱一段時 間’以進行加速老化之測試目的。然而，經由觀察測試失敗的 半導體封雜造，可發簡本該以承座ηι之底面與封裝膠 體15是結合在-起’但在加熱回焊的測試步驟之後該晶片 承座m之底面與封歸體15之間常會因為導熱性差異及熱 能產生的應力，喊生所分魏_e_laminati〇n)，也就 是會出現-錢16，同_職15之底面可能對應出現 一麵曲表面15卜甚至造痕。結果，大幅降低可靠度測試 的良率。-般而言’當該晶料座⑴下方之封裝膠體15的 厚度愈厚，或者該_賴15整體_餘大，因熱能產生 的應力將愈_ ’齡層現象發生_率也會愈高，也就會產 生該氣隙16聽曲表© 151等永久性缺陷^再者，即使該半 導體封裝構制試結果良好並6 Α廠組裝至電子產品上，該半 導體封裝構造仍可能因為電子產品長期制下造成的高溫影 響，而逐漸產生該氣隙16及翹曲表面151等永久性缺陷，進 而降低該半導體封裝構造之可靠度及使用壽命。 故’有必要提供-轉，餘及具有導驗之聽構造，以 解決習知技術所存在的問題。 6 1363413 . 【發明内容】 本發月之主要目的在於提供_種導線架及具有導線架之封 裝構造，其係在晶片承座之底面形成至少二環狀凹槽以便使 封裝谬體填入該等環狀凹槽内，進而提升可靠度測試良率、膠 體結合強度、封裝可靠度及產品使用壽命。 ’ 為達上述之目的’本發明提供—種具有導線架之封裝構 造’其包含-導線架、至少一半導體晶片、複數條導線及二封 • ^膠體。該導線架包含一晶片承座及複數個引腳。該晶片承座 具有頂面及-底面，該底面凹設有至少二環狀凹槽，各該等 環狀凹槽魅賴舰。_丨腳顧繞射胸^承座之 周圍、亥半導體晶片設於該晶片承座之頂面上。各該等導線分 別電性連接該半導體晶片至各該等引腳。該封裝膠體包覆該晶 片承座、該半導體晶片、該等導線以及該等引腳的一部分= =封裝膠體填人該等環狀凹触，以形成至少二環狀卡擎凸 力 本發明另提供一種導線架 Ό raj 〜< 外尔六巴含一晶片承座 及複數個引腳。該晶片承座具有一頂面及一底面，該底面凹設 有至v 一歡凹槽，各辦魏凹槽縣連續雜。該等引 係環繞排列在該晶片承座之周圍。 在本發明之-實施例中，最外圈之該環狀凹槽與該晶片承 座的邊緣之間具有—第—間距，以及任二相鄰該等環狀凹槽之 間具有一第二間距。該第—間距不小於該第二間距。曰 7 在本發明之-實施例中，該第一間距係介於60至100微米 («Π1)之間，及該第二間距係介於6〇至1〇〇微米之間。^ 在本發明之-實施例中’該等環狀凹槽之深度係介於6〇至 100微米之間。 在本發明之-實施例中，該等環狀凹槽之剖面是呈U形、 V形、廣口形(即梯形)或狹口形(即馬蹄形或〇形）。 在本發明之-實施例中，該等環狀凹槽内具有一粗糖面。 在本發明之-實施例中，該等環狀凹槽之深度係相同。 在本發明之-實施例中，該等環狀凹槽之深度及截面積相 對該晶>{承座勤最賴之該職凹齡最關之該環狀凹 槽逐漸變大。 在本發明之一實施例中，該等環狀凹槽之深度及截面積相 對該晶片承座係由最外圈之該環狀凹槽往最關之該環狀凹 槽逐漸變小。 【實施方式】 ，為了讓本發明之上述及其他目的、特徵、優點能更明顯易 懂’下文將特舉本發明較佳實施例，並配合所附圖式，作詳細 說明如下。 口凊參照第3、4及5圖所示，本發明第一實施例之具有導線 架之封裝構造主要包含—導線架2卜—黏著層η、至少一半 體曰日片23、複數條導線24及一封裝膠體乃。該導線架 8 1363413 包含一晶片承座211及複數個引腳212。本發明適用於該晶片 承座211被該封裝膠體25整個包覆的封裝構造，例如：雙列 直插式封裝(dual in-line package，DIP)、四方扁平封裝(quad flat package ’ QFP)、小外形封裝(small outline package，SOP)或 J 型接腳小外形封裝(small outline J-leaded package，SOJ)等等， 但並不限於上述封裝構造之種類。 請再參照第3、4及5圖所示，本發明第一實施例之導線架 鲁 21係由金屬板材沖廢形成該晶片承座211及複數個引腳212 之形狀，該金屬板材可取材自銅、鋁、其他金屬或其合金，本 發明並不限制其材質。再者，該晶片承座211通常概呈矩形， 但亦可為圓形、正多邊形或其他幾何形狀，本發明亦未限制其 形狀。該晶片承座211具有一頂面及一底面。在本發明第一實 施例中，本發明之改良在於該晶片承座211的底面凹設有至少 _ —城凹槽211a ’其製造方式可選自賴(stamping)法，或選 自光阻(ph0t0-resist)顯影搭配侧液_ (etching)的方式。各該 等環狀凹槽2lla係呈連續環狀，其形狀較佳對應於該晶片承 座211的外形，但亦可為不同形狀，例如：由直線或波浪線構 成之圓形、形、三角形、正多邊形或其他多邊形。如第4 圖所示，本實施例仙設置3個料躲_施為例，但 該等環狀_ 211a之數量亦可為2個或2個以上。再者，本 發明可選擇以適當數量的該等環狀凹槽咖儘可能佈滿於該 9 m片承座211之底面’以便使該晶片承座如底面與所有該等 =凹槽2lla内表面的總表面積可達到大於該晶片承座叫 未叹該等被狀凹槽21la時之底面的總表面積約％倍，以提 供更多的表面積結合該封裝膠體25。 凊參照第4及5騎示，在本發明第一實施例中，最外圈 之該環狀凹槽211a與該晶片承座211的邊緣之間具有一第一 間距m，以及任二相鄰該等環狀凹槽2Ua之間具有一第二間 距此。該第-間距m係約介於6〇至1〇〇微米(職)之間該 第二間距D2係约介於60至1〇〇微米之間，及該第一間細 較佳大於該第二間距D2，但亦可選擇等於該第二間距〇2。如 第5圖所示’在本實施例中，各該等環狀凹槽施之剖面是 呈u形’且各料環狀凹槽2Ua之深度係選擇形成相同該 等環狀凹槽之深度係介於6G至1〇()微米之間。 再者，請再參照第3、4及5圖所示，在本發明第一實施例 中’該晶片承座2ΐι之頂面係可藉由該該黏著層η固定該至 少一半導船片23。該黏著層22可選自麟轉或固態黏貼 膠帶，本發職不關其_。依财品需求，料導體晶片 23之數量可為i個或！個以上，及其通常選自石夕晶圓切割而 成之晶>1 ’但本發明並不限制其數量與種類。該半導體晶月 23具有-主動表面(未標示），其上設有複數個焊墊加。該等 引腳犯職·在該晶片承座211之周圍，各該等引腳212 1363413 具有一内引腳部2na及一冰 選自金線，但亦可選自^^啊⑽°該㈣線24較佳 以電性連接該半導體晶片23之 °等導線％分別用 的内⑽部212a。該封裝 通 至該料腳扣 脂)與絕緣填充材(如二氧化__咖環氧樹 發明並不嶋_==轉)谢材料，但本 叫、該賴22哪·該晶片承座 引_的内_2丨23„二^_24_等 =%將填入該等環狀凹槽咖内，以形成至少二環狀 L251 ’其係灯錄合於辦職凹獅a之内表面。 ^再參照第3、4及5嶋，當本鶴—實施例之具有 1之封，構造因應客戶需求在出廠前進行可靠度測試 ，、中通常包含—加熱__。_戦步驟，該步驟利 用約26代的高溫加熱—段時間，以進行加速老化之測試目 的。由於本發明之晶片承座211的底面設有該至少二環狀凹槽 211a能與該封裳膠體2S的至少二環狀卡掣凸部⑸結合在一 起’以增加結合時的有效表面積，故可大幅提高膠體結合強 度因此’經實際觀察，在加熱回焊的測試步驟之後，該等環 狀凹槽211a及環狀卡掣凸部251能有效避免該晶片承座2ιι 之底面與封裝膠體25之間因為導熱性差異及熱能產生的應 力，而產生所謂的分層現象(de-lamination)，也就是能防止出 1363413 現氣隙或Μ曲表面(如第2圖之習用封裝構造所示)等…生缺 陷，因此騎提高可靠度測試良率。特別是，當該晶片承座 如下方之封麵體25的厚度愈厚，或者該封裝膠體^整體 的體積愈大時，因熱能產生的應力將愈明顯，該分層現象發生 的機率也會愈高。此時，利用本發明之環狀凹槽2旧及環狀 卡掣凸部251更能突顯其提升雜可靠度的效果。再者，在該 封裝構造载絲良紐6出歧裝至電子產品上之後，本發 明同樣可聽騎麟造因為電子產品長期㈣下造成的高 溫影響，祕漸產生該氣隙及_表面縣久性缺陷，因此本 發明亦能德該封裝構造峡後之封裝可靠歧產品使 命。 請參照第6、7及8圖所示，本發明第二、第三及第四實施 例的導線纽具有導線架之封裝構造係相似於第3至5圖之本 發明第-實施例卿線架及具有導線架之雜構造，但兩者間 差^之特徵在於：如第6 ®所示，該第二實施例之導線架21 的b曰片承座211係在其底面凹設形成剖面呈v形的至少二環 狀凹槽211a如第7圖所示，該第三實施例之導線架η的晶 ^座211係在其底面凹設形成剖面呈廣口形(即梯形)的至少 ^狀凹槽211a如第8圖所示，該第四實施例之導線架 的晶片承座211係在其底面凹設形成剖面呈狹口形(即馬蹄形 〆形)的至夕一環狀凹槽2lla。上述環狀凹槽I同樣可提 12 1363413 升膠體結合強度、封討靠度及產品使用壽命。Referring to the semiconductor package structure shown in FIG. 1, the lead frame 1 includes an adhesive layer 12, a semiconductor wafer 13, a plurality of wires 14, and a package impurity I5. The material has a wafer holder hi and a plurality of pins m, and the wafer socket ln slit rectangles and the like pins 112 are arranged at the periphery of the wafer holder (1). When assembled, the semiconductor wafer I3 is fixed on the upper surface of the wafer holder lu by the adhesive layer 12, and the semiconductor wafer 13 has a plurality of pads 131, and the pads m are electrically connected by the wires 14 respectively. Connected to the pins 112. Finally, the package holder 15 is used to cover and protect the wafer holder lu, the adhesive layer 12, the semiconductor wafer 13, the conductive lines 14, and a portion of the pins m to complete the assembly of the semiconductor package structure. . The practical applications of this semiconductor package structure include dual MN package (DIP), quad flat package (QFad), small outline package and thin package. Shape package (smau touch J-leaded package, SOJ) and so on. 5 1363413 However, the conventional material package structure still has the following problems in practical use. For example, please refer to the 2nd riding display. Certain semiconductor packaging structures must be tested for reliability before leaving the factory according to customer requirements, including - Heat reflow _ 〇 w_m shaving step is the test purpose of the accelerated aging. However, by observing the failed semiconductor package, it can be simplified that the bottom surface of the socket ηι is combined with the encapsulant 15 but after the test step of heating reflow, the bottom surface of the wafer holder m is Sealed body 15 often because of the difference in thermal conductivity and the stress generated by thermal energy, shouting the points of Wei _e_laminati〇n), that is, there will be - money 16, the bottom of the same _ job 15 may correspond to a curved surface 15 Bu even made marks. As a result, the yield of the reliability test is greatly reduced. - Generally speaking, when the thickness of the encapsulant 15 below the crystal holder (1) is thicker, or the overall thickness of the encapsulation 15 is greater, the stress generated by the thermal energy will be higher. , and the permanent defect such as the air gap 16 can also be generated. Even if the semiconductor package construction test result is good and the assembly is assembled to the electronic product, the semiconductor package structure may still be due to the electronic product. The high temperature effect caused by the long-term system gradually produces permanent defects such as the air gap 16 and the warped surface 151, thereby reducing the reliability and service life of the semiconductor package structure. Therefore, it is necessary to provide - transfer, and a listening structure with a guide to solve the problems of the prior art. 6 1363413 . SUMMARY OF THE INVENTION The main purpose of this month is to provide a lead frame and a package structure having a lead frame, which is formed on the bottom surface of the wafer holder to form at least two annular grooves for filling the package body. In the annular groove, the reliability test yield, colloid bonding strength, package reliability and product service life are improved. For the purposes described above, the present invention provides a package structure having a lead frame that includes a lead frame, at least one semiconductor wafer, a plurality of wires, and a second gel. The leadframe includes a wafer holder and a plurality of pins. The wafer holder has a top surface and a bottom surface, and the bottom surface is recessed with at least two annular grooves, each of the annular grooves. _ 丨 顾 绕 ^ ^ ^ ^ ^ ^ ^ 承 承 承 承 承 承 亥 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体Each of the wires is electrically connected to the semiconductor chip to each of the pins. The encapsulant encapsulates the wafer holder, the semiconductor wafer, the wires, and a portion of the pins == the encapsulant colloids fill the annular recesses to form at least two annular occlusions A lead frame is provided Ό raj ~< The outer samba contains a wafer holder and a plurality of pins. The wafer holder has a top surface and a bottom surface, and the bottom surface is recessed to a v-shaped groove, and each of the Wei-grooves is continuously mixed. The leads are arranged around the wafer holder. In an embodiment of the invention, the annular groove of the outermost ring has a -first spacing between the edge of the wafer holder and a second between the adjacent annular grooves spacing. The first spacing is not less than the second spacing.曰 7 In an embodiment of the invention, the first spacing is between 60 and 100 microns («Π1) and the second spacing is between 6〇 and 1〇〇. ^ In the embodiment of the invention - the annular grooves have a depth between 6 〇 and 100 microns. In the embodiment of the invention, the annular grooves are U-shaped, V-shaped, wide-mouthed (i.e., trapezoidal) or narrow-shaped (i.e., horseshoe or scorpion). In an embodiment of the invention, the annular grooves have a rough side. In the embodiment of the invention, the annular grooves have the same depth. In the embodiment of the present invention, the depth and the cross-sectional area of the annular grooves are gradually increased relative to the crystal groove which is the most relevant to the position of the seat. In one embodiment of the invention, the depth and cross-sectional area of the annular recesses are gradually reduced from the annular recess of the outermost ring to the most annular recess. The above and other objects, features and advantages of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Referring to Figures 3, 4 and 5, the package structure having a lead frame according to the first embodiment of the present invention mainly comprises a lead frame 2 - an adhesive layer η, at least a half body 曰 23, and a plurality of wires 24 And a package of colloids. The lead frame 8 1363413 includes a wafer holder 211 and a plurality of pins 212. The present invention is applicable to a package structure in which the wafer holder 211 is entirely covered by the encapsulant 25, for example, a dual in-line package (DIP), a quad flat package (QFP), A small outline package (SOP) or a small outline J-leaded package (SOJ), etc., but is not limited to the type of the above package structure. Referring to FIG. 3, FIG. 4 and FIG. 5 again, the lead frame of the first embodiment of the present invention is formed by smashing metal sheets to form the wafer holder 211 and a plurality of pins 212. The metal sheet can be obtained. The material is not limited by the present invention from copper, aluminum, other metals or alloys thereof. Moreover, the wafer holder 211 is generally rectangular in shape, but may also be circular, regular polygonal or other geometric shape, and the present invention does not limit its shape. The wafer holder 211 has a top surface and a bottom surface. In a first embodiment of the present invention, the improvement of the present invention is that the bottom surface of the wafer holder 211 is recessed with at least a recess 211a. The manufacturing method may be selected from a stamping method or a photoresist ( Ph0t0-resist) development with side liquid _ (etching) way. Each of the annular grooves 2lla has a continuous annular shape, and its shape preferably corresponds to the outer shape of the wafer holder 211, but may also have different shapes, for example, a circle, a shape, and a triangle formed by straight lines or wavy lines. , regular polygons or other polygons. As shown in Fig. 4, in the present embodiment, three materials are set as examples, but the number of the ring_211a may be two or more. Furthermore, the present invention may alternatively fill the bottom surface of the 9 m piece holder 211 as much as possible with an appropriate number of the annular groove so that the wafer holder is as the bottom surface and all of the grooves = 21a The total surface area of the surface can be greater than about a factor of the total surface area of the bottom surface of the wafer holder without the slanted grooves 21la to provide more surface area for bonding the encapsulant 25. Referring to FIGS. 4 and 5, in the first embodiment of the present invention, the annular groove 211a of the outermost ring and the edge of the wafer holder 211 have a first spacing m, and any two adjacent The annular grooves 2Ua have a second spacing therebetween. The first spacing m is between about 6 〇 and 1 〇〇 micrometer, and the second spacing D2 is between about 60 and 1 〇〇 micrometer, and the first spacing is preferably greater than the first The two spacings D2, but may also be chosen to be equal to the second spacing 〇2. As shown in Fig. 5, in the present embodiment, each of the annular grooves is formed in a U-shape and the depth of each annular groove 2Ua is selected to form the same depth of the annular grooves. The system is between 6G and 1〇() micron. Furthermore, referring to FIGS. 3, 4 and 5, in the first embodiment of the present invention, the top surface of the wafer holder 2 can be fixed to the at least half of the guide boat 23 by the adhesive layer n. . The adhesive layer 22 can be selected from a sling or a solid adhesive tape. According to the demand of the goods, the number of material conductor chips 23 can be i or! More than one, and it is usually selected from the stone wafer dicing > 1 ', but the invention does not limit its number and type. The semiconductor crystal moon 23 has an active surface (not shown) on which a plurality of pads are provided. The pins are in the vicinity of the wafer holder 211. Each of the pins 212 1363413 has an inner lead portion 2na and an ice selected from the gold wire, but may also be selected from the group (^) (10) ° (4) The wire 24 is preferably electrically connected to the inner (10) portion 212a for the wire % of the semiconductor wafer 23 or the like. The package is connected to the material and the insulating filler (such as the oxidized __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The inner 2 丨 23 „ 2 ^ _ 24 _ = % will be filled into the annular groove coffee to form at least two rings L251 'the light is recorded on the inner surface of the lion a. ^ Referring to Figures 3, 4 and 5 again, when the Crane-Example has a seal of 1 and the structure is tested for reliability before leaving the factory according to customer requirements, it usually includes a heating__._戦 step, this step The high temperature heating period of about 26 generations is used for the purpose of accelerated aging. Since the bottom surface of the wafer holder 211 of the present invention is provided with the at least two annular grooves 211a and at least two rings of the sealing body 2S The tabs (5) are joined together to increase the effective surface area at the time of bonding, so that the colloidal bonding strength can be greatly improved. Therefore, after actual observation, after the test step of heating reflow, the annular grooves 211a and the ring shape are formed. The tab protrusion 251 can effectively avoid the thermal conductivity between the bottom surface of the wafer holder 2 ι and the encapsulant 25 Irrespective of the stress generated by thermal energy, resulting in so-called de-lamination, that is, it can prevent the current air gap or tortuous surface of the 1363413 (as shown in the conventional package structure of Figure 2), etc. Therefore, riding improves the reliability test yield. In particular, when the thickness of the cover body 25 of the wafer holder is thicker, or the bulk of the package colloid is larger, the stress due to thermal energy will become more apparent. The probability of occurrence of the delamination phenomenon is also higher. At this time, the use of the annular groove 2 of the present invention and the annular latching convex portion 251 can further highlight the effect of improving the reliability of the hybrid. Further, in the package After the construction of the wire-bearing wire 6 is disassembled onto the electronic product, the present invention can also be heard by the high temperature effect caused by the long-term (four) of the electronic product, and the air gap and the surface of the county are prolonged. The invention can also be used to encapsulate the structural reliability of the package after the construction of the gorge. Referring to Figures 6, 7 and 8, the wire ties of the second, third and fourth embodiments of the present invention have a package structure of the lead frame. The invention similar to the figures 3 to 5 - the embodiment of the wire frame and the hybrid structure having the lead frame, but the difference between the two is characterized in that, as shown in the 6th ®, the b-plate holder 211 of the lead frame 21 of the second embodiment is attached thereto The bottom surface is recessed to form at least two annular grooves 211a having a v-shaped cross section. As shown in FIG. 7, the crystal holder 211 of the lead frame η of the third embodiment is recessed on the bottom surface thereof to form a wide-mouth shape (ie, At least the groove 211a of the trapezoidal shape is as shown in Fig. 8. The wafer holder 211 of the lead frame of the fourth embodiment is recessed on the bottom surface thereof to form a slit shape (i.e., a horseshoe shape). Annular groove 2lla. The above-mentioned annular groove I can also provide 12 1363413 liter of colloid bonding strength, sealing strength and product service life.
清參照第9圖所示，本發明第五實施例的導線架及具有導 線架之封裝構造係相似於第5、6、7及s圖之本發明第一至第 四實施例的導線架及具有導線架之封裝構造，但兩者間差異之 特徵在於：如第9圖所示，該第五實施例之導線架2i的晶片 承座211係在其底面選擇凹設形成剖面呈^形、¥形、廣口 幵/( P梯形）或狹口形（即馬蹄形或q形）的至少二環狀凹槽 211a’而該等環狀凹槽2Ua内則選擇利職刻或喷砂等方式 形成一粗#面211b。藉由該粗趟面211b，本發明將可以進一 步增加該晶片承座211底面與所有該等環狀凹槽2na内表面 的總表面積’啸供更多誠_結合該封轉體％，用來 提升膠體結合強度、封裝可靠度及產品使用壽命。 請參照第10及η圖所示，本發明第六及第七實施例的導 線架及具有導線架之封裝構造係相似於第5、6、7、8及9圖 之本發明第一至第五實施例的導線架及具有導線架之封裝構 造，但兩者間差異之特徵在於：如第1〇圖所示，該第六實施 例之導線架以的晶片承座2U係在其底面選擇凹設形成剖面 呈U形、V形、廣口形(即梯形)或狹口形(即馬蹄形或⑽)的 至少二環狀凹槽211a ’且該等環狀凹槽2Ua之深度及戴面積 係由該晶片承座211外緣之最外圈之該環狀凹槽211&往該晶 片承座211中心方向的最内圈之該環狀凹槽咖逐漸變大日。曰 13 =第®所示’該第七實_之導猶21的晶科座21]係 t底面選擇㈣形編呈U形、V形、狗(即_ 或狹口_馬蹄形或〇形)的至少二環狀凹槽2m，且該等學 狀凹槽2113之深度及截面積係由該晶片承座2U外緣之最夕: 圈之該環狀凹槽211a往該晶片承座211中心方向的最内圈之 該環狀凹槽211a逐漸變小。藉由不同尺寸的至少二環狀凹槽 扣a ’本發明將可以進一步增加該晶片承座2ιι底面與所有該 等環狀凹槽21Ia内表面的總表面積，以提供更多的表面積处 合該封裝膠體25，用來提升膠體結合強度、封裝可靠度及產 品使用壽命。 如上所述’她於第丨及2圖之f用轉體封裝構造在加 熱回焊測試時’容易產生該氣隙16她曲表面⑸等永久性 缺陷，而導致降低可靠度測試的良率等缺點，第3 i u圖之 本發明藉由在該晶片承座211之底面形成該至少二環狀凹槽 211a，以便使該封裝膠體25填入該等環狀凹槽2na内，形成 該至少二環狀卡掣凸部25卜如此即可緊密結合於該等環狀凹 槽211a之内表面，故確實可有效提升膠體結合強度、封裝可 靠度、可靠度測試良率及產品使用壽命。 雖然本發明已以較佳實施例揭露，然其並非用以限制本發 明’任何Μ此項技藝之人士，在不脫離本發明之精神和範圍 内，當可作各種更動與修飾，因此本發明之保護範圍當視後附 之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖.習用半導體封裝構造之組合剖視圖。 第2圖·習肖半導體雜構造經過加熱回制試後產生分層現 象的示意圖。 第3圖.本發明第一實施例之具有導線架之封裝構造之組合剖 視圖。 第4圖：本發明第一實施例之導線架之底面之示意圖。 第5圖：本發明第一實施例之導線架之局部放大剖視圖。 第ό圖：本發明第二實施例之導線架之局部放大剖視圖。 第7圖：本發明第三實施例之導線架之局部放大剖視圖。 第8圖：本發明第四實施例之導線架之局部放大剖視圖。 第9圖：本發明第五實施例之導線架之局部放大剖視圖。 第圖：本發明第六實施例之導線架之局部放大剖視圖。 第Π圖：本發明第七實施例之導線架之局部放大剖視圖。 【主要元件符號說明】 11導線架 111 晶片承座 弓丨腳 12 黏著層 13 半導體晶片 131 焊墊 14導線 15 封裝膠體 151翹曲表面 16 氣隙 1363413 21 導線架 211晶片承座 211a環狀凹槽 211b粗縫面 212 引腳 212a内引腳部 212b外引腳部 22 黏著層 23 半導體晶片 231 焊墊 24 導線 25封裝膠體 251環狀卡掣凸部 D2 第二間距 D1 第一間距As shown in FIG. 9, the lead frame of the fifth embodiment of the present invention and the package structure having the lead frame are similar to the lead frames of the first to fourth embodiments of the present invention in the fifth, sixth, seventh and seventh embodiments. The package structure having the lead frame, but the difference between the two is characterized in that, as shown in FIG. 9, the wafer holder 211 of the lead frame 2i of the fifth embodiment is selected to have a concave shape on the bottom surface thereof. At least two annular grooves 211a' of a shape, a wide mouth 幵/(P trapezoidal) or a narrow mouth shape (ie, a horseshoe shape or a q shape), and the annular grooves 2Ua are formed by means of a job or sand blasting. A rough #面211b. With the rough surface 211b, the present invention can further increase the total surface area of the bottom surface of the wafer holder 211 and all the inner surfaces of the annular grooves 2na. Improve colloidal bond strength, package reliability and product life. Referring to FIGS. 10 and η, the lead frame of the sixth and seventh embodiments of the present invention and the package structure having the lead frame are similar to the first to the first invention of the fifth, sixth, seventh, eighth and ninth drawings. The lead frame of the fifth embodiment and the package structure having the lead frame, but the difference between the two is characterized in that, as shown in FIG. 1 , the lead frame 2U of the lead frame of the sixth embodiment is selected on the bottom surface thereof. The concave portion is formed into at least two annular grooves 211a' having a U-shaped, V-shaped, wide-mouth (ie, trapezoidal) or slit shape (ie, a horseshoe shape or (10)), and the depth and wearing area of the annular grooves 2Ua are The annular groove 211 of the outermost circumference of the outer edge of the wafer holder 211 and the annular groove of the innermost circle toward the center of the wafer holder 211 gradually become larger.曰13 = 'The seventh _ _ _ _ _ _ _ _ 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 At least two annular grooves 2m, and the depth and cross-sectional area of the learning grooves 2113 are from the outer edge of the outer edge of the wafer holder 2U: the annular groove 211a of the ring is toward the center of the wafer holder 211 The annular groove 211a of the innermost circumference of the direction gradually becomes smaller. The invention can further increase the total surface area of the bottom surface of the wafer holder 2 ι and the inner surfaces of all of the annular grooves 21Ia by at least two annular groove buckles 'a of different sizes to provide more surface area for the purpose Encapsulant 25 is used to improve the bond strength, package reliability and product life. As described above, 'she used the swivel package structure of the second and second diagrams in the heating reflow test to easily generate permanent defects such as the curved surface (5) of the air gap, resulting in lowering the reliability test yield, etc. Disadvantages, the invention of the third embodiment forms the at least two annular grooves 211a on the bottom surface of the wafer holder 211, so that the encapsulant 25 is filled into the annular grooves 2na to form the at least two The annular latching projections 25 can be tightly coupled to the inner surfaces of the annular recesses 211a, so that the colloidal bonding strength, package reliability, reliability test yield, and product life can be effectively improved. The present invention has been disclosed in its preferred embodiments, and it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a combination of a conventional semiconductor package structure. Fig. 2 Schematic diagram of the stratified phenomenon after the heat recovery test of the Xixiao semiconductor hybrid structure. Fig. 3 is a sectional view showing a combination of a package structure having a lead frame according to a first embodiment of the present invention. Fig. 4 is a view showing the bottom surface of the lead frame of the first embodiment of the present invention. Fig. 5 is a partially enlarged cross-sectional view showing the lead frame of the first embodiment of the present invention. Fig. 1 is a partially enlarged cross-sectional view showing a lead frame of a second embodiment of the present invention. Figure 7 is a partially enlarged cross-sectional view showing a lead frame of a third embodiment of the present invention. Figure 8 is a partially enlarged cross-sectional view showing a lead frame of a fourth embodiment of the present invention. Fig. 9 is a partially enlarged cross-sectional view showing a lead frame of a fifth embodiment of the present invention. Fig.: is a partially enlarged cross-sectional view showing a lead frame of a sixth embodiment of the present invention. Fig. 1 is a partially enlarged cross-sectional view showing a lead frame of a seventh embodiment of the present invention. [Main component symbol description] 11 lead frame 111 wafer holder bow 12 adhesive layer 13 semiconductor wafer 131 pad 14 wire 15 package colloid 151 warped surface 16 air gap 1363413 21 lead frame 211 wafer holder 211a annular groove 211b rough surface 212 pin 212a inner lead portion 212b outer lead portion 22 adhesive layer 23 semiconductor wafer 231 pad 24 wire 25 encapsulant colloid 251 ring dowel convex portion D2 second pitch D1 first pitch