CN112018093A - 具有定位成减少模片开裂的顶部模片的半导体器件 - Google Patents

具有定位成减少模片开裂的顶部模片的半导体器件 Download PDF

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CN112018093A
CN112018093A CN201910469575.0A CN201910469575A CN112018093A CN 112018093 A CN112018093 A CN 112018093A CN 201910469575 A CN201910469575 A CN 201910469575A CN 112018093 A CN112018093 A CN 112018093A
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die
semiconductor
stack
semiconductor device
dies
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严俊荣
张建明
赵敏
张凯雷
陈治强
莫金理
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SanDisk Technologies LLC
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Western Digital Technologies Inc
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Priority to CN201910469575.0A priority Critical patent/CN112018093A/zh
Priority to US16/814,761 priority patent/US11177241B2/en
Publication of CN112018093A publication Critical patent/CN112018093A/zh
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Abstract

本发明题为“具有定位成减少模片开裂的顶部模片的半导体器件”。本发明公开了一种半导体器件，所述半导体器件包括模片叠堆，所述模片叠堆包括相对于轴线彼此对准的多个模片以及沿所述轴线偏移以防止模片开裂的顶部模片。

Description

具有定位成减少模片开裂的顶部模片的半导体器件
背景技术
便携式消费电子器件需求的强劲增长推动了对高容量存储设备的需求。非易失性半导体存储装置，诸如闪存存储卡，已广泛用于满足对数字信息存储和交换的日益增长的需求。它们的便携性、多功能性和坚固耐用的设计以及它们的高可靠性和大容量，使得此类存储装置理想地用于多种电子设备中，包括例如数字相机、数字音乐播放器、视频游戏控制器、PDA和蜂窝电话。
虽然已知许多不同的封装配置，但是闪存半导体产品通常可以被制造为系统级封装(SIP)或多芯片模块(MCM)，其中多个半导体模片被安装并互连到基板的上表面。基板通常可以包括刚性的电介质基部，其具有在一侧或两侧上蚀刻的导电层。焊料球通常安装在形成在基板下表面上的接触焊盘上，以允许基板焊接到主机设备，诸如印刷电路板。一旦安装，信号可以经由基板在包装件中的半导体模片于主机设备之间传输。
一直存在在较小的整体形状因数半导体包装件中提供更大的存储容量的需求。这样做的一种方法是减小包装件内半导体模片的厚度，而不会损失或甚至获得存储容量。减小半导体模片的厚度的一个缺点在于它们变得更加易碎，并且易于例如在经受封装工艺时开裂。在包装件中的所有模片中，最上面的模片通常最易于开裂。这是因为其上不存在其他模片来提供结构支撑。同时也因为最上面的模片具有用于将该模片接合到叠堆上的最短的加热时间。例如，底部模片不仅在添加时被加热，而且在添加每个后续模片时都被加热。在最上面的模片之后不再添加模片，因此它仅经历与其附接相关的单个加热过程。
附图说明
图1是根据本发明技术的实施方案的用于形成半导体器件的流程图。
图2是根据本发明技术的实施方案的包括半导体模片的半导体晶圆的顶视图。
图3是根据本发明技术的实施方案的半导体模片的顶视图。
图4是根据本发明技术的实施方案的半导体模片的边视图。
图5是根据本发明技术的实施方案的一组堆叠的半导体模片的顶视图。
图6是根据本发明技术的实施方案的图5的该组半导体模片的前边视图。
图7是根据本发明技术的实施方案的一组堆叠且线接合的半导体模片的顶视图。
图8是根据本发明技术的实施方案的图7的一组堆叠且线接合的半导体模片的前边视图。
图9是根据本发明技术的实施方案的图7的一组堆叠且线接合的半导体模片的侧边视图。
图10是根据本发明技术的实施方案的图7的一组堆叠且线接合的半导体模片的透视图。
图11是根据本发明技术的实施方案的一组堆叠且线接合的半导体模片的顶视图。
图12是根据本发明技术的实施方案的图11的一组堆叠且线接合的半导体模片的前边视图。
图13是根据本发明技术的实施方案的图11的一组堆叠且线接合的半导体模片的侧边视图。
图14是根据本发明技术的实施方案的图11所示的模片叠堆中不同半导体模片的粘结时间图表。
图15是根据本发明技术的实施方案的一组堆叠且线接合的半导体模片的顶视图。
图16是根据本发明技术的实施方案的图11的一组堆叠且线接合的半导体模片的前边视图。
图17是根据本发明技术的实施方案的图11的一组堆叠且线接合的半导体模片的侧边视图。
图18是根据本发明技术的实施方案的完整半导体器件的侧边视图。
图19是本发明技术的另选实施方案的前边视图。
具体实施方式
现在将参考附图描述本发明的技术，该附图在实施方案中涉及包括顶部模片的半导体器件，该顶部模片被偏移以防止模片开裂。应当理解，本发明可体现为许多不同形式并且不应解释为限于本文所阐述的实施方案。相反，提供了这些实施方案，使得本公开将是周密且完整的，并且将充分地将本发明传达给本领域的技术人员。实际上，本发明旨在覆盖这些实施方案的另选方案、修改和等同物，这些均包括在由所附权利要求书所限定的本发明的范围和实质内。此外，在本发明的以下具体实施方式中，给出了许多具体细节，以便提供对本发明的周密理解。然而，对于本领域的普通技术人员将显而易见的是，本发明可在没有此类具体细节的情况下被实施。
本文所用的术语“顶部”和“底部”、“上”和“下”以及“垂直”和“水平”及其形式，如可仅以举例方式和出于示例性目的用于本文，并且不旨在限制技术的描述，因为所引用的项目可在位置和取向上交换。另外，如本文所用，术语“基本上”和/或“约”是指指定的尺寸或参数可在给定应用的可接受的制造公差内变化。在一个实施方案中，可接受的制造公差为给定尺寸的±2.5％。
现在将参考图1的流程图以及图2至图18的视图解释本发明技术的实施方案。在步骤200中，可以将半导体晶圆100加工成如图2所示的多个半导体模片102。半导体晶圆100开始时可以是晶圆材料的晶锭，晶圆材料可以是根据Czochralski(CZ)或浮区(FZ)工艺生长的单晶硅。然而，在另外的实施方案中，晶圆100可由其他材料并通过其他工艺形成。
可以从晶锭切割出半导体晶圆100并在第一主平坦表面104和与该表面104相反的第二主平坦表面105(图4)两者上抛光，以提供平滑表面。第一主表面104可以经历各种加工步骤以将晶圆100分成相应的半导体模片102。具体地讲，在步骤200中，可在实施方案中加工半导体模片102以在电介质基板中形成集成电路和内部电连接。半导体模片的顶表面可包括聚酰亚胺(PI)/钝化层110和模片接合焊盘106(图3)。图2中晶圆100上所示的半导体模片102的数目是为了进行示意性的说明，并且晶圆100可包括比在另外的实施方案中所示更多的半导体模片102。
众所周知，切割道112可被限定在晶圆100上的半导体模片102的行和列之间。将一个水平切割道和一个垂直切割道在图2中以虚线示出并标记，但围绕晶圆100中的每个半导体模片都设置有水平切割道和垂直切割道。这些切割道112没有集成电路和PI/钝化层110，并且被设置作为其中可例如通过刀片或激光切割晶圆的区域。在实施方案中，切割道112可为70微米宽，但在另外的实施方案中，切割道112可更宽或更窄。在步骤202中，在晶圆100被加工以形成集成电路之后，可在第二主平面表面105上形成模片附着膜(DAF)层114(图4)。
在步骤204中，可将半导体晶圆100沿切割道112切割以将各个半导体模片102与晶圆100分开。在图3和图4中分别以顶视图和边视图示出各个半导体模片102。在实施方案中，可使用激光切割晶圆100，这样为切缝宽度窄的晶圆提供高度精确且受控的切力。结果，切割的半导体模片102各自包括围绕其四个边缘的边界，包括切割道112的宽度的一部分(例如，一半)。如上所述，图中标记为118的这些边界没有任何集成电路并且没有PI/钝化层110。
在实施方案中，边界118可具有35微米的宽度w，但在另外的实施方案中，该宽度可更小或更大。在实施方案中，边界118可具有围绕半导体模片102的所有四个边缘的相同宽度，但在另外的实施方案中，该边界可具有围绕一个或多个边缘的不等宽度。如图4中可见，PI/钝化层110可在围绕半导体模片102的外周形成的边界118上方延伸。因此，半导体模片102包括具有厚度t1的内部部分和具有小于t1的厚度t2的外部边界。在实施方案中，模片102(包括DAF层114)的内部部分的厚度t1可为43.4微米，并且围绕模片102的边界部分的厚度t2可为37微米。这些厚度仅以举例的方式示出，并且可在另外的实施方案中变化。
除了绝缘和保护之外，PI/钝化层110还沿垂直于主表面104、105的轴线为半导体模片102提供附加的强度。因此，半导体模片102更坚固，并且与穿过边界118的横截面相比，沿穿过包括PI/钝化层110的模片102的横截面的抗剪切力和抗弯曲力更大。
在步骤208中，在切割之后，可将多个半导体模片102安装在基板上，诸如图5和图6所示的基板120。图5和图6分别示出了半导体器件150的一部分的顶视图和前边视图，该半导体器件包括模片叠堆122中的模片中的一些。如下文所述，将附加的模片102添加到叠堆122。在图5和图6所示的模片叠堆122中，模片在y方向上以阶梯式的偏移构型堆叠，使得第一模片102上的一排模片接合焊盘106不被覆盖并由安装在其上的第二模片102暴露。叠堆122中的模片102可相对于x轴彼此对准。模片102可通过DAF层114(图5至图19中未单独标记)附连到基板120并彼此附连。如图6中可见，PI/钝化层110的厚度在叠堆122中的相邻模片102的边界118之间提供空间。
图7、图8、图9和图10分别示出了包括完整模片叠堆122的半导体器件150的一部分的顶视图、前边视图，侧边视图和透视图。在图7至图10所示的模片叠堆122中，已将最上面的模片102a添加到该叠堆。如同叠堆122中较低的模片102中一样，该模片102a在y方向上以偏移构型呈现阶梯状。根据该技术的各方面，模片102a也在x方向上偏移。模片102a可沿x轴偏移，使得模片102a的边缘126(图7、图8和图10)位于下一较低的模片102的PI/钝化层110之上。在实施方案中，顶部模片102a可沿x轴偏移6.4微米，但在另外的实施方案中，其可偏移更多或更少。另外，虽然边缘126被示出为直接安装在下一较低模片102的PI/钝化层110之上，但应当理解，沿x轴的偏移可增大，使得模片102a的边缘126与下一较低的模片的PI/钝化层110的边缘向内间隔开。
半导体模片102可以是各种半导体模片中的任何一种，包括例如存储器模片，诸如2D NAND闪存存储器或3D BiCS(位成本缩放)、V-NAND或其他3D闪存存储器。然而，可以使用其他类型的半导体模片，包括例如RAM，诸如SDRAM、DDR SDRAM、LPDDR和GDDR。另外，在步骤208中，也可将控制器模片诸如ASIC(未示出)安装在基板上或叠堆122的顶部上。
在将半导体模片安装在基板120上之前或之后，都可在步骤210中将无源部件(未示出)安装在基板120上。无源部件可包括例如电阻器、电容器和/或电感器。
一旦将模片102(包括模片102a)安装在叠堆122中，则在步骤214中，模片102可彼此电互连，并且与基板120电互连。在一个实施方案中，电互连件可为如图7至图10所示的线接合件128。可使用线接合毛细管(未示出)在已知的线接合工艺中形成线接合件，线接合毛细管将不同模片102中的对应模片接合焊盘106彼此连接并且连接到基板120上的接触焊盘130(图7和图10)上。线接合件可直线向上延伸到模片叠堆122，然后在最上面的模片102a和下一较低的模片之间进行对角延伸。
线接合件128可例如为在沉积在接合焊盘106和接触焊盘130上的球形接合上形成的楔形接合，但在另外的实施方案中，也可为其他类型的线接合件。此外，可设想的是，除了线接合件外，电互连件还可通过硅通孔(TSV)形成，该硅通孔(TSV)向下穿过叠堆122中的不同模片102形成并且与基板120上的接触焊盘的图案接触。
虽然图7至图10示出了叠堆122中的四个半导体模片，但应当理解，在另外的实施方案中，叠堆122可包括各种数量的存储器模片，包括例如2、8、16、32和64个存储器模片。介于2和64之间以及大于64的其他数量的模片是可能的。图11至图13示出了包括八个半导体模片的另一个此类实施方案的顶视图、前边视图和侧边视图。如上所述，模片叠堆122中的所有模片沿y轴以阶梯式构型偏移。除了最上面的模片102a之外，模片叠堆122中的所有模片均相对于x轴彼此对准。如上所述，最上面的模片102a沿x轴偏移，使得模片102a的边缘126在下一较低的模片的PI/钝化层110之上对准。
如背景技术部分所述，考虑到现代半导体模片的薄轮廓，这些半导体模片是脆弱的并且易于在制造期间开裂。例如，考虑到PI/钝化层的高度，半导体模片在其在边界区域中的边缘周围不受支撑。当经受应力时，例如在封装工艺期间，模片可能在这些边缘处开裂。这在顶部半导体模片处是最为可能的，因为该模片经历最少量的固化时间。如图14的图表所示，八模片叠堆中的每个模片经历1秒的直接接合。然而，早期接合的模片(即，叠堆122中较低的那些模片)还经历间接接合时间。例如，第一(最底部)模片经历1秒的直接接合时间，然后每向模片堆叠添加一个另外模片都会增加附加1秒的间接接合时间。除了最上面的模片之外，叠堆122中的每个模片均经历这种附加的间接接合时间。因此，最上面的模片102a与叠堆的接合最弱，并且在经受应力时可能会弯曲和/或断裂。
本发明技术通过沿x轴偏移最上面的模片102a来解决该问题。这样，模片102a的外边缘126被完全支撑在其下方的模片上(即，在其下方的模片的PI/钝化层110上)。相对的边缘-边缘134(图12)仍然悬于空的空间之上。然而，模片102a在边缘134处悬于空的空间之上的部分也包括PI/钝化层110。因此，模片102a延伸超出下一较低的模片的PI/钝化层110的部分在悬伸部处具有更大的厚度(即，边界118的厚度加上PI/钝化层110的厚度)。(与较低的模片相比)在边缘134处在悬伸区域处的这种相对更大的厚度提供比叠堆中的较低的模片更大的强度和抗剪切应力。
图15至图17分别示出了叠堆122中包括八个模片的另一个实施方案的顶视图、前边视图和侧边视图。如例如图17中可见，并非每个模片沿y轴在相同方向上偏移，而是模片堆叠成自身对折。这种实施方案可在x-y平面中在基板上具有更小的占有面积。在该实施方案中，线接合件128可在基板120的相对边缘处连接至基板120上的两行接触焊盘，如图17所示。除了最上面的模片102a之外，所有模片均可沿x轴彼此对准，最上面的模片可如上所述地沿x轴偏移。
再次参考图1，在将半导体模片102安装到叠堆122中并电互连之后，可在步骤216中将这些半导体模片102封装在模塑化合物140中，如图18所示。模塑化合物140可包括例如固体环氧树脂、酚醛树脂、熔融二氧化硅、结晶二氧化硅、炭黑和/或金属氢氧化物。设想了来自其他制造商的其他模塑化合物。模塑化合物可通过各种已知工艺施加，包括通过压塑、FFT(无流动薄)模塑、传递模塑或注塑成型技术。
在制造过程中，可以将基板120保持为许多基板的面板，以在制造过程中实现规模经济。在封装步骤之后，各个半导体器件150可在步骤220中彼此切割(分离)以形成图18所示的完整半导体器件。根据半导体器件150的应用，可将焊料球148的图案施加在基板120的底表面上，如图18所示。例如，可在将模片安装在基板上的步骤208之前施加这些焊料球。然后，通过将焊料球148焊接在主机设备的接触焊盘上，可以将半导体器件150安装在主机设备(未示出)上。此后，可通过半导体模片102完成半导体器件150和主机设备之间的通信。
在上述实施方案中，通过偏移模片来加强最上面的模片102a以防开裂，使得一边缘直接支撑在下一较低的模片上，而相对边缘在其悬于下一较低的模片的地方具有相对较大的厚度。应当理解，除了最上面的模片之外的模片也可以沿x轴偏移，以为这些模片增加强度。图19示出了一个示例，其中最上面的三个模片(模片102a、模片102b和模片102c)各自不仅沿y轴彼此偏移，而且以上文相对于模片102a描述的方式沿x轴偏移。在图19所示的实施方案中，模片102a、模片102b和模片102c沿x轴在交替方向上偏移。在另外的实施方案中，模片102a、模片102b和模片102c可各自沿x轴在相同方向上偏移。应当理解，在另外的实施方案中，最上面的两个模片或多于最上面的三个模片可沿x轴彼此偏移。
概括地说，本发明技术的示例涉及一种半导体器件，包括：多个半导体模片，该多个半导体模片各自包括：具有第一厚度的内部部分，以及沿相对的第一边缘和第二边缘的具有小于该第一厚度的第二厚度的外部部分；其中多个半导体模片在叠堆中堆叠在彼此的顶部上，使得在该叠堆的底部处的一组半导体模片相对于第一轴线彼此对准，并且至少最上面的模片相对于下一较低的模片沿第一轴线偏移，该偏移量将最上面的模片在第一边缘处的外部部分定位在下一较低的模片的内部部分之上。
在另一示例中，本发明技术涉及一种半导体器件，包括：多个n半导体模片，该多个半导体模片各自包括：具有第一厚度的内部部分，以及沿相对的第一边缘和第二边缘的具有小于该第一厚度的第二厚度的外部部分；其中多个n半导体模片在叠堆中堆叠在彼此的顶部上，并且被配置为通过以下方式来增加最上面的半导体模片的强度和抗开裂性：使在该叠堆的底部处的一组n-1个半导体模片相对于第一轴线彼此对准，并且使最上面的模片相对于下一较低的模片沿第一轴线偏移，该偏移量将最上面的模片在第一边缘处的外部部分定位在下一较低的模片的内部部分之上。
在另一示例中，本发明技术涉及半导体器件，包括：多个n半导体模片，该多个半导体模片各自包括：具有第一厚度的内部部分，以及沿相对的第一边缘和第二边缘的具有小于该第一厚度的第二厚度的外部部分；其中多个n半导体模片堆叠在彼此的顶部上；用于通过以下方式来增加最上面的半导体模片的强度和抗开裂性的装置：使在该叠堆的底部处的一组n-1个半导体模片相对于第一轴线彼此对准，并且使最上面的模片相对于下一较低的模片沿第一轴线偏移，该偏移量将最上面的模片在第一边缘处的外部部分定位在下一较低的模片的内部部分之上。
已出于例证和描述的目的提出本发明的上述具体实施方式。它并非旨在是穷尽的或将本发明限制为所公开的精确形式。根据以上教导内容，很多修改形式和变型形式都是可能的。选择所述实施方案是为了最佳地阐明本发明的原理以及其实际应用，以由此使得本领域的其他技术人员能够最佳地在各种实施方案中使用具有适合于所构想的特定用途的各种修改的本发明。本发明的范围旨在由所附权利要求书限定。

Claims (20)

1.一种半导体器件，包括：
多个半导体模片，所述多个半导体模片各自包括：
具有第一厚度的内部部分，以及
沿相对的第一边缘和第二边缘的具有小于所述第一厚度的第二厚度的外部部分；
其中所述多个半导体模片在叠堆中堆叠在彼此的顶部上，使得在所述叠堆的底部处的一组半导体模片相对于第一轴线彼此对准，并且至少最上面的模片相对于下一较低的模片沿所述第一轴线偏移，偏移量将所述最上面的模片在所述第一边缘处的外部部分定位在所述下一较低的模片的内部部分之上。
2.根据权利要求1所述的半导体器件，其中所述最上面的模片在所述第二边缘处的所述内部部分悬于所述下一较低的模片的所述外部部分之上。
3.根据权利要求1所述的半导体器件，其中所述内部部分和所述外部部分之间的厚度差在于所述内部部分包括在所述外部部分的表面上方延伸的聚酰亚胺/钝化层。
4.根据权利要求3所述的半导体器件，其中外部部分为切割道的一部分，在此处从晶圆切割所述多个半导体模片。
5.根据权利要求1所述的半导体器件，其中所述叠堆中的所述多个半导体模片沿正交于所述第一轴线的第二轴线以阶梯式构型彼此偏移。
6.根据权利要求5所述的半导体器件，其中所述叠堆中的所述多个半导体模片沿所述第二轴线在相同方向上以所述阶梯式构型彼此偏移。
7.根据权利要求5所述的半导体器件，其中所述叠堆中的所述多个半导体模片中的一些沿所述第二轴线在第一方向上以所述阶梯式构型彼此偏移，并且其中所述叠堆中的所述多个半导体模片中的一些沿所述第二轴线在与所述第一方向相反的第二方向上以所述阶梯式构型彼此偏移。
8.根据权利要求5所述的半导体器件，还包括线接合件，所述线接合件在所述叠堆中的所述多个半导体模片上的对应模片接合焊盘之间沿所述第二方向延伸。
9.根据权利要求1所述的半导体器件，其中所述叠堆中的模片的数量为n，并且在所述叠堆的底部处的模片组中相对于第一轴线彼此对准的模片的数量为n-1。
10.根据权利要求1所述的半导体器件，其中所述多个半导体模片为存储器模片。
11.根据权利要求10所述的半导体器件，其中所述多个存储器模片为2D NAND闪存存储器或3D位成本缩放闪存存储器中的一者。
12.一种半导体器件，包括：
多个n半导体模片，所述多个半导体模片各自包括：
具有第一厚度的内部部分，以及
沿相对的第一边缘和第二边缘的具有小于所述第一厚度的第二厚度的外部部分；
其中所述多个n半导体模片在叠堆中堆叠在彼此的顶部上，并且被配置为通过以下方式来增加最上面的半导体模片的强度和抗开裂性：使在所述叠堆的底部处的一组n-1个半导体模片相对于第一轴线彼此对准，并且使最上面的模片相对于下一较低的模片沿所述第一轴线偏移，偏移量将所述最上面的模片在所述第一边缘处的外部部分定位在所述下一较低的模片的内部部分之上。
13.根据权利要求12所述的半导体器件，其中所述最上面的模片在所述第二边缘处的所述内部部分悬于所述下一较低的模片的所述外部部分之上。
14.根据权利要求12所述的半导体器件，其中所述内部部分和所述外部部分之间的厚度差在于所述内部部分包括在所述外部部分的表面上方延伸的聚酰亚胺/钝化层。
15.根据权利要求14所述的半导体器件，其中外部部分为切割道的一部分，在此处从晶圆切割所述多个半导体模片。
16.根据权利要求12所述的半导体器件，其中所述叠堆中的所述多个半导体模片沿正交于所述第一轴线的第二轴线以阶梯式构型彼此偏移。
17.根据权利要求16所述的半导体器件，其中所述叠堆中的所述多个半导体模片沿所述第二轴线在相同方向上以所述阶梯式构型彼此偏移。
18.根据权利要求16所述的半导体器件，其中所述叠堆中的所述多个半导体模片中的一些沿所述第二轴线在第一方向上以所述阶梯式构型彼此偏移，并且其中所述叠堆中的所述多个半导体模片中的一些沿所述第二轴线在与所述第一方向相反的第二方向上以所述阶梯式构型彼此偏移。
19.根据权利要求16所述的半导体器件，还包括线接合件，所述线接合件在所述叠堆中的所述多个半导体模片上的对应模片接合焊盘之间沿所述第二方向延伸。
20.一种半导体器件，包括：
多个n半导体模片，所述多个半导体模片各自包括：
具有第一厚度的内部部分，以及
沿相对的第一边缘和第二边缘的具有小于所述第一厚度的第二厚度的外部部分；
其中所述多个n半导体模片堆叠在彼此的顶部上；
用于通过以下方式来增加最上面的半导体模片的强度和抗开裂性的装置：使在所述叠堆的底部处的一组n-1个半导体模片相对于第一轴线彼此对准，并且使所述最上面的模片相对于下一较低的模片沿所述第一轴线偏移，偏移量将所述最上面的模片在所述第一边缘处的外部部分定位在所述下一较低的模片的内部部分之上。
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