CN109904083A - 用于晶片级管芯桥的方法和设备 - Google Patents

用于晶片级管芯桥的方法和设备 Download PDF

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Publication number
CN109904083A
CN109904083A CN201811493073.3A CN201811493073A CN109904083A CN 109904083 A CN109904083 A CN 109904083A CN 201811493073 A CN201811493073 A CN 201811493073A CN 109904083 A CN109904083 A CN 109904083A
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China
Prior art keywords
rdl
tube core
bridge
mold layer
electrical interconnection
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CN201811493073.3A
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熊健刚
A·桑达拉扬
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Applied Materials Inc
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Applied Materials Inc
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Publication of CN109904083A publication Critical patent/CN109904083A/zh
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Abstract

公开了用于晶片级管芯桥的方法和设备。将晶片级桥管芯用粘合剂层附贴到已经暂时地接合到载体的重分布层(RDL)。在所述RDL上和所述桥管芯上形成电互连件并将其封装在第一模层中。将多个管芯耦接到所述RDL和所述桥管芯，使得管芯电连接到所述RDL的至少一个电互连件和所述桥管芯的至少一个电互连件。在所述第一模层上形成第二模层以封装所述多个管芯。然后，破坏暂时接合并去除载体，从而暴露RDL连接。

Description

用于晶片级管芯桥的方法和设备
技术领域
本原理的实施方式总体涉及半导体工艺。
背景技术
集成电路通常根据所期望的功能由不同工艺形成。一个功能的多个芯片一般被构造在单个晶片上，并且然后被切分以形成单个管芯或“芯片”。在其它实例中，多个芯片可以具有多个功能并包括管芯划分和多个功能管芯集成。芯片具有输入和输出(“I/O”)，芯片的I/O需要电连接到其它芯片的I/O连接。例如，处理芯片可以需要连接到存储器芯片以正确地执行功能。一种电连结两个芯片的方式是使用称为“桥”的有源或无源器件。桥提供从一个芯片的I/O连接到另一个芯片的I/O连接的路径。桥可以是具有无源连接路径或具有有源功能的硅管芯。然而，使用桥来提供连接通常增加半导体器件的制造复杂性，并且因此也可能会限制可制造半导体器件的制造者。形成在基板中的桥通常是如前述情况那样，这可能会限制制造厂(芯片的制造商)的工艺，这与外包组装和测试(OSAT)设施(限于晶片级制造)相反。在桥和芯片放置之后形成重分布层(RDL)的一些晶片级工艺存在因低RDL产量而不得不丢弃昂贵芯片的风险。
因此，发明人已提供了一种用于形成晶片级管芯桥的改进的方法和设备。
发明内容
一种形成晶片级桥管芯的方法的一些实施方式包括：形成重分布层(RDL)；和将桥管芯附贴在所述RDL上，所述桥管芯在与所述RDL相对的暴露表面上具有电连接。
一种形成晶片级桥管芯的方法的一些实施方式还包括：在载体上形成所述RDL；或使用所述桥管芯与所述RDL之间的粘合剂将所述桥管芯附贴在所述RDL上；或在所述RDL上形成至少一个电互连件；在所述桥管芯上形成至少一个电互连件；在所述RDL和所述桥管芯上面形成第一模层；和将多个管芯耦接到所述RDL并耦接到所述桥管芯，使得管芯电连接到所述RDL的至少一个电互连件并电连接到所述桥管芯的至少一个电互连件；或在所述第一模层上和在所述多个管芯上形成第二模层；或在所述第一模层上形成至少一个集成无源器件；和在所述第一模层上、在所述多个管芯上和在所述至少一个集成无源器件上形成第二模层；或使用铜基材料在所述RDL上形成至少一个电互连件或在所述桥芯片上形成至少一个电互连件；或在所述RDL上形成至少一个电互连件；在所述桥管芯上形成至少一个电互连件；在所述RDL上形成至少一个穿模通孔(TMV)的至少一个第一部分；在所述RDL和所述桥管芯上面形成第一模层；形成所述至少一个TMV的至少一个第二部分；将多个管芯耦接到所述RDL并耦接到所述桥管芯，使得管芯电连接到所述RDL的至少一个电互连件并电连接到所述桥管芯的至少一个电互连件；和在所述第一模层上和在所述多个管芯上形成第二模层，所述至少一个TMV在所述第二模层的顶表面处具有电连接以用于支持封装层叠(PoP)电连接；或使用电镀工艺形成所述至少一个TMW。
一种形成晶片级桥管芯的方法的一些实施方式包括：暂时地将重分布层(RDL)结合在载体上；将桥管芯附贴在所述RDL上，所述桥管芯在与所述RDL相对的暴露表面上具有电连接；在所述RDL上形成至少一个电互连件；在所述桥管芯的所述暴露表面上形成至少一个电互连件；在所述RDL和所述桥管芯上形成第一模层；将多个管芯耦接到所述RDL并耦接到所述桥管芯，使得管芯电连接到所述RDL的至少一个电互连件并电连接到所述桥管芯的至少一个电互连件；在所述第一模层上和在所述多个管芯上形成第二模层；和从所述RDL上去除所述载体。
一种形成晶片级桥管芯的方法的一些实施方式还包括：将热交换层附贴到所述多个管芯中的至少一个的顶表面；或将所述RDL电连接到基板或印刷电路板；或在形成所述第二模层之前在所述第一模层上形成至少一个集成无源器件；或形成从所述RDL到所述第二模层的顶表面的至少一个穿模通孔。
一种用于连接半导体器件的设备的一些实施方式包括：重分布层(RDL)；桥管芯；和插置在所述RDL与所述桥管芯之间的粘合剂层。
一种用于连接半导体器件的设备的一些实施方式还包括：在所述RDL上的至少一个电互连件；在所述桥管芯上的至少一个电互连件；和在所述RDL和所述桥管芯上的第一模层；或多个管芯，耦接到所述RDL并耦接到所述桥管芯，使得管芯电连接到所述RDL的所述至少一个电互连件中的至少一个并电连接到所述桥管芯的所述至少一个电互连件中的至少一个；和在所述第一模层上和在所述多个管芯上的第二模层；或多个管芯，耦接到所述RDL并耦接到所述桥管芯，使得管芯电连接到所述RDL的所述至少一个电互连件中的至少一个并电连接到所述桥管芯的所述至少一个电互连件中的至少一个；在所述第一模层上的至少一个集成无源器件；和在所述第一模层上、在所述多个管芯上和在所述至少一个集成无源器件上的第二模层；或在所述RDL上的至少一个电互连件；在所述RDL上的至少一个集成无源器件；在所述桥管芯上的至少一个电互连件；在所述RDL上的至少一个穿模通孔(TMV)的至少一个第一部分；和在所述RDL和所述桥管芯上的第一模层；或所述至少一个TMV的至少一个第二部分；多个管芯，耦接到所述RDL并耦接到所述桥管芯，使得管芯电连接到所述RDL的所述至少一个电互连件中的至少一个并电连接到所述桥管芯的所述至少一个电互连件中的至少一个；和在所述第一模层上和在所述多个管芯上的第二模层，所述至少一个TMV在所述第二模层的顶表面处具有电连接以用于支持封装层叠(PoP)电连接。
附图简述
可以参考附图中描绘的本原理的说明性实施方式来理解在以上简要地概述且以下更详细讨论的本原理的实施方式。然而，附图仅示出了本原理的典型实施方式，并且因此不应视为限制范围，因为本原理可允许其它同等有效实施方式。
图1是根据本原理的一些实施方式的形成晶片级桥管芯的方法。
图2是根据本原理的一些实施方式的形成晶片级桥管芯的另一种方法。
图3A至3G描绘了根据本原理的一些实施方式的从图1的方法形成的设备。
图4A至4F描绘了根据本原理的一些实施方式的从图2的方法形成的设备。
为了促进理解，已经尽可能地使用相同的附图标记标示各图共有的相同要素。各图未按比例绘制，并且为了清楚起见，可以进行简化。一些实施方式的要素和特征可有益地结合在其它实施方式中，而不赘述。
具体实施方式
晶片级管芯桥附贴到重分布层(RDL)。RDL可以预制造并暂时地接合到载体或用暂时粘合的粘合剂直接地形成在载体上。一般，RDL具有低生产量(高故障率)。细间距RDL结构甚至更难制造。通过首先预制造RDL并将RDL附接到载体或首先在载体上形成RDL，可以丢弃任何有缺陷的RDL而不丢弃其它有价值的部件，从而降低总生产成本。此外，由于首先构造RDL，因此其它半导体器件(诸如管芯)的热预算不会限制RDL形成工艺。另一个优点是可以实现RDL的延长的高温固化，而不会有损坏其它昂贵部件的风险。
桥管芯通过遵循线后端(BEOL)工艺流程(例如，双镶嵌工艺)或标准RDL工艺流程(半添加工艺)单独地制造，这可以实现小于1/1线/间隔(典型，0.8/0.8L/S或0.4/0.4μm)设计。细间距电路能够满足芯片对芯片的互连需要。另外，由于管芯桥是在晶片级处生产的，并且不需要铸造工作，因此该工艺还与外包装配和测试(OSAT)设施高度兼容。如果RDL是在芯片放置之后构建的，那么大多数的(即使不是全部)OSAT设施很可能不具有正确地形成RDL的精度对准能力，从而限制铸造厂的生产并增加制造成本。
由于首先形成RDL，因此细线间隔可以是2/2或更小。RDL形成在载体上，该载体可具有非常光滑的表面。当在其它模层和管芯上形成RDL时，在管芯/磨具交点处形成阶梯高度。阶梯高度产生不适合形成细间距RDL的形貌，大大降低更细间距RDL产量，并且随后，当RDL工艺失败时，因制造时间的损失和芯片成本的损失而增加成本。RDL第一晶片级管芯桥工艺具有更好地控制RDL工艺(没有管芯热预算问题)、提高RDL质量(因平坦形貌而引起的细间距控制)和提高RDL产量而没有损失昂贵管芯的风险的优点。晶片级管芯桥工艺成本也低于使用插置器的桥方案。由于没有插置器，也可以减小大小，因此管芯替代插入物成为尺寸的限制因素。尺寸减小允许晶片级桥管芯与更大的封装兼容(2X掩模版大小的突破)。
图1示出了根据本原理的一些实施方式的用于形成RDL第一晶片级桥管芯的方法100。方法100涉及图3A至3G中所示的设备，这将被相应地参考。在框102中，如图3A所示的结构300A包括RDL 306，其中至少一个电互连件314形成在RDL 306上，RDL 306用接合层304或RDL 306暂时地接合到载体302，并且至少一个电连接件314形成在载体302上的接合层304上。载体302可以由诸如玻璃、GaN、硅或聚丙烯(预浸渍)基板等的材料制成。在框104中，如图3B所示的结构300B包括用粘合剂308附贴在RDL 306上的桥管芯310。粘合剂308有助于在进一步的处理期间定位和保持桥管芯，从而允许方法100被执行。粘合剂308可以是通常用于引线接合技术中的有机或无机物质或化合物。在框106中，结构300B还包括形成在桥芯片310与RDL 306相对的暴露表面330上的至少一个电互连件312。电互连件312、314允许在形成后续层(下面讨论)之后与RDL306和桥管芯310进行连接。电互连件312、314有时被称为柱，并且可以由导电材料形成，导电材料诸如例如包括铜基材料、钨基材料和银基材料的金属和/或例如导电聚合物基材料等。典型地使用电镀工艺来形成电互连件312、314。任选的集成无源器件(IPD)322也可以放置在RDL 306的顶表面394上。包括IPD是方法100相对于其它技术的另一个优点。
在框108中，如图3C所示的结构300C包括形成在RDL 306和桥管芯310上的第一模层316。第一模层316可以由诸如例如聚酰亚胺、苯并环丁烯、聚苯并恶唑、环氧模塑料(EMC)(有或没有填料)等的材料形成。在形成第一模层316之后可以采用平面化工艺诸如化学机械抛光(CMP)以平面化第一模层316的顶表面360来进一步暴露电互连件312、314。在框110中，如图3D所示的结构300D包括放置在第一模层316上并经由电互连件312、314耦合到RDL306和桥管芯310的多个管芯318、320。另一个任选的集成无源器件(IPD)322也可以放置在第一模层316的顶表面360上。
在框112中，如图3E所示的结构300E包括形成在第一模层316上和多个管芯318、320上(以及任选的IPD上)的第二模层324。第二模层324可以由诸如例如聚酰亚胺、苯并环丁烯、聚苯并恶唑、环氧模塑料(EMC)(有或没有填料)等的材料形成。在形成第二模层324之后可以采用平面化工艺诸如CMP以平面化第二模层324的顶表面370来进一步暴露多个管芯318、320的顶表面380。平面化可以允许多个管芯的顶表面380与热交换层等之间的更好的接触(下面讨论)。在框114中，如图3F所示的结构300F具有载体302，载体302从RDL 306上去除(去接合)。例如球焊可以用于形成任选的球326以将RDL 306的下表面390连接到其它电路。如图3G所示的结构300G包括任选的基板或印刷电路板354和与多个管芯318、320的顶表面380接触以在多个管芯318、320的操作期间移除热的任选的热交换层350。基板或印刷电路板354可以包含经由形成在RDL 306的下表面390上的任选的球326连接的另外的电路。
图2是根据本原理的一些实施方式的用于形成RDL第一晶片级桥管芯的另一种方法200。方法200涉及图4A至4F中所示的设备，这将被相应地参考。在适当时使用相似的元件符号来简化说明。在框202中，如图4A所示的结构400A包括RDL 306，RDL 306用接合层304暂时地接合到载体302，或RDL 306形成在载体302上的接合层304上。载体302可以由诸如玻璃、GaN、硅或聚丙烯(预浸渍)基板等的材料制成。在框204中，结构400A还包括用粘合剂308附贴在RDL 306上的桥管芯310。粘合剂308有助于在进一步的处理期间定位和保持桥管芯，从而允许方法200被执行。粘合剂308可以是通常用于引线接合技术中的有机或无机物质。
在框206中，结构400A还包括形成在桥芯片310与RDL 306相对的暴露表面330上的至少一个电互连件312。电互连件312、314允许在形成后续层(下面讨论)之后与RDL 306和桥管芯310进行连接。电互连件312、314有时被称为柱，并且可以由导电材料形成，导电材料诸如例如包括铜基材料、钨基材料和银基材料的金属和/或例如导电聚合物基材料等。典型地使用电镀工艺来形成电互连件312、314。在框208中，结构400A还包括延伸穿过RDL 306的至少一个穿模通孔(TMV)(图4C-4E中的406)的至少一个第一部分402。至少一个TMV 406的至少一个第一部分402可以由类似材料(金属、导电聚合物等)并用与电互连件312、314类似的工艺(包括电镀工艺等)形成。虽然未示出，但是至少一个TMV 406可以电连接到RDL 306。包括TMV是方法200相对于其它技术的另一个优点。
在框210中，如图4B所示的结构400B包括形成在RDL 306和桥管芯310上的第一模层316。在形成第一模层316之后可以采用平面化工艺诸如CMP以平面化第一模层316的顶表面360来进一步暴露电互连件312、314和至少一个TMV 406的至少一个第一部分402。在框212中，如图4C所示的结构400C包括至少一个TMV 406的至少一个第二部分404。至少一个TMV 406的至少一个第二部分404可以例如使用电镀工艺等形成，以在至少一个TMV 406的至少一个第一部分402上形成至少一个第二部分404。
在框214中，如图4D所示的结构400D包括放置在第一模层316上并经由电互连件312、314耦合到RDL 306和桥管芯310的多个管芯318、320。任选的集成无源器件(IPD)322(未示出)也可以与具有顶表面420的至少一个TMV 406一起放置在第一模层316的顶表面360上。在框216中，结构400D还包括形成在第一模层316上和多个管芯318、320上(以及任选的IPD上)的第二模层324。在形成第二模层324之后可以采用平面化工艺诸如CMP以平面化第二模层324的顶表面370来进一步暴露多个管芯318、320的顶表面380。平面化可以允许多个管芯的顶表面380与热交换层等之间的更好的接触(上面讨论)。
在框218中，如图4E所示的结构400E具有载体302，载体302从RDL306上去除(去接合)。例如球焊可以用于形成任选的球326以将RDL 306的下表面390连接到其它电路。如图4F所示的结构400F包括任选的半导体封装408，任选的半导体封装408经由由至少一个TMV406的顶表面420的球焊形成的任选的球410连接到至少一个TMV 406。至少一个TMV 406有利地允许支持封装层叠(PoP)电连接。
上述方法具有的优点是更高的管芯和桥管芯放置精度以及RDL相对于基于衬底的工艺的更严格的公差。该方法还具有与高温电介质相容的优点，因为首先构造RDL(不受管芯热预算限制)。该方法还具有的优点是使得OSAT能够在没有铸造厂协助的情况下在内部形成工艺。
虽然前述内容针对的是本原理的实施方式，但是也可在不脱离本原理的基本范围的情况下设计本原理的其它和进一步实施方式。
元件符号列表
100 方法
102 框
104 框
106 框
108 框
110 框
112 框
114 框
200 方法
202 框
204 框
206 框
208 框
210 框
212 框
214 框
218 框
300a-g 结构
302 载体
304 接合层
306 RDL
308 粘合剂
310 桥管芯
312 电互连件
314 电互连件
316 第一模层
318 多个管芯
320 多个管芯
322 集成无源器件
324 第二模层
326 任选的球
330 暴露的表面
350 任选的热交换层
354 印刷电路板
360 顶表面
370 顶表面
380 暴露的顶表面
390 下表面
394 顶表面
400a-f 结构
402 第一部分
404 一个第二部分
406 TMV
408 任选的半导体封装
410 任选的球

Claims (15)

1.一种形成晶片级桥管芯的方法，包括：
形成重分布层(RDL)；和
将桥管芯附贴在所述RDL上，所述桥管芯在与所述RDL相对的暴露表面上具有电连接。
2.如权利要求1所述的方法，还包括：
在载体上形成所述RDL。
3.如权利要求1所述的方法，还包括：
使用所述桥管芯与所述RDL之间的粘合剂将所述桥管芯附贴在所述RDL上。
4.如权利要求1所述的方法，还包括：
在所述RDL上形成至少一个电互连件；
在所述桥管芯上形成至少一个电互连件；
在所述RDL和所述桥管芯上面形成第一模层；和
将多个管芯耦接到所述RDL并耦接到所述桥管芯，使得管芯电连接到所述RDL的至少一个电互连件并电连接到所述桥管芯的至少一个电互连件。
5.如权利要求4所述的方法，还包括：
在所述第一模层上和在所述多个管芯上形成第二模层。
6.如权利要求4所述的方法，还包括：
在所述第一模层上形成至少一个集成无源器件；和
在所述第一模层上、在所述多个管芯上和在所述至少一个集成无源器件上形成第二模层。
7.如权利要求4所述的方法，还包括：
使用铜基材料在所述RDL上形成至少一个电互连件或在所述桥管芯上形成至少一个电互连件。
8.如权利要求1所述的方法，还包括：
在所述RDL上形成至少一个电互连件；
在所述桥管芯上形成至少一个电互连件；
在所述RDL上形成至少一个穿模通孔(TMV)的至少一个第一部分；
在所述RDL和所述桥管芯上面形成第一模层；
形成所述至少一个TMV的至少一个第二部分；
将多个管芯耦接到所述RDL并耦接到所述桥管芯，使得管芯电连接到所述RDL的至少一个电互连件并电连接到所述桥管芯的至少一个电互连件；和
在所述第一模层上和在所述多个管芯上形成第二模层，所述至少一个TMV在所述第二模层的顶表面处具有电连接以用于支持封装层叠(PoP)电连接。
9.一种形成晶片级桥管芯的方法，包括：
暂时地将重分布层(RDL)接合在载体上；
将桥管芯附贴在所述RDL上，所述桥管芯在与所述RDL相对的暴露表面上具有电连接；
在所述RDL上形成至少一个电互连件；
在所述桥管芯的所述暴露表面上形成至少一个电互连件；
在所述RDL和所述桥管芯上形成第一模层；
将多个管芯耦接到所述RDL并耦接到所述桥管芯，使得管芯电连接到所述RDL的至少一个电互连件并电连接到所述桥管芯的至少一个电互连件；
在所述第一模层上和在所述多个管芯上形成第二模层；和
从所述RDL去除所述载体。
10.如权利要求9所述的方法，还包括：
形成从所述RDL到所述第二模层的顶表面的至少一个穿模通孔。
11.一种用于连接半导体器件的设备，包括：
重分布层(RDL)；
桥管芯；
粘合剂层，插置在所述RDL与所述桥管芯之间；
在所述RDL上的至少一个电互连件；
在所述桥管芯上的至少一个电互连件；和
在所述RDL和所述桥管芯上的第一模层；。
12.如权利要求11所述的设备，还包括：
多个管芯，耦接到所述RDL并耦接到所述桥管芯，使得管芯电连接到所述RDL的所述至少一个电互连件中的至少一个并电连接到所述桥管芯的所述至少一个电互连件中的至少一个；和
在所述第一模层上和在所述多个管芯上的第二模层。
13.如权利要求11所述的设备，还包括：
多个管芯，耦接到所述RDL并耦接到所述桥管芯，使得管芯电连接到所述RDL的所述至少一个电互连件中的至少一个并电连接到所述桥管芯的所述至少一个电互连件中的至少一个；
在所述第一模层上的至少一个集成无源器件；和
在所述第一模层上、在所述多个管芯上和在所述至少一个集成无源器件上的第二模层。
14.如权利要求11所述的设备，还包括：
在所述RDL上的至少一个集成无源器件；和
在所述RDL上的至少一个穿模通孔(TMV)的至少一个第一部分；。
15.如权利要求14所述的设备，还包括：
所述至少一个TMV的至少一个第二部分；
多个管芯，耦接到所述RDL并耦接到所述桥管芯，使得管芯电连接到所述RDL的所述至少一个电互连件中的至少一个并电连接到所述桥管芯的所述至少一个电互连件中的至少一个；和
在所述第一模层上和在所述多个管芯上的第二模层，所述至少一个TMV在所述第二模层的顶表面处具有电连接以用于支持封装层叠(PoP)电连接。
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