CN112242367A - 封装件结构及其形成方法 - Google Patents

封装件结构及其形成方法 Download PDF

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Publication number
CN112242367A
CN112242367A CN202010686308.1A CN202010686308A CN112242367A CN 112242367 A CN112242367 A CN 112242367A CN 202010686308 A CN202010686308 A CN 202010686308A CN 112242367 A CN112242367 A CN 112242367A
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China
Prior art keywords
package
bridge die
redistribution
die
semiconductor substrate
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CN202010686308.1A
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English (en)
Inventor
余振华
苏安治
吴集锡
叶德强
叶名世
林宗澍
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN112242367A publication Critical patent/CN112242367A/zh
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Abstract

封装件结构包括桥式管芯。桥式管芯包括半导体衬底；以及位于半导体衬底上方的互连结构。互连结构包括介电层和位于介电层中的导线，将桥式管芯密封在其中的密封剂，以及位于桥式管芯上方的再分布结构。再分布结构中包括再分布线。第一封装组件和第二封装组件接合至再分布线。第一封装组件和第二封装组件通过再分布线和桥式管芯电互连。本发明的实施例还涉及形成封装件结构的方法。

Description

封装件结构及其形成方法
技术领域
本发明的实施例涉及封装件结构及其形成方法。
背景技术
随着集成电路的发展，越来越多的功能被内置到集成电路封装件中。因此，对在相邻器件管芯和封装件之间的局部通信和互连的要求也变得更加苛刻。
发明内容
本发明的一些实施例提供了一种封装件结构，包括：桥式管芯，包括：半导体衬底；以及互连结构，位于所述半导体衬底上方，其中，所述互连结构包括介电层和位于所述介电层中的导线；密封剂，将所述桥式管芯密封在其中；再分布结构，位于所述桥式管芯上方，其中，所述再分布结构中包括再分布线；以及第一封装组件和第二封装组件，接合至所述再分布线，其中，所述第一封装组件和所述第二封装组件通过所述再分布线和所述桥式管芯电互连。
本发明的另一些实施例提供了一种封装件结构，包括：第一再分布结构，所述第一再分布结构中包括第一再分布线；桥式管芯，位于所述第一再分布结构上方，其中，所述桥式管芯包括：半导体衬底；以及第一通孔，贯穿所述半导体衬底；第二通孔，位于所述第一再分布结构上方；密封剂，将所述桥式管芯和所述第二通孔密封在其中；第二再分布结构，位于所述桥式管芯上方，并且所述第二再分布结构中包括第二再分布线，其中，所述第一再分布线和所述第二再分布线通过所述第一通孔和所述第二通孔互连；以及第一封装组件和第二封装组件，位于所述第二再分布结构上方并且接合至所述第二再分布结构，其中，所述第一封装组件和所述第二封装组件通过桥式管芯电互连。
本发明的又一些实施例提供了一种形成封装件结构的方法，包括：将桥式管芯密封在密封剂中，所述桥式管芯包括：半导体衬底；以及互连结构，位于所述半导体衬底上方，其中，所述互连结构包括介电层和位于所述介电层中的金属线；在所述桥式管芯上方形成第一再分布结构，其中，所述第一再分布结构包括第一再分布线；以及将第一封装组件和第二封装组件接合至所述第一再分布线，其中，所述第一封装组件和所述第二封装组件通过所述第一再分布线和所述桥式管芯电互连。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图7示出了根据一些实施例在形成包括桥式管芯的封装件的中间阶段的截面图。
图8至图12示出了根据一些实施例在形成包括桥式管芯的封装件的中间阶段的截面图。
图13至图18示出了根据一些实施例在形成包括桥式管芯的封装件的中间阶段的截面图。
图19示出了根据一些实施例包括桥式管芯的封装件的截面图。
图20和图21示出了根据一些实施例包括桥式管芯的封装件的平面图。
图22示意性地示出了根据一些实施例的桥式管芯的布线方案。
图23和图24示出了根据一些实施例在包括通孔的桥式管芯的工艺期间的中间阶段的截面图。
图25示出了根据一些实施例用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而在此使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，提供了包括用于局部互连的桥式管芯的封装件及其形成方法。根据一些实施例示出了封装件形成中的中间阶段。讨论了一些实施例的一些变型。本文讨论的实施例将提供实例以使得能够制成或使用本发明的主题，并且本领域普通技术人员将容易理解可以进行的修改，同时保持在不同实施例的预期范围内。贯穿各个视图和示例性实施例，相同的参考标号用于指示相同的元件。尽管方法实施例可以被讨论为以特定顺序实施，但是其它方法实施例可以以任何逻辑顺序实施。根据本发明的一些实施例，将桥式管芯密封在密封剂中，在其上方形成包括再分布线的再分布结构。诸如器件管芯的两个封装组件接合至互连结构，并且通过桥式管芯互连。
图1至图7示出了根据本发明的一些实施例在封装件的形成中的中间阶段的截面图。相应的工艺也示意性地反映在图25所示的工艺流程中。
图1示出了载体20和形成在载体20上的释放膜22。载体20可以是玻璃载体、有机载体等。载体20可以具有圆形的顶视图形状，并且可以具有普通硅晶圆的尺寸。例如，载体20可以具有8英寸的直径、12英寸的直径等。释放膜22可以由基于聚合物的材料形成(诸如光热转换(LTHC)材料)，其能够与载体20一起从将在后续步骤中形成的上面结构去除。根据本发明的一些实施例，释放膜22由基于环氧树脂的热释放材料形成。释放膜22可以涂覆在载体20上。
如图1所示，形成金属柱24。尽管作为实例示出了一个金属柱24，但是可以形成多个金属柱24。根据本发明的一些实施例，金属柱24的形成包括沉积金属晶种层(未示出)，该金属晶种层可以包括钛层和位于钛层上方的铜层。可以是光刻胶的镀掩模(未示出)被涂覆在金属晶种层上，并且然后被图案化，使得金属晶种层的一些部分通过镀掩模中的多个开口暴露。下一步，将诸如铜的金属材料镀到开口中以及金属晶种层的暴露部分上。在镀工艺之后，去除镀掩模，暴露下面的金属晶种层的部分。然后蚀刻金属晶种层的暴露部分，留下所得的金属柱24，其包括镀的金属材料和金属晶种层的未蚀刻部分。
在形成金属柱24之后，将桥式管芯26放置在载体上方。相应的工艺在图25所示的工艺流程中示出为工艺204。桥式管芯26通过为粘合膜的管芯附接膜30附接至释放膜22。根据本发明的一些实施例，桥式管芯26包括半导体衬底128、通孔(也称为半导体通孔或硅通孔(TSV))134以及位于通孔134上方的互连结构130。互连结构130包括金属线和电连接至通孔134的通孔。金属柱28位于桥式管芯26的顶面处，并且还电连接至金属线、通孔和通孔134。
图22示出了根据一些实施例的桥式管芯26的布线方案的示意图。桥式管芯26具有使随后接合的封装组件(诸如图2中所示的封装组件46A和46B)互连的功能。根据本发明的一些实施例，桥式管芯26包括衬底128，其可以是诸如硅衬底的半导体衬底，或者可以是由例如氧化硅、氮化硅等形成的介电衬底。衬底128也可以是由诸如氧化硅、氮化硅等的介电材料形成的介电衬底。
根据本发明的一些实施例，桥式管芯26中没有有源器件，诸如晶体管和二极管。根据本发明的可选实施例，桥式管芯26包括有源器件，该有源器件可以形成在半导体衬底128的顶面处。桥式管芯26中的相应电路可以包括存储电路、逻辑电路等。根据本发明的一些实施例，桥式管芯26包括无源器件137，诸如电容器、变压器、电感器、电阻器和/或等，其被示意性地示出。根据本发明的其它实施例，桥式管芯26没有无源器件。因此，使用虚线示出了无源器件137，以指示无源器件137可以存在或不存在于桥式管芯26中。桥式管芯26中可以没有有源器件和无源器件。
桥式管芯26还包括互连结构130，该互连结构130还包括介电层131以及介电层131中的金属线和通孔132。介电层131可以包括金属间介电(IMD)层。根据本发明的一些实施例，介电层131中的一些下部介电层由介电常数(k值)小于约3.0的低k介电材料形成。介电层131可以由黑金刚石(应用材料的注册商标)、含碳的低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等形成。根据本发明的一些实施例，介电层131的形成包括沉积含致孔剂的介电材料，然后实施固化工艺以驱除致孔剂，并且因此剩余的介电层131是多孔的。可以由碳化硅、氮化硅等形成的蚀刻停止层(未示出)形成在IMD层131之间，并且为了简单起见未示出。
在介电层131中形成金属线和通孔132。形成工艺可以包括单镶嵌和双镶嵌工艺。在示例性单镶嵌工艺期间，首先在介电层131的一个中形成沟槽，以及随后用导电材料填充沟槽。然后实施诸如化学机械抛光(CMP)工艺的平坦化工艺以去除高于对应介电层的顶面的导电材料的过量部分，从而在沟槽中留下金属线。在双镶嵌工艺期间，在IMD层中形成沟槽和通孔开口，其中，通孔开口位于沟槽下面并且连接至沟槽。然后将导电材料填充至沟槽和通孔开口中以分别形成金属线和通孔。导电材料可以包括扩散阻挡层和在扩散阻挡层上方的含铜金属材料。扩散阻挡层可以包括钛、氮化钛、钽、氮化钽等。金属线和通孔132还可包括形成在钝化层中的一些部分。
桥式管芯26还可以包括位于低k介电层131上方的钝化层(也表示为131)。钝化层具有将下面的低k介电层(如果有)与有害化学物质和水分隔离的功能。钝化层可以由非低k介电材料形成，诸如氧化硅、氮化硅、未掺杂硅酸盐玻璃(USG)等。在钝化层中可以存在诸如铝焊盘的金属焊盘(例如，其可以由铝铜形成)。接合焊盘(或金属柱)28形成在桥式管芯26的表面处。金属柱28可以由铜、铝、镍、钯等、它们的多层或它们的合金形成。
根据本发明的一些实施例，一些金属柱28通过金属线和通孔132、金属焊盘等直接连接至其它金属柱28。可以存在多对金属柱28，其中，一对中的每个金属柱28电连接至该对中的另一金属柱28。在整个说明书中，成对的金属柱28中的一个表示为28A，而另一个表示为28B。当两个金属柱28互连时，在金属柱28A和28B之间可以不连接任何电阻器、电容器、电感器等。因此，同一对中的金属柱28A和28B彼此电短路。另一方面，如果需要，无源器件137(诸如电容器、电阻器、电感器等)也可以成对插入在金属柱28A和28B之间，并且无源器件和金属柱28A和28B可以串联连接。
图23示出了根据本发明的一些实施例的桥式管芯26的截面图。桥式管芯26的布线方案可以参考图22。截面图示出了金属线和通孔132。根据一些实施例，可以在金属柱28上方形成聚合物层29(可以由聚苯并恶唑(PBO)、聚酰亚胺等形成)。根据可选实施例，没有形成将金属柱28嵌入其中的含聚合物介电层。
根据本发明的一些实施例，如图23所示，TSV 134被形成为延伸至衬底128中。每个TSV 134可以由隔离衬垫136围绕，隔离衬垫136由诸如氧化硅、氮化硅等的介电材料形成。隔离衬垫136将相应TSV 134与半导体衬底128隔离。TSV 134和隔离衬垫136从半导体衬底128的顶面延伸至在半导体衬底128的顶面和底面之间的中间水平。根据一些实施例，TSV134的顶面与半导体衬底128的顶面齐平。根据可选实施例，TSV 134延伸至介电层131的一个中，并且从相应的介电层131的顶面向下延伸至半导体衬底128中。
根据本发明的可选实施例，不管衬底128是由半导体还是介电材料形成，都没有形成贯穿衬底128的通孔。在图8至图18的实施例中示出了相应的桥式管芯26。
再次参考图1，当放置桥式管芯26时，其它封装组件(包括但不限于封装件、器件管芯、独立无源器件(IPD)等)也可以通过DAF放置在释放膜22上方。例如，封装组件32可以被放置在与桥式管芯26相同的水平处，并且通过DAF 34放置在释放膜22上方。根据其它实施例，不存在与桥式管芯26放置在相同的水平处的其它封装组件，诸如器件管芯、封装件、IPD等。因此，封装组件32使用虚线示出以指示其可以放置或可以不放置。封装组件32(如果放置)在其表面包括金属柱36。根据一些实施例，封装组件32是或包括存储器管芯、逻辑管芯、封装件、IPD等。
作为实例，图1示出了聚合物层29形成在桥式管芯26中，而没有形成将金属柱36嵌入其中的聚合物。应该理解，放置在释放膜22上方的封装组件和桥式管芯的每个都可以包括或可以不包括用于嵌入相应金属柱的聚合物。
桥式管芯26和封装组件32(如果放置)密封在密封剂38中，密封剂38可以由或包括模塑料、模制底部填充物、环氧树脂、树脂等形成。相应的工艺示出为图25所示的工艺流程中的工艺206。密封剂38可以包括可以是树脂和/或聚合物的基底材料以及位于该基底材料中的填料颗粒。填料颗粒可以由诸如二氧化硅或氧化铝的介电材料形成，其可以是球形颗粒。在密封之后，密封剂38覆盖桥式管芯26和封装组件32。然后实施平坦化工艺以去除密封剂38的过量部分，从而暴露金属柱28和36。平坦化工艺可以是化学机械抛光(CMP)工艺或机械研磨工艺。根据其中金属柱36不位于聚合物层中的本发明的一些实施例，密封剂38流入金属柱36之间的空间。
图1还示出了再分布结构40的形成，该结构包括介电层44和再分布线(RDL)42。相应的工艺示出为图25所示的工艺流程中的工艺208。根据一些实施例，介电层44由诸如PBO、聚酰亚胺等的聚合物形成。形成方法包括以可流动形式涂覆介电层44，并且然后固化相应的介电层。根据本发明的可选实施例，介电层44由无机介电材料形成，诸如氮化硅、氧化硅、碳化硅、它们的多层、它们的组合等。形成方法可以包括涂覆、化学汽相沉积(CVD)、原子层沉积(ALD)、等离子体增强化学汽相沉积(PECVD)或其它适用的沉积方法。
RDL 42包括延伸至相应介电层44中的通孔部分，以及位于相应介电层44上方的迹线部分。形成工艺可以包括图案化相应介电层44以形成开口，形成毯式金属晶种层(未示出)，形成并且图案化镀掩模(诸如光刻胶)以露出金属晶种层的一些部分，在镀掩模的开口中镀RDL 42，去除镀掩模，并且蚀刻先前由镀掩模覆盖的部分金属晶种层。根据本发明的一些实施例，金属晶种层包括钛层和位于钛层上方的铜层。金属晶种层的形成可以包括例如，物理汽相沉积(PVD)。根据本发明的一些实施例，镀材料包括铜、铝、铝铜或铜合金。镀可以包括电化学镀或化学镀。在整个说明书中，介电层44和形成在其中的RDL 42的组合称为再分布结构40。可以形成一层、两层或更多层的RDL 42。RDL 42电连接至金属柱28和36以及通孔24。根据一些实施例，在再分布结构40的表面处形成接合焊盘或凸块下金属(UBM)，并且也表示为42。
下一步，参考图2，例如通过焊料区域48将封装组件46(包括46A和46B，它们统称为和分别称为46)接合至再分布结构40的接合焊盘上。相应的工艺示出为图25所示的工艺流程中的工艺210。封装组件46A和46B中的每个可以是或包括逻辑器件管芯、存储器件管芯、存储器堆叠件(诸如高带宽存储器(HBM)堆叠件)、IPD等。
根据一些实施例，封装组件46A和46B两者均电连接至相同的桥式管芯26，并且通过桥式管芯26和RDL 42中的电路径互连。例如，如图22所示，桥式管芯26包括多对金属柱28A和28B，其中同一对中的金属柱28A和金属柱28B被定向电连接。金属柱28A可以通过上面的RDL 42直接连接至封装组件46A中的接合焊盘，并且金属柱28B可以通过上面的RDL 42直接连接至封装组件46B中的接合焊盘。因此，图2和图22的组合示出了桥式管芯26将封装组件46A和46B电互连。使用桥式管芯26(而不是仅使用RDL 42)互连封装组件46A和46B的一个有利特征是，桥式管芯26中的金属线和通孔可以使用用于形成器件管芯的相同技术来形成，其包括例如，镶嵌工艺。因此，由于RDL 42的间距和线宽明显大于桥式管芯26中的间距和线宽，因此通过使用桥式管芯26，相交的线间距和线长度可能非常小，并且可用互连的总数量比仅使用RDL 42来实施互连显著更多。根据一些实施例，封装组件46A和46B的连接路径内的RDL 42用于从封装组件46A和46B至下面的金属柱28的垂直连接，并且这些RDL42不具有水平布线功能。因此，使封装组件46A和46B互连的所有电路径均穿过桥式管芯。根据本发明的一些实施例，使封装组件46A和46B互连的一些电路径穿过RDL 42而没有穿过桥式管芯26，而其它电路径则穿过桥式管芯26。而且，封装组件46A中的一些接合焊盘和/或封装组件46B中的一些接合焊盘可以电连接至通孔134。
在接合之后，将底部填充物50分配在封装组件46和再分布结构40之间，然后固化。然后将诸如模塑料的密封剂52密封在封装组件46A和46B上。相应的工艺示出为图25所示的工艺流程中的工艺212。根据一些实施例，代替分别施加底部填充物50和密封剂52，施加并且固化模制底部填充物。在密封工艺之后，实施诸如化学机械抛光(CMP)工艺的平坦化工艺。平坦化工艺可以在仍然有密封剂52的层覆盖封装组件46A和46B时停止。在封装组件46A和46B上方留下一些密封剂52可以使所得的封装件保持足够厚以用于后续工艺，并且可以在图3和图4所示的工艺期间保护封装组件46A和46B的背面。
然后实施载体交换，其中如图2所示的封装件通过如图3所示的释放膜56附接至载体54。相应的工艺示出为图25所示的工艺流程中的工艺214。然后，例如通过将辐射(诸如激光束)投射至释放膜22(图2)上，将载体20从上面的结构剥离，使得释放膜22分解，从而释放载体20。产生的结构如图3所示。
在随后的工艺期间，实施减薄工艺以去除DAF 30、位于通孔134下面的衬底128的部分以及绝缘衬垫136(图23)，直至露出通孔134的端部。密封剂38和通孔24(图3)的相应部分也被抛光。可以形成(或可以不形成)覆盖暴露的衬底128的介电层，并且图24示出了桥式管芯26和密封剂38的相应部分的细节，其中，示出了介电层135。产生的结构也如图4所示。
图4还示出了再分布结构58的形成，其包括介电层60和RDL 62。相应的工艺示出为图25所示的工艺流程中的工艺216。介电层60和RDL 62的形成工艺和候选材料与介电层44和RDL 42的形成工艺和候选材料相似，并且因此在此不再重复细节。然后在RDL 62上方形成电连接至RDL 62的电连接件64。相应的工艺也示出为图25所示的工艺流程中的工艺216。电连接件64可以包括金属柱和金属柱上的预焊料区域，或者可以包括与RDL62接触的焊料区域。在整个说明书中，释放膜56上方的部件统称为重构晶圆66。
然后，例如通过将辐射(诸如激光束)投射在释放膜56上，使得释放膜56分解，从而释放载体54来将载体54从重构晶圆66上剥离。相应的工艺示出为图25所示的工艺流程中的工艺218。产生的重构晶圆66在图5中示出。在随后的工艺期间，实施分割工艺(诸如锯切工艺)以将重构晶圆66分成多个封装件66’。相应的工艺示出为图25所示的工艺流程中的工艺220。
参考图6，例如通过焊料接合将封装件66’接合至封装衬底68。相应的工艺示出为图25所示的工艺流程中的工艺222。根据本发明的一些实施例，多个封装件66’接合至多个封装衬底68，这些封装衬底是封装衬底带的集成部分。封装衬底68可以是无芯衬底或有芯衬底。焊料区域70可以形成在衬底68的底部处。焊料区域70可以电连接至通孔24和134，并且可以电连接至封装组件46。分配密封剂82，并且然后固化以将封装件66’密封在其中。密封剂82可以包括模塑料、模制底部填充物等。然后实施分割工艺以分割相应结构并且形成多个封装件72。相应的工艺示出为图25所示的工艺流程中的工艺224。
图7示出了根据一些实施例的封装件72，其中DAF 34可具有留在最终封装件72中的一部分。根据一些实施例，在图1所示的结构中，封装组件32比桥式管芯26薄，并且DAF 34比DAF 30厚。因此，在对图2所示的结构实施减薄工艺之后，DAF 34的一些部分留下，如图7所示。图7还示出了封装组件46A是其中包括多个存储器管芯46’的存储器堆叠件。底部填充物47可以形成在多个存储器管芯46’之间，并且密封剂49还在其中密封存储器管芯46’。
如图6和图7所示，通孔24贯穿密封剂38。在相同的封装件中，通孔134贯穿桥式管芯26的衬底128。通孔24和134均具有使RDL 42和62互连的功能。应该理解，通孔24可以在封装件72中占据相对小的芯片面积，并且布线来自远离桥式管芯26的RDL 42的信号意味着布线路径很长。因此，通孔24用于缩短布线路径。
图8至图12示出了根据本发明的一些实施例在封装件的形成中的中间阶段的截面图。这些实施例类似于图1至图7所示的实施例，不同之处在于IPD接合至再分布结构40，并且桥式管芯26中没有通孔。除非另有说明，否则这些实施例中的组件的材料和形成工艺与相同的组件基本相同，在图1至图7所示的先前实施例中，由相同的参考标号表示。因此，可以在先前实施例的讨论中找到关于图8至图12(以及图13至图18)所示的组件的形成工艺和材料的细节。
参考图8，首先在载体20上方的释放膜22上形成再分布结构58。再分布结构58包括介电层60和再分布线62。通孔24形成在再分布结构58上方。使用DAF 30将桥式管芯26放置在释放膜22上方。桥式管芯26可具有与图22和图23所示的基本相同的结构，除了未形成如图23所示的通孔134。下一步，在平坦化工艺中平坦化密封剂38，然后形成再分布结构40。在随后的工艺中，封装组件46A和46B例如通过焊料接合而接合至再分布结构40。封装组件46A和46B也通过RDL 42和桥式管芯26彼此互连。
IPD 74例如通过焊料接合而接合至再分布结构40的表面。IPD 74可以包括电容器、电感器、电阻器等。根据本发明的一些实施例，IPD 74中的一些或全部可以是离散的IPD管芯，其中可以没有有源器件。一些IPD管芯74中可以仅包括单个无源器件。将IPD 74接合至再分布结构40与传统的接合方案不同，在传统的接合方案中，IPD接合至封装衬底，例如，如图12所示的封装衬底68。将IPD管芯74接合至再分布结构40使得芯片面积的有效利用，并且封装衬底的尺寸可以减小，从而使得产生的封装件的覆盖区减小。
参考图9，分配底部填充物50，并且将封装组件46和IPD 74密封在密封剂52中。然后平坦化密封剂52，直至暴露封装组件46的顶面。由此形成重构晶圆66。下一步，实施剥离工艺，并且将重构晶圆66从载体20剥离。
图10示出了重构晶圆66在带76上的放置，带76固定在框架78上。现在，再分布结构58中的介电层60是顶面层，然后对其进行图案化，例如，在激光钻孔工艺或蚀刻工艺期间，以露出RDL 62中的一些接合焊盘。在图11中，封装衬底68例如通过焊料区域接合至重构晶圆66。尽管示出了一个封装衬底68，但是有多个相同的封装衬底68接合至重构晶圆66。该工艺与传统工艺不同，在传统的工艺中，首先将封装件分割为离散的封装件，并且然后将离散的封装件接合至包括多个封装衬底的集成封装衬底带。
图12示出了封装衬底68上的电连接件70的形成。然后实施分割工艺以将重构晶圆66锯切成多个离散的封装件72。重构晶圆66也被分割为封装件66’。每个离散的封装件72包括封装组件46A和46B、桥式管芯26和封装衬底68。
如图12所示，IPD 74接合至再分布结构40，而不是接合至封装衬底68。这使得可以分割封装衬底，并且然后将分割的封装衬底接合至(晶圆级)重构晶圆66。因此，封装衬底68的尺寸可以减小至与封装件66’相同或小于封装件66’。而且，IPD 74接合至再分布结构40，而不是接合至封装衬底68，从而还可以减小封装衬底68的尺寸。例如，封装衬底68的长度L1(或宽度)可以等于或小于封装件66’的长度L2(或宽度)。这与传统的封装件不同，在传统的封装件中，封装衬底比接合至它们的封装件大，这是因为封装件是离散的封装件，并且被接合至包括多个封装衬底的集成封装衬底带上。
图13至图18示出了根据可选实施例的封装件72的形成。这些实施例与图8至图12中的实施例相似，除了没有接合IPD 74之外。而且，与图8至图12所示的实施例不同，在图13至图18的实施例中，首先形成离散的封装件66’，然后将其接合至封装衬底带上。该工艺简要讨论如下。
参考图13，在载体20和释放膜22上方形成再分布结构58。再分布结构58包括介电层60和延伸至介电层60中的RDL 62。形成工艺和材料可以分别选自用于形成介电层44和RDL 42的候选形成工艺和材料，如图1所示。下一步，在再分布结构58上方形成电连接至RDL62的通孔24。桥式管芯26通过DAF 30放置在再分布结构58上方。然后，将通孔24和桥式管芯26密封在密封剂38中。然后形成再分布结构40。再分布结构40中的RDL 42电连接至桥式管芯26和通孔24。
参考图14，例如，通过焊料接合将封装组件46A和46B接合至再分布结构40。封装组件46A和46B也通过RDL 42和桥式管芯26彼此互连。分配底部填充物50，并且将封装组件46A和46B密封在密封剂52中。然后平坦化密封剂52。根据一些实施例，在平坦化之后，封装组件46仍然由一些密封剂52覆盖。根据可选实施例，封装组件46A和46B中的至少一个，并且也可能是两个的背面暴露。由此形成重构晶圆66。下一步，实施剥离工艺，并且将重构晶圆66从载体20剥离。
图15示出了载体交换工艺，其中，图14中所示的载体20被剥离，并且重构晶圆66通过释放膜56附接至载体54。在如图16所示的后续工艺期间，形成电连接件64。然后将重构晶圆66从载体54剥离，并且所得的重构晶圆66在图17中示出。然后实施分割以将重构晶圆66分割为封装件66’。
参考图18，例如，通过焊料接合将封装件66’接合至封装衬底68。根据本发明的一些实施例，多个封装件66’接合至封装衬底带中的多个封装衬底68。施加密封剂82以将多个封装件66’密封在其中。密封剂82可以包括模塑料、模制底部填充物等。然后分割封装衬底带和密封剂82以形成多个封装件72。
图19示出了根据一些实施例的封装件72。除了桥式管芯26和通孔24之外，还示出了附加管芯。例如，IPD管芯74’、存储器管芯46C(可以是静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等)以及输入/输出(I/O)管芯46D也密封在密封剂38中，并且电连接至再分布结构40。根据一些实施例，封装组件46A是包括堆叠在一起的多个存储器管芯46’的存储器堆叠件。根据本发明的一些实施例，I/O管芯46D中包括TSV 134’，其将再分布结构40和58电互连。通孔24’形成在再分布结构40上方，并且贯穿密封剂58。其中可以包括存储器管芯、存储器堆叠件等的封装件86例如通过焊料区域88接合至通孔24。
应当理解，如图19所示的IPD管芯74’、存储器管芯46C和I/O管芯46D也可以被合并至如图6、图7、图12和图18所示的封装件72中。此外，尽管示出的桥式管芯26位于再分布结构40下方，并且互连的封装组件46A和46B接合至再分布结构40，但是可以采用其它方案。例如，桥式管芯26可以位于互连结构40上方并且接合至再分布结构40，而封装组件46A和46B可以密封在密封剂38中，其中，再分布结构40形成在封装组件46A和46B上。
图20示出了根据一些实施例的封装件72的平面图。封装组件46A可以具有彼此相同或彼此不同的结构和电路。封装组件46B可以具有彼此相同或彼此不同的结构和电路。多个桥式管芯26将封装组件46A接合至相应的封装组件46B。每个桥式管芯26将至少一对封装组件46A和46B互连。根据一些实施例，如图20所示，一个桥式管芯26可以将两个封装组件46A连接至相同的封装组件46B。两个封装组件46A还可以通过桥式管芯26彼此互连。此外，桥式管芯26可以互连两个封装组件46B。图21示出了根据一些实施例的封装件72的平面图。这些实施例与图20所示的实施例相似，除了每个桥式管芯26连接至一对封装组件46之外。
在以上示出的实施例中，根据本发明的一些实施例讨论了一些工艺和部件以形成三维(3D)封装件。也可以包括其它部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘，以允许使用探针和/或探针卡等测试3D封装件或3DIC。可以在中间结构以及最终结构上实施验证测试。此外，本文公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合使用，以提高良率并且降低成本。
本发明的实施例具有一些有利特征。通过使用桥式管芯来互连封装组件，与仅将RDL用于互连相比，可以在两个封装组件之间建立的电连接的可用数量显著增加。这是由于桥式管芯中的连接处的间距和线宽较小。形成在桥式管芯上方的互连结构还提供了平坦的表面，以平整桥式管芯和其它器件管芯的不同厚度，使得封装组件可以容易地布置。
根据本发明的一些实施例，结构包括桥式管芯，桥式管芯包括半导体衬底；以及半导体衬底上方的互连结构，其中，互连结构包括介电层和介电层中的导线；将桥式管芯密封在其中的密封剂；位于桥式管芯上方的再分布结构，其中，再分布结构中包括再分布线；以及接合至再分布线的第一封装组件和第二封装组件，其中，第一封装组件和第二封装组件通过再分布线和桥式管芯电互连。在实施例中，桥式管芯中没有有源器件。在实施例中，桥式管芯还包括贯穿半导体衬底的第一通孔。在实施例中，该结构还包括贯穿密封剂的第二通孔。在实施例中，结构还包括接合至再分布结构的无源器件管芯。在实施例中，桥式管芯包括与第一封装组件重叠的第一部分和与第二封装组件重叠的第二部分。在实施例中，互连第一封装组件和第二封装组件的所有电路径均通过桥式管芯。在实施例中，结构还包括位于桥式管芯的与第一封装组件相对的侧上的封装衬底，其中封装衬底电耦接至第一封装组件，并且其中封装衬底的侧壁从密封剂的相应侧壁横向凹进。
根据本发明的一些实施例，结构包括第一再分布结构，该第一再分布结构中包括第一再分布线；位于第一再分布结构上方的桥式管芯，其中，桥式管芯包括半导体衬底；以及贯穿半导体衬底的第一通孔；位于第一再分布结构上方的第二通孔；将桥式管芯和第二通孔密封在其中的密封剂；位于桥式管芯上方并且其中包括第二再分布线的第二再分布结构，其中第一再分布线和第二再分布线通过第一通孔和第二通孔互连；以及位于第二再分布结构上方并且接合至第二再分布结构的第一封装组件和第二封装组件，其中第一封装组件和第二封装组件通过桥式管芯电互连。在实施例中，桥式管芯中没有有源器件和无源器件。在实施例中，结构还包括器件管芯；以及位于器件管芯和第一再分布结构之间并且接触器件管芯和第一再分布结构的粘合膜。
根据本发明的一些实施例，方法包括将桥式管芯密封在密封剂中，桥式管芯包括半导体衬底；以及位于半导体衬底上方的互连结构，其中，互连结构包括介电层和位于介电层中的金属线；在桥式管芯上方形成第一再分布结构，其中，第一再分布结构包括第一再分布线；并且将第一封装组件和第二封装组件接合至第一再分布线，其中，第一封装组件和第二封装组件通过第一再分布线和桥式管芯电互连。在实施例中，该方法还包括形成金属柱，其中，金属柱由密封剂密封；并且在半导体衬底的背侧上形成第二再分布线，其中第一再分布线和第二再分布线通过金属柱互连。在实施例中，桥式管芯还包括延伸至半导体衬底中的通孔，并且该方法还包括实施背侧研磨以露出通孔，其中，第一再分布线和第二再分布线还通过通孔互连。在实施例中，该方法还包括对密封剂和再分布结构实施分割工艺以形成多个封装件；将封装件接合至封装衬底带上；并且分割封装衬底带。在实施例中，该方法还包括形成第二再分布结构，其中第一再分布结构和第二再分布结构位于桥式管芯的相对侧上；在第二再分布结构上接合多个离散的封装衬底；并且对密封剂、第一再分布结构和第二再分布结构实施分割工艺，以形成多个离散的封装件。在实施例中，该方法还包括将桥式管芯放置在释放膜上方，其中，释放膜位于载体上方；在形成第一再分布线之后，去除释放膜和载体；并且实施背侧研磨工艺以露出桥式管芯中的通孔。在实施例中，该方法还包括放置器件管芯，其中器件管芯通过粘合膜放置在释放膜上，并且器件管芯和粘合膜密封在密封剂中，并且其中在背侧研磨工艺之后，一部分粘合膜保留在密封剂中。在实施例中，该方法还包括将无源器件接合在第一再分布结构上。在实施例中，桥式管芯中没有有源器件。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的前提下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种封装件结构，包括：
桥式管芯，包括：
半导体衬底；以及
互连结构，位于所述半导体衬底上方，其中，所述互连结构包括介电层和位于所述介电层中的导线；
密封剂，将所述桥式管芯密封在其中；
再分布结构，位于所述桥式管芯上方，其中，所述再分布结构中包括再分布线；以及
第一封装组件和第二封装组件，接合至所述再分布线，其中，所述第一封装组件和所述第二封装组件通过所述再分布线和所述桥式管芯电互连。
2.根据权利要求1所述的封装件结构，其中，所述桥式管芯中没有有源器件。
3.根据权利要求1所述的封装件结构，其中，所述桥式管芯还包括：
第一通孔，贯穿所述半导体衬底。
4.根据权利要求3所述的封装件结构，还包括，贯穿所述密封剂的第二通孔。
5.根据权利要求1所述的封装件结构，还包括，接合至所述再分布结构的无源器件管芯。
6.根据权利要求1所述的封装件结构，其中，所述桥式管芯包括与所述第一封装组件重叠的第一部分，以及与所述第二封装组件重叠的第二部分。
7.根据权利要求1所述的封装件结构，其中，使所述第一封装组件和所述第二封装组件互连的所有电路径均贯穿所述桥式管芯。
8.根据权利要求1所述的封装件结构，还包括，位于所述桥式管芯的与所述第一封装组件相对的侧上的封装衬底，其中，所述封装衬底电耦接至所述第一封装组件，并且其中，所述封装衬底的侧壁从所述密封剂的相应侧壁横向凹进。
9.一种封装件结构，包括：
第一再分布结构，所述第一再分布结构中包括第一再分布线；
桥式管芯，位于所述第一再分布结构上方，其中，所述桥式管芯包括：
半导体衬底；以及
第一通孔，贯穿所述半导体衬底；
第二通孔，位于所述第一再分布结构上方；
密封剂，将所述桥式管芯和所述第二通孔密封在其中；
第二再分布结构，位于所述桥式管芯上方，并且所述第二再分布结构中包括第二再分布线，其中，所述第一再分布线和所述第二再分布线通过所述第一通孔和所述第二通孔互连；以及
第一封装组件和第二封装组件，位于所述第二再分布结构上方并且接合至所述第二再分布结构，其中，所述第一封装组件和所述第二封装组件通过桥式管芯电互连。
10.一种形成封装件结构的方法，包括：
将桥式管芯密封在密封剂中，所述桥式管芯包括：
半导体衬底；以及
互连结构，位于所述半导体衬底上方，其中，所述互连结构包括介电层和位于所述介电层中的金属线；
在所述桥式管芯上方形成第一再分布结构，其中，所述第一再分布结构包括第一再分布线；以及
将第一封装组件和第二封装组件接合至所述第一再分布线，其中，所述第一封装组件和所述第二封装组件通过所述第一再分布线和所述桥式管芯电互连。
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