CN111128750B - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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CN111128750B
CN111128750B CN201910293131.6A CN201910293131A CN111128750B CN 111128750 B CN111128750 B CN 111128750B CN 201910293131 A CN201910293131 A CN 201910293131A CN 111128750 B CN111128750 B CN 111128750B
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polymer layer
redistribution
forming
polymer
layer
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CN111128750A (zh
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陈世明
苏竟典
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例提供了一种形成半导体器件的方法，包括在晶圆的半导体衬底上方形成多个金属焊盘，形成覆盖多个金属焊盘的钝化层，图案化钝化层以露出多个金属焊盘，在钝化层上方形成第一聚合物层，形成多条再分布线，再分布线延伸至第一聚合物层和钝化层中以连接至多个金属焊盘，在第一聚合物层上方形成第二聚合物层，以及图案化第二聚合物层以露出多条再分布线。第一聚合物层通过第二聚合物层的剩余部分中的开口进一步露出。本发明实施例还涉及一种半导体器件。

Description

半导体器件及其形成方法
技术领域
本发明的实施例总体涉及半导体领域，更具体地，涉及半导体器件及其形成方法。
背景技术
在集成电路的形成中，在晶圆中的半导体衬底的表面处形成诸如晶体管的器件。然后在集成电路器件上方形成互连结构。金属焊盘形成在互连结构上方并且电连接至互连结构。钝化层和第一聚合物层形成在金属焊盘上方，金属焊盘通过钝化层和第一聚合物层中的开口暴露。
然后形成再分布线以连接至金属焊盘的顶面，接着在再分布线上方形成第二聚合物层。形成延伸至第二聚合物层中的开口中的凸块下金属(UBM)，其中，UBM电连接至再分布线。然后将焊球放置在UBM上方并回流。
发明内容
根据本发明的一些实施例，提供了一种形成半导体器件的方法，所述方法包括：在晶圆的半导体衬底上方形成多个金属焊盘；形成覆盖所述多个金属焊盘的钝化层；图案化所述钝化层以露出所述多个金属焊盘；在所述钝化层上方形成第一聚合物层；形成延伸至所述第一聚合物层和所述钝化层中以连接至所述多个金属焊盘的多条再分布线；在所述第一聚合物层上方形成第二聚合物层；以及图案化所述第二聚合物层以露出所述多条再分布线，其中，所述第一聚合物层进一步通过所述第二聚合物层的剩余部分中的开口暴露。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，所述方法包括：在无机钝化层上方形成第一聚合物层；形成多条再分布线，每条再分布线包括在所述第一聚合物层上方的第一部分和延伸至所述第一聚合物层中的第二部分，其中，所述多条再分布线物理上彼此分开；在所述多条再分布线上方涂布第二聚合物层；将所述第二聚合物层图案化成彼此分开的多个离散部分，多个所述离散部分中的每一个覆盖所述多条再分布线中的一个；以及形成延伸至所述第二聚合物层的多个所述离散部分中以接触所述多条再分布线的多个凸块下金属(UBM)。
根据本发明的另一些实施例，还提供了一种半导体结构，包括：第一封装组件，包括：介电层；第一聚合物层，在所述介电层上方；多条再分布线，每条再分布线包括在所述第一聚合物层上方的第一部分和延伸至所述第一聚合物层中的第二部分，其中，所述多条再分布线物理上彼此分开；图案化的第二聚合物层，包括彼此分开的多个离散部分，多个所述离散部分中的每一个覆盖所述多条再分布线中的一个；以及多个凸块下金属(UBM)，延伸至所述图案化的第二聚合物层的多个所述离散部分中以接触所述多条再分布线。
附图说明
当结合附图进行阅读时，从以下详细描述可以最佳理解本发明的各个方面。应注意到，根据本行业中的标准惯例，各种部件未按比例绘制。事实上，为了清楚的讨论，可以任意地增加或减少各种部件的尺寸。
图1至图3、图4A、图4B、图5、图6A、图6B、图6C、图7至图9示出了根据一些实施例的形成封装件的中间阶段的截面图。
图10至图13示出了根据一些实施例的顶部聚合物层中的开口的顶视图。
图14示出了根据一些实施例的封装件的一部分的截面图。
图15至图23示出了根据一些实施例的形成包括密封器件管芯和通孔的封装件的中间阶段的截面图。
图24示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开提供了多种不同实施例或实例用于实现本发明的不同特征。下面描述了组件和布置的具体实例，以简化本发明。当然，这些仅仅是实例而不旨在限制。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括附加部件形成在第一部件和第二部件之间，使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个实例中可以重复参考标号和/或字母。该重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在...下面”、“在...下方”、“下部”、“在...上面”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。空间相对术语旨在包括除了附图中所示的方位之外，在使用中或操作中的器件的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据一些实施例，提供了一种封装件及其形成方法。根据一些实施例，示出了形成封装件的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和示例性实施例，相同的参考标号用于表示相同的元件。根据本发明的一些实施例，图案化封装件或器件管芯中的顶部聚合物层，以减小顶部聚合物层施加到下层的应力，从而提高封装件的可靠性。
图1至图3、图4A、图4B、图5、图6A、图6B、图6C、图7至图9示出了根据一些实施例的形成封装件的中间阶段的截面图和顶视图。相应的工艺也示意性地反映在图24所示的工艺流程200中。
图1示出了封装组件20的截面图。根据本发明的一些实施例，封装组件20是包括有源器件和可能的无源器件的器件晶圆，无源器件被表示为集成电路器件26。器件晶圆20可以在其中包括多个芯片22，其中示出了芯片22中的一个。根据本发明的可选实施例，封装组件20是可以或可以不包括有源器件和/或无源器件的中介晶圆。根据本发明的又一些替代实施例，封装组件20是封装衬底条，其包括无芯封装衬底或其中具有芯的封装衬底。在后续讨论中，所讨论的器件晶圆作为封装组件20的实例。本发明的实施例还可以应用于中介晶圆、封装衬底、封装件等。
根据本发明的一些实施例，晶圆20包括半导体衬底24和在半导体衬底24的顶面处形成的部件。半导体衬底24可以由晶体硅、晶体锗、硅锗或诸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等的III-V族化合物半导体形成。半导体衬底24也可以是块状半导体衬底或绝缘体上半导体(SOI)衬底。可以在半导体衬底24中形成浅沟槽隔离(STI)区域(未示出)以隔离半导体衬底24中的有源区域。尽管未示出，可以形成通孔以延伸至半导体衬底24中，其中，使用通孔以电互连位于晶圆20的相对两侧上的部件。
根据本发明的一些实施例，晶圆20包括在半导体衬底24的顶面上形成的集成电路器件26。根据本发明的一些实施例，集成电路器件26可以包括互补金属氧化物半导体(CMOS)晶体管、电阻器、电容器、二极管等。在此未示出集成电路器件26的细节。根据可选实施例，晶圆20用于形成中介层，并且衬底24可以是半导体衬底或介电衬底。
层间介电层(ILD)28形成在半导体衬底24上方并且填充集成电路器件26中的晶体管(未示出)的栅极堆叠件之间的间隔。根据一些实施例，ILD 28由磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、氟掺杂的硅酸盐玻璃(FSG)、正硅酸乙酯(TEOS)等形成。可以使用旋涂、可流动化学汽相沉积(FCVD)等形成ILD 28。根据本发明的一些实施例，使用诸如等离子体增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)等的沉积方法形成ILD 28。
接触插塞30形成在ILD 28中，并用于将集成电路器件26电连接至上面的金属线和通孔。根据本发明的一些实施例，接触插塞30由选自钨、铝、铜、钛、钽、氮化钛、氮化钽、它们的合金和/或它们的多层的导电材料形成。形成接触插塞30可包括在ILD 28中形成接触开口，将导电材料填充到接触开口中，以及执行平坦化(诸如化学机械抛光(CMP)工艺或机械研磨工艺)以使接触插塞30的顶面与ILD 28的顶面齐平。
在ILD和接触插塞30上方是互连结构32。互连结构32包括金属线34和通孔36，其形成在介电层38(也称为金属间介电层(IMD))中。下文中将位于同一层级(level)处的金属线共同地称为金属层。根据本发明的一些实施例，互连结构32包括多个金属层，该多个金属层包括通过通孔36互连的金属线34。金属线34和通孔36可以由铜或铜合金形成，并且它们也可以由其他金属形成。根据本发明的一些实施例，介电层38由低k介电材料形成。例如，低k介电材料的介电常数(k值)可以低于约3.0。介电层38可包括含碳低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等。根据本发明的一些实施例，介电层38的形成包括沉积含致孔剂的介电材料，然后执行固化工艺以驱除致孔剂，因此剩余的介电层38是多孔的。
金属线34和通孔36形成在介电层38中。形成工艺可包括单镶嵌和/或双镶嵌工艺。在单镶嵌工艺中，首先在介电层38之一中形成沟槽，然后用导电材料填充沟槽。然后执行诸如化学机械抛光(CMP)工艺的平坦化以去除高于IMD层的顶面的导电材料的多余部分，在沟槽中留下金属线。在双镶嵌工艺中，沟槽和通孔开口都形成在IMD层中，其中通孔开口位于沟槽下方并连接至沟槽。然后将导电材料填充到沟槽和通孔开口中以分别形成金属线和通孔。导电材料可以包括扩散阻挡层和在扩散阻挡层上方的含铜金属化材料。扩散阻挡层可以包括钛、氮化钛、钽、氮化钽等。
金属线34包括顶部导电(金属)部件，诸如金属线、金属焊盘或顶部介电层中的通孔(表示为34A)，顶部介电层为介电层38之一(标记为介电层38A)中。根据一些实施例，介电层38A由低k介电材料形成，类似于介电层38中下层介电层的材料。根据其他实施例，介电层38A由非低k介电材料形成，其可包括氮化硅、未掺杂的硅酸盐玻璃(USG)、氧化硅等。介电层38A也可以具有多层结构，包括例如两个USG层和其间的氮化硅层。顶部金属部件34A也可以由铜或铜合金形成，并且可以具有双镶嵌结构或单镶嵌结构。介电层38A有时被称为钝化层。
金属焊盘42形成在金属部件34A上方并与金属部件34A接触。相应的工艺被示为图24所示的工艺流程中的工艺202。图示的金属焊盘42表示处于相同层级的多个金属焊盘。根据一些实施例，金属焊盘42可以通过诸如金属线34和通孔36的导电部件电连接至集成电路器件26。金属焊盘42可以是铝焊盘或铝铜焊盘，并且可以使用其他金属材料。根据本发明的一些实施例，金属焊盘42具有的铝百分比大于约95％。
图案化的钝化层44形成在互连结构32上方。相应的工艺被示为图24所示的工艺流程中的工艺204。钝化层44的一些部分可以覆盖金属焊盘42的边缘部分，并且金属焊盘42的顶面的中心部分通过钝化层44中的开口46暴露。钝化层44可以是单层或复合层，并且可以由无孔材料形成。根据本发明的一些实施例，钝化层44是复合层，其包括氧化硅层和在氧化硅层上方的氮化硅层。
图2示出了介电层48的形成。根据本发明的一些实施例，介电层48由诸如聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)等的聚合物形成。根据本发明的一些实施例，介电层48由诸如氮化硅、氧化硅、氮氧化硅等的无机介电材料形成。在后续讨论中，介电层48被称为聚合物层48，虽然它可以由其他材料形成。相应的工艺被示为图24中所示的工艺流程中的工艺206。图案化聚合物层48，使得金属焊盘42的中心部分暴露。聚合物层48可以由光敏材料(诸如光刻胶)形成，其可以是负性光刻胶或正性光刻胶。聚合物层48的形成和图案化可包括旋涂聚合物层48，预烘烤聚合物层48，对聚合物层48执行曝光工艺和显影工艺，以及执行另一烘烤工艺以固化聚合物层48。根据聚合物层48由PBO形成的一些实施例，预烘烤可以在约100度至约180度之间的温度范围执行。预烘烤持续时间可以在约15分钟至约45分钟的范围内。使用具有透明图案和不透明图案的光刻掩模(未示出)执行曝光，不透明图案限定开口46的图案。在曝光之后，执行显影工艺以去除聚合物层48的一些部分，从而露出开口46以暴露下面的金属焊盘42。根据一些实施例，聚合物层48中的开口46小于钝化层44中的开口46(图1)。根据一些实施例，在显影之后，聚合物层48覆盖晶圆20的整个下面部分，除了下面金属焊盘(例如42)的将被露出的部分。
在显影之后，执行另一个烘烤工艺(其也是固化工艺)以固化聚合物层48。根据聚合物层48由PBO形成的一些实施例，烘烤工艺可以在约250度至约350度之间的温度范围执行。烘烤持续时间可以在约60分钟至约120分钟之间的范围内。通过曝光工艺和固化工艺，聚合物层48的剩余部分是交联的，并且不会通过后续曝光和显影工艺图案化和去除。
图3示出了导电迹线50的形成。根据一些实施例，导电迹线50也称为再分布线(RDL)。相应的工艺被示为图24所示的工艺流程中的工艺208。根据本发明的一些实施例，导电迹线50的形成包括沉积可以是铜层的毯式金属晶种层、在毯式金属晶种层上形成图案化的电镀掩模(未示出)、电镀导电迹线50、去除图案化的电镀掩模以及蚀刻之前由图案化的电镀掩模覆盖的毯式金属晶种层的部分。如图3所示，金属晶种层的剩余部分50'和电镀材料50”的组合形成导电迹线50，导电迹线50包括延伸至聚合物层48中的通孔部分和在聚合物层48上方的迹线部分。
图4A示出了顶部聚合物层52的形成。相应的工艺被示为图24所示的工艺流程中的工艺210。形成工艺可包括旋涂聚合物层52，然后执行预烘烤工艺。根据本发明的一些实施例，聚合物层52由诸如聚酰亚胺、PBO等的光敏聚合物形成。聚合物层52可以是负性光刻胶或正性光刻胶。此外，聚合物层48和52可以都是负性光刻胶、或者都是正性光刻胶、或者聚合物层48和52中的任一个是正性，而另一个是负性。聚合物层52可以由与聚合物层48相同类型的聚合物(例如PBO或聚酰亚胺)形成。或者，聚合物层52由与聚合物层48的聚合物不同类型的聚合物形成。根据聚合物层48由PBO形成的一些实施例，预烘烤可以在约100度至约180度之间的温度范围执行。预烘烤持续时间可以在约15分钟至约45分钟的范围内。
根据所示的一些实施例，图4B示出了如图4A所示的晶圆20一部分、RDL50的一些部分和聚合物层52的顶视图。由于聚合物层52完全覆盖RDL 50，因此使用虚线示出RDL 50。RDL 50可以包括(金属)焊盘部分50A和连接至焊盘部分50A的迹线部分50B。RDL 50的通孔部分(图4A)可以直接形成在焊盘部分50A或迹线部分50B下面。未示出通孔部分。
图5示出了根据一些实施例的图案化聚合物层52。相应的工艺被示为图24所示的工艺流程中的工艺212。图案化可包括对聚合物层52执行曝光工艺和显影工艺，以及执行另一烘烤工艺以固化聚合物层52。使用具有透明图案和不透明图案的光刻掩模(未示出)执行曝光，使得开口56和58的图案从光刻掩模转移到聚合物层52中。在曝光之后，执行显影工艺，使得开口56形成为与下面的RDL 50重叠，并且形成开口58以露出聚合物层48。在显影工艺中，暴露的聚合物层48将不会被去除(无论聚合物层48和52是否由相同类型的材料(如PBO)形成)，因为聚合物层48的所有剩余部分已经固化，并且通过前面的工艺已经交联。
在显影工艺之后，执行另一个烘烤工艺(其也是固化工艺)以固化聚合物层52。根据聚合物层52由PBO形成的一些实施例，烘烤工艺可以在约250度至约350度之间的温度范围执行。烘烤持续时间可以在约60分钟至约90分钟之间的范围内。由于聚合物层48和52以不同的工艺形成，无论聚合物层48和52是由不同材料还是相同材料形成，它们之间可以存在可区分的界面。例如，当使用二次电子显微镜(SEM)或透射电子显微镜(TEM)时，可以区分界面。
图6A示出了凸块下金属(UBM)60的形成。相应的工艺被示为图24所示的工艺流程中的工艺214。根据本发明的一些实施例，UBM 60的形成可以包括沉积金属晶种层，该金属晶种层可以包括钛层和在钛层上方的铜层，在毯式金属晶种层上形成图案化的电镀掩模(未示出)，将诸如铜的金属材料电镀到图案化的电镀掩模的开口中，去除图案化的电镀掩模，以及蚀刻先前被图案化的电镀掩模覆盖的金属晶种层的部分。
图6B示出了晶圆20的一部分的顶视图。根据本发明的一些实施例，聚合物层52的剩余部分(下文中称为聚合物岛52)形成为彼此分离的孤立岛。在岛之间，暴露聚合物层48。根据一些实施例，聚合物岛52的图案的设计包括确定晶圆20(和管芯22)上所有RDL 50的位置和尺寸，以确保聚合物岛52覆盖所有RDL 50。此外，如图6A和图6B所示，由于聚合物岛52具有缓冲由上面的UBM 60施加的应力的功能，因此聚合物岛52从RDL 50的边缘横向扩大，使得每个聚合物岛52具有超出下面的RDL 50的相应边缘的延伸部分。延伸部分以延伸距离E1添加在RDL 50的所有方向上(图6A)。延伸距离E1不能太大或太小。如果延伸距离E1太小，则聚合物岛52提供的缓冲功能受到折中。如果延伸距离E1太大，则聚合物岛52的区域太大，并且聚合物岛52本身可能向下面的钝化层44引入显著应力，导致钝化层44具有裂缝。根据一些实施例，延伸距离E1等于或大于聚合物层52的厚度T2(图6A)以提供足够缓冲，使得由UBM 60施加的应力被充分吸收。根据一些实施例，在相邻离散的聚合物岛52之间存在最小允许间距S1(图6B)。最小允许间距S1可以等于或大于约10nm。如图6C所示，如果发现相邻聚合物岛52之间的间距(例如图6C中的S2)将小于最小间距S1，则留下一部分聚合物层52以将相邻聚合物岛52连接成单个聚合物岛。因此，在晶圆20中，彼此离散的两个相邻聚合物岛52的间距不小于最小允许间距S1，并且间距小于最小允许间距S1的所有相邻聚合物岛52通过聚合物层52的连接部分互连。
图7示出了焊料区域62的形成。相应的工艺被示为图24所示的工艺流程中的工艺216。根据本发明的一些实施例，焊料区域62的形成包括将焊球放置在UBM 60上，以及回流焊球。根据替代实施例，焊料区域62的形成包括使用与电镀UBM 60相同的电镀掩模来电镀焊料区域，并且在去除电镀掩模并且蚀刻金属晶种层之后回流电镀焊料区域。
图7还示出了晶圆20的分割(管芯切割)，其沿划线64分割。相应的工艺被示为图24所示的工艺流程中的工艺218。因此，芯片22(被称为管芯22或封装组件22)彼此分离，并且所得的分离的芯片22也可称为管芯22。由于聚合物层52已经被图案化，因此划线64处没有聚合物层52。在分割工艺中，划线64穿过聚合物层48，并穿过聚合物岛52之间的间距。因此，在分割工艺中，分割中使用的刀片可能不会切穿聚合物层52的任何部分。而且，在所得到的管芯22中，聚合物岛52可以与所得到的管芯22的边缘横向间隔开。
接下来，将一个管芯22接合到封装组件66，封装组件66可以是中介板、封装衬底、封装件、器件管芯、印刷电路板等。相应的工艺被示为图24所示的工艺流程中的工艺220。底部填充物70可以设置在管芯22和封装组件66之间的间隙中。底部填充物70可以与聚合物层48的顶面接触。此外，底部填充物70可以环绕聚合物岛52并且接触聚合物岛52的侧壁，并且将聚合物岛52彼此分开。由此形成封*装件68。
图9示出了根据一些实施例的封装件68。这些实施例类似于图8中的实施例，除了开口72形成在聚合物层52中，开口72是通过连续聚合物层52彼此隔离的离散开口。底部填充物70延伸至开口72中，并且与聚合物层48接触。各个管芯22(和晶片20)的一些部分的顶视图在图10至图13中示出，图10至图13具有不同的开口72的图案。例如，图10示出了开口72是条形。图11示出了开口72是圆形。图12示出了开口72可以是多边形，例如正方形、矩形、六边形、八边形等。开口72也可具有混合图案。例如，图13示出了一些开口72具有多边形形状，其他开口72具有圆形形状、条形等。选择开口72的位置，使得没有RDL 50通过任一开口72暴露。
根据一些实施例，在开口72的形成中，从划线64(图7)去除聚合物层52，并且划线64中没有聚合物层52。在分割工艺中，切割刀片切穿聚合物层48，并穿过聚合物层52的剩余部分之间的间隔，而不切割聚合物层52。聚合物层52的剩余部分可以在每个管芯22中形成整体件(其中具有开口72)，划线不含聚合物层52。或者，在划线64中，留下聚合物层52的一些部分，并且离散的开口72也形成在划线64中。因此，在管芯分割工艺中，也切割聚合物层52。
在图6B，图6C和图11至图13所示的实施例中，管芯22中的RDL 50的总面积表示为A(μm2)。管芯22的总面积表示为B(μm2)。因此，RDL 50的密度C是B/A，表示为百分比。由于聚合物层52覆盖所有RDL 50和附加区域，因此聚合物层52的聚合物密度D(百分比)，即管芯22中聚合物层52的总面积除以管芯22的总面积，大于RDL密度C。根据本发明的一些实施例，聚合物密度D比RDL密度C大差值(D-C)，(D-C)大于约5％。差值(D-C)可以在约5％至约10％的范围内。如果E用于表示不含聚合物层52的面积密度，则E等于(100％-D)，可以在约(90％-C)至约(95％-C)之间的范围内。在下文中密度E称为聚合物开口比率E。聚合物开口比率E不能太大或太小。如果聚合物开口比率E太大，例如大于约70％，则聚合物层52的剩余部分可能太小，并且不能提供足够缓冲。如果聚合物开口比率E太小，例如小于约10％，则聚合物52产生的应力可能导致下面的钝化层44破裂。根据一些实施例，聚合物开口比率E在约10％至约70％的范围内。
图14示出了根据一些实施例的管芯22(晶圆20)的一部分，其中示出了一些部件的轮廓的一些细节。根据一些实施例，聚合物层48具有厚度T1，T1可以小于约12μm，并且可以在约5μm至约12μm之间的范围内。聚合物层52的厚度T2可以大于、等于或小于厚度T1。
本发明的实施例还适用于除晶圆和器件管芯之外的其他封装组件。例如，图15至图23示出了根据本发明的一些实施例的形成封装件的中间阶段的截面图，封装件包括密封在密封剂中的器件管芯。除非另有说明，否则这些实施例中的组件的材料和形成方法基本上与相同的部件相同，相同的部件在图1至图9所示的实施例中用相同的参考标号表示。因此，可以在对图1至图9中所示的实施例的讨论中找到关于图15至图23中所示的组件的形成工艺和材料的细节。
图15示出了形成包括载体120、离型膜122、介电层124、RDL 126、介电层128和金属柱132的初始结构。载体120可以是玻璃载体、陶瓷载体等。离型膜122可以由基于聚合物的材料(例如光热转换(LTHC)材料)形成。在离型膜122上形成介电层124。根据本发明的一些实施例，介电层124由聚合物形成，该聚合物也可以是诸如PBO、聚酰亚胺等的光敏材料。根据替代实施例，介电层124由诸如氮化硅的氮化物、诸如氧化硅的氧化物、PSG、BSG、BPSG等形成。在介电层124上方形成RDL 126。RDL 126的形成工艺和材料可以类似于RDL 50(图4A)的工艺和材料。
进一步参考图15，在RDL126上形成介电层128。介电层128的底面与RDL 126和介电层124的顶面接触。介电层128可以由选自用于形成介电层124的相同候选材料组的材料形成。然后图案化介电层128以在其中形成开口(由通孔130填充)以暴露RDL 126。
形成金属柱132和通孔130。在整个说明书中，金属柱132可选地称为通孔132，因为金属柱132穿透随后形成的密封剂。根据本发明的一些实施例，通孔132通过电镀形成。电镀通孔132可包括在介电层128上方形成毯式晶种层(未示出)并延伸至介电层128中的开口中，形成并图案化电镀掩模(未示出)，以及在晶种层的通过光刻胶中的开口暴露的部分上电镀通孔32。然后去除光刻胶和被光刻胶覆盖的晶种层的部分。通孔132和通孔130的材料可包括铜、铝、钛等，它们的多层。
图16示出了放置器件管芯136。器件管芯136通过可以是粘合膜的管芯附接膜(DAF)137粘合到介电层128。DAF 137可以与器件管芯136中的半导体衬底139的背面接触。器件管芯136可以是其中包括逻辑晶体管的逻辑器件管芯。根据一些实施例，金属柱138(诸如铜柱)预先形成为器件管芯136的最顶部，其中，金属柱138电连接至诸如器件管芯136中的晶体管的集成电路器件。根据本发明的一些实施例，聚合物填充相邻的金属柱138之间的间隙，以形成顶部介电层140。根据一些实施例，顶部介电层140(也称为聚合物层140)可以由PBO、聚酰亚胺等形成。
接下来，将密封剂144封装在器件管芯136上。密封剂144填充相邻通孔132之间的间隙以及通孔132和器件管芯136之间的间隙。密封剂144可包括模塑料、模制底部填充物、环氧树脂、树脂等。密封剂144的顶面高于金属柱138的顶端。
进一步参照图16，执行诸如CMP工艺或机械研磨工艺的平坦化工艺以薄化密封剂144，直到暴露出通孔132和金属柱138。由于研磨，通孔132的顶端与金属柱138的顶面基本齐平(共面)，并且基本上与密封剂144的顶面共面。
参照图17，形成介电层146。根据本发明的一些实施例，介电层146由聚合物形成，该聚合物也可以是根据本发明的一些实施例的光敏介电材料。例如，介电层146可以由PBO、聚酰亚胺等形成。根据替代实施例，介电层146由诸如氮化硅、氧化硅等的无机材料形成。在光刻工艺中图案化介电层146，从而形成开口(由RDL 148填充)。
接下来，形成RDL 148以连接至金属柱138和通孔132。RDL 148还可以互连金属柱138和通孔132。RDL 148包括在介电层146上方的金属迹线(金属线)以及延伸至介电层146中以电连接至通孔132和金属柱138的通孔。RDL 148的形成方法、材料和形成工艺可以与图3中的RDL 50的形成方法、材料和形成工艺基本相同，因此在此不再重复。
如图18至图22所示的后续工艺中，形成更多的介电层、RDL、上面的UBM和焊料区域。形成工艺类似于图3至图7中所示的工艺，因此在此不再详细讨论。通过参考图3至图7的讨论可以找到细节。图18示出了聚合物层48的形成。图19示出了RDL 50的形成，随后形成图20中的聚合物层52。图21示出了图案化聚合物层52以形成开口56和58，RDL 50和聚合物层48通过开口56和58暴露。图22示出了UBM 60和焊料区域62的形成。然后将所得到的重建晶圆63从载体120上卸下，并形成焊料区域74。然后沿着划线64切割重建晶圆63以形成单独的封装组件22。图23示出了接合封装组件22至封装组件66以形成封装件68，底部填充物70填充在封装组件22和66之间。
应当理解，图6B、图6C和图10至图14讨论的实施例也适用于图23所示的实施例。此外，聚合物层48和52、RDL 50和UBM 60的面积、比率、厚度等的讨论也适用于图23中的实施例。
在上面说明的实施例中，根据本发明的一些实施例讨论了一些工艺和部件。还可以包括其他部件和工艺。例如，可以包括测试结构以帮助3D封装或3DIC器件的验证测试。例如，测试结构可以包括在再分布层中或在允许测试3D封装或3DIC的衬底上形成的测试焊盘，使用探针和/或探针卡等。可以对中间结构以及最终结构执行验证测试。另外，本文所公开的结构和方法可以与测试方法结合使用，该测试方法包含中间验证已知良好的管芯以增加产量并降低成本。
本发明的实施例具有一些有利特征。通过图案化顶部聚合物层以形成聚合物岛或在顶部聚合物层中形成开口，顶部聚合物层施加至下面的介电层的应力减小，并且下面的介电层破裂的可能性降低了。
根据本发明的一些实施例，一种形成半导体器件的方法包括在晶圆的半导体衬底上方形成多个金属焊盘；形成覆盖多个金属焊盘的钝化层；图案化钝化层以露出多个金属焊盘；在钝化层上方形成第一聚合物层；形成多条再分布线，再分布线延伸至第一聚合物层和钝化层中以连接至多个金属焊盘；在第一聚合物层上方形成第二聚合物层；以及图案化第二聚合物层以露出多条再分布线，其中，第一聚合物层通过第二聚合物层的剩余部分中的开口进一步露出。在实施例中，图案化第二聚合物层成为彼此间隔开的多个离散岛，并且第一聚合物层通过多个离散岛之间的间隔露出。在实施例中，在图案化第二聚合物层时，在第二聚合物层中形成多个开口以露出第一聚合物层的下面部分，并且每个开口的边缘形成完整的环。在实施例中，第一聚合物层和第二聚合物层由相同的聚合物材料形成，并且在第一聚合物层上停止图案化第二聚合物层。在实施例中，第一聚合物层和第二聚合物层由不同的聚合物材料形成。在实施例中，方法还包括在图案化第一聚合物层之后并且在形成多条再分布线之前烘烤第一聚合物层。在实施例中，在图案化第二聚合物层之后，晶圆中和与多条再分布线相同层级的所有再分布线由第二聚合物层的剩余部分覆盖。在实施例中，第二聚合物层的剩余部分横向延伸超过相应的下面的多条再分布线中的一个的边缘。在实施例中，在图案化第二聚合物层之后，晶圆中和与多条再分布线相同层级的所有再分布线由第二聚合物层的剩余部分覆盖。在实施例中，多条再分布线包括：形成彼此相邻并具有第一间距的第一再分布线和第二再分布线，其中，第二聚合物层的第一剩余部分从第一再分布线延伸至第二再分布线，并且第一剩余部分覆盖第一再分布线和第二再分布线的部分。在实施例中，方法还包括形成彼此相邻并且具有第二间距的第三再分布线和第四再分布线，第二间距大于第一间距，其中，第二聚合物层的第二剩余部分和第三剩余部分分别覆盖第三再分布线和第四再分布线，其中，第二剩余部分和第三剩余部分是彼此分开的离散部分。在实施例中，方法还包括：形成延伸至第二聚合物层的剩余部分中的多个凸块下金属(UBM)；通过焊接区域接合封装组件以电连接至多个UBM；以及分配底部填充物以接触第二聚合物层的剩余部分的侧壁和第一聚合物层的顶面。
根据本发明的一些实施例，一种形成半导体器件的方法包括在无机钝化层上方形成第一聚合物层；形成多条再分布线，每个再分布线包括在第一聚合物层上方的第一部分和延伸至第一聚合物层中的第二部分，其中，多条再分布线物理上彼此分开；在多条再分布线上方涂覆第二聚合物层；将第二聚合物层图案化成彼此分开的多个离散部分，多个离散部分中的每一个覆盖多条再分布线中的一个；以及形成多个凸块下金属(UBM)，延伸至第二聚合物层的多个离散部分中以接触多条再分布线。在实施例中，方法还包括：切割第一聚合物层以形成离散管芯，其中，切割的划线穿过第二聚合物层的离散部分之间的间隔。在实施例中，第二聚合物层的离散部分覆盖与多条再分布线处于相同层级的所有再分布线。在实施例中，第二聚合物层的离散部分延伸超过相应的下面的多条再分布线中的一个的边缘的距离基本上等于或大于第二聚合物层的厚度。
根据本发明的一些实施例，一种半导体结构，包括：第一封装组件，包括：介电层；第一聚合物层，在介电层上方；多条再分布线，每个再分布线包括在第一聚合物层上方的第一部分和延伸至第一聚合物层中的第二部分，其中，多条再分布线物理上彼此分开；图案化的第二聚合物层，包括彼此分开的多个离散部分，多个离散部分中的每一个覆盖多条再分布线中的一个；以及多个凸块下金属(UBM)，延伸至图案化的第二聚合物层的多个离散部分中以接触多条再分布线。在实施例中，图案化的第二聚合物层的所有部分与第一封装组件的边缘间隔开。在实施例中，多条再分布线包括：彼此相邻并具有第一间距的第一再分布线和第二再分布线，其中，图案化的第二聚合物层的第一剩余部分从第一再分布线延伸至第二再分布线，并且第一剩余部分覆盖第一再分布线和第二个再分布线。在实施例中，结构还包括：彼此相邻并且具有第二间距的多条再分布线的第三再分布线和第四再分布线，第二间距大于第一间距，其中，图案化的第二聚合物层的第二剩余部分和第三剩余部分分别覆盖第三再分布线和第四再分布线，其中，第二剩余部分和第三剩余部分是彼此分开的离散部分。在实施例中，结构还包括：第二封装组件，接合到第一封装组件；以及底部填充物，环绕并接触图案化的第二聚合物层的多个离散部分的侧壁，其中，底部填充物还接触第一聚合物层的顶面。
根据本发明的一些实施例，提供了一种形成半导体器件的方法，所述方法包括：在晶圆的半导体衬底上方形成多个金属焊盘；形成覆盖所述多个金属焊盘的钝化层；图案化所述钝化层以露出所述多个金属焊盘；在所述钝化层上方形成第一聚合物层；形成延伸至所述第一聚合物层和所述钝化层中以连接至所述多个金属焊盘的多条再分布线；在所述第一聚合物层上方形成第二聚合物层；以及图案化所述第二聚合物层以露出所述多条再分布线，其中，所述第一聚合物层进一步通过所述第二聚合物层的剩余部分中的开口暴露。
在上述方法中，将所述第二聚合物层图案化为彼此间隔开的多个离散岛，并且所述第一聚合物层通过所述多个离散岛之间的间隔暴露。
在上述方法中，在图案化所述第二聚合物层中，在所述第二聚合物层中形成多个开口以露出下面的所述第一聚合物层的部分，并且每个所述开口的边缘形成完整的环。
在上述方法中，所述第一聚合物层和所述第二聚合物层由相同的聚合物材料形成，并且图案化所述第二聚合物层停止在所述第一聚合物层上。
在上述方法中，所述第一聚合物层和所述第二聚合物层由不同的聚合物材料形成。
在上述方法中，还包括在图案化所述第一聚合物层之后并且在形成所述多条再分布线之前，烘烤所述第一聚合物层。
在上述方法中，在图案化所述第二聚合物层之后，所述晶圆中和与所述多条再分布线处于相同层级的所有再分布线由所述第二聚合物层的剩余部分覆盖。
在上述方法中，所述第二聚合物层的剩余部分横向延伸超过相应的下面的所述多条再分布线中的一个的边缘。
在上述方法中，形成所述多条再分布线包括：形成彼此相邻并具有第一间距的第一再分布线和第二再分布线，其中，所述第二聚合物层的第一剩余部分从所述第一再分布线延伸至所述第二再分布线，并且所述第一剩余部分覆盖所述第一再分布线和所述第二再分布线的部分。
在上述方法中，形成所述多条再分布线还包括：形成彼此相邻并且具有第二间距的第三再分布线和第四再分布线，所述第二间距大于所述第一间距，其中，所述第二聚合物层的第二剩余部分和第三剩余部分分别覆盖所述第三再分布线和所述第四再分布线，其中，所述第二剩余部分和所述第三剩余部分是彼此分开的离散部分。
在上述方法中，还包括：形成延伸至所述第二聚合物层的剩余部分中的多个凸块下金属(UBM)；通过焊料区域接合封装组件以电连接至所述多个UBM；以及分配底部填充物以接触所述第二聚合物层的剩余部分的侧壁和所述第一聚合物层的顶面。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，所述方法包括：在无机钝化层上方形成第一聚合物层；形成多条再分布线，每条再分布线包括在所述第一聚合物层上方的第一部分和延伸至所述第一聚合物层中的第二部分，其中，所述多条再分布线物理上彼此分开；在所述多条再分布线上方涂布第二聚合物层；将所述第二聚合物层图案化成彼此分开的多个离散部分，多个所述离散部分中的每一个覆盖所述多条再分布线中的一个；以及形成延伸至所述第二聚合物层的多个所述离散部分中以接触所述多条再分布线的多个凸块下金属(UBM)。
在上述方法中，还包括：切割所述第一聚合物层以形成离散管芯，其中，切割的划线穿过所述第二聚合物层的所述离散部分之间的间隔。
在上述方法中，所述第二聚合物层的所述离散部分覆盖与所述多条再分布线处于相同层级的所有再分布线。
在上述方法中，所述第二聚合物层的所述离散部分延伸超过相应的下面的所述多条再分布线的边缘的距离等于或大于所述第二聚合物层的厚度。
根据本发明的另一些实施例，还提供了一种半导体结构，包括：第一封装组件，包括：介电层；第一聚合物层，在所述介电层上方；多条再分布线，每条再分布线包括在所述第一聚合物层上方的第一部分和延伸至所述第一聚合物层中的第二部分，其中，所述多条再分布线物理上彼此分开；图案化的第二聚合物层，包括彼此分开的多个离散部分，多个所述离散部分中的每一个覆盖所述多条再分布线中的一个；以及多个凸块下金属(UBM)，延伸至所述图案化的第二聚合物层的多个所述离散部分中以接触所述多条再分布线。
在上述半导体结构中，所述图案化的第二聚合物层的所有部分与所述第一封装组件的边缘间隔开。
在上述半导体结构中，所述多条再分布线包括：彼此相邻并具有第一间距的第一再分布线和第二再分布线，其中，所述图案化的第二聚合物层的第一剩余部分从所述第一再分布线延伸至所述第二再分布线，并且所述第一剩余部分覆盖所述第一再分布线和所述第二个再分布线。
在上述半导体结构中，还包括：彼此相邻并且具有第二间距的所述多条再分布线的第三再分布线和第四再分布线，所述第二间距大于所述第一间距，其中，所述图案化的第二聚合物层的第二剩余部分和第三剩余部分分别覆盖所述第三再分布线和所述第四再分布线，其中，所述第二剩余部分和所述第三剩余部分是彼此分开的离散部分。
在上述半导体结构中，还包括：第二封装组件，接合到所述第一封装组件；以及底部填充物，环绕并接触所述图案化的第二聚合物层的多个所述离散部分的侧壁，其中，所述底部填充物还接触所述第一聚合物层的顶面。
以上论述了若干实施例的部件，使得本领域的技术人员可以更好地理解本发明的各个实施例。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍的实施例相同的目的和/或实现相同优点的其它工艺和结构。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (20)

1.一种形成半导体器件的方法，所述方法包括：
在晶圆的半导体衬底上方形成多个金属焊盘；
形成覆盖所述多个金属焊盘的钝化层；
图案化所述钝化层以露出所述多个金属焊盘；
在所述钝化层上方形成第一聚合物层；
形成延伸至所述第一聚合物层和所述钝化层中以连接至所述多个金属焊盘的多条再分布线；
在所述第一聚合物层上方形成第二聚合物层；以及
图案化所述第二聚合物层以露出所述多条再分布线，其中，所述第一聚合物层进一步通过所述第二聚合物层的剩余部分中的开口暴露，
其中，将所述第二聚合物层图案化为彼此间隔开的多个离散岛，并且所述第一聚合物层通过所述多个离散岛之间的间隔暴露，
如果在相邻离散的所述离散岛之间的间距小于预定间距，则留下一部分所述第二聚合物层以将小于该预定间距的相邻离散岛连接成单个聚合物岛。
2.根据权利要求1所述的方法，每个所述离散岛具有超出下面的再分布线的相应边缘的延伸部分，所述延伸部分的延伸距离等于或大于所述第二聚合物层的厚度。
3.根据权利要求1所述的方法，其中，在图案化所述第二聚合物层中，在所述第二聚合物层中形成多个开口以露出下面的所述第一聚合物层的部分，并且每个所述开口的边缘形成完整的环。
4.根据权利要求1所述的方法，其中，所述第一聚合物层和所述第二聚合物层由相同的聚合物材料形成，并且图案化所述第二聚合物层停止在所述第一聚合物层上。
5.根据权利要求1所述的方法，其中，所述第一聚合物层和所述第二聚合物层由不同的聚合物材料形成。
6.根据权利要求1所述的方法，还包括在图案化所述第一聚合物层之后并且在形成所述多条再分布线之前，烘烤所述第一聚合物层。
7.根据权利要求1所述的方法，其中，在图案化所述第二聚合物层之后，所述晶圆中和与所述多条再分布线处于相同层级的所有再分布线由所述第二聚合物层的剩余部分覆盖。
8.根据权利要求7所述的方法，其中，所述第二聚合物层的剩余部分横向延伸超过相应的下面的所述多条再分布线中的一个的边缘。
9.根据权利要求1所述的方法，其中，形成所述多条再分布线包括：
形成彼此相邻并具有第一间距的第一再分布线和第二再分布线，其中，所述第二聚合物层的第一剩余部分从所述第一再分布线延伸至所述第二再分布线，并且所述第一剩余部分覆盖所述第一再分布线和所述第二再分布线的部分。
10.根据权利要求9所述的方法，其中，形成所述多条再分布线还包括：
形成彼此相邻并且具有第二间距的第三再分布线和第四再分布线，所述第二间距大于所述第一间距，其中，所述第二聚合物层的第二剩余部分和第三剩余部分分别覆盖所述第三再分布线和所述第四再分布线，其中，所述第二剩余部分和所述第三剩余部分是彼此分开的离散部分。
11.根据权利要求1所述的方法，还包括：
形成延伸至所述第二聚合物层的剩余部分中的多个凸块下金属(UBM)；
通过焊料区域接合封装组件以电连接至所述多个凸块下金属；以及
分配底部填充物以接触所述第二聚合物层的剩余部分的侧壁和所述第一聚合物层的顶面。
12.一种形成半导体器件的方法，所述方法包括：
在无机钝化层上方形成第一聚合物层；
形成多条再分布线，每条再分布线包括在所述第一聚合物层上方的第一部分和延伸至所述第一聚合物层中的第二部分，其中，所述多条再分布线物理上彼此分开；
在所述多条再分布线上方涂布第二聚合物层；
将所述第二聚合物层图案化成彼此分开的多个离散部分，多个所述离散部分中的每一个覆盖所述多条再分布线中的一个；以及
形成延伸至所述第二聚合物层的多个所述离散部分中以接触所述多条再分布线的多个凸块下金属(UBM)，
如果在相邻离散的所述离散部分之间的间距小于预定间距，则留下一部分所述第二聚合物层以将小于该预定间距的相邻离散部分连接成单个聚合物岛。
13.根据权利要求12所述的方法，还包括：
切割所述第一聚合物层以形成离散管芯，其中，切割的划线穿过所述第二聚合物层的所述离散部分之间的间隔。
14.根据权利要求12所述的方法，其中，所述第二聚合物层的所述离散部分覆盖与所述多条再分布线处于相同层级的所有再分布线。
15.根据权利要求14所述的方法，其中，所述第二聚合物层的所述离散部分延伸超过相应的下面的所述多条再分布线的边缘的距离等于或大于所述第二聚合物层的厚度。
16.一种半导体结构，包括：
第一封装组件，包括：
介电层；
第一聚合物层，在所述介电层上方；
多条再分布线，每条再分布线包括在所述第一聚合物层上方的第一部分和延伸至所述第一聚合物层中的第二部分，其中，所述多条再分布线物理上彼此分开；
图案化的第二聚合物层，包括彼此分开的多个离散部分，多个所述离散部分中的每一个覆盖所述多条再分布线中的一个；以及
多个凸块下金属(UBM)，延伸至所述图案化的第二聚合物层的多个所述离散部分中以接触所述多条再分布线，以及
至少一对相邻的所述离散部分连接成的单个聚合物岛。
17.根据权利要求16所述的半导体结构，其中，所述图案化的第二聚合物层的所有部分与所述第一封装组件的边缘间隔开。
18.根据权利要求16所述的半导体结构，其中，所述多条再分布线包括：
彼此相邻并具有第一间距的第一再分布线和第二再分布线，其中，所述图案化的第二聚合物层的第一剩余部分从所述第一再分布线延伸至所述第二再分布线，并且所述第一剩余部分覆盖所述第一再分布线和所述第二再分布线。
19.根据权利要求18所述的半导体结构，还包括：
彼此相邻并且具有第二间距的所述多条再分布线的第三再分布线和第四再分布线，所述第二间距大于所述第一间距，其中，所述图案化的第二聚合物层的第二剩余部分和第三剩余部分分别覆盖所述第三再分布线和所述第四再分布线，其中，所述第二剩余部分和所述第三剩余部分是彼此分开的离散部分。
20.根据权利要求16所述的半导体结构，还包括：
第二封装组件，接合到所述第一封装组件；以及
底部填充物，环绕并接触所述图案化的第二聚合物层的多个所述离散部分的侧壁，其中，所述底部填充物还接触所述第一聚合物层的顶面。
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