TWI817728B - 內埋元件之封裝結構 - Google Patents

內埋元件之封裝結構 Download PDF

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TWI817728B
TWI817728B TW111135594A TW111135594A TWI817728B TW I817728 B TWI817728 B TW I817728B TW 111135594 A TW111135594 A TW 111135594A TW 111135594 A TW111135594 A TW 111135594A TW I817728 B TWI817728 B TW I817728B
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Taiwan
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layer
semiconductor chip
embedded
conductive
circuit
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TW111135594A
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TW202414703A (zh
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胡竹青
許詩濱
楊智貴
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恆勁科技股份有限公司
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Priority to TW111135594A priority Critical patent/TWI817728B/zh
Priority to CN202311032626.6A priority patent/CN117747553A/zh
Priority to US18/469,450 priority patent/US20240096838A1/en
Application granted granted Critical
Publication of TWI817728B publication Critical patent/TWI817728B/zh
Publication of TW202414703A publication Critical patent/TW202414703A/zh

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Abstract

一種內埋元件之封裝結構，係於半導體晶片之晶背形成多層金屬層以作為緩衝部，再將該半導體晶片以該緩衝部藉由膠材接置於該承載部上，之後以絕緣層包覆該半導體晶片，且於該絕緣層上形成一電性連接該半導體晶片之增層線路結構，故在該半導體晶片之熱膨脹係數小於膠材之熱膨脹係數的情況下，該緩衝部能防止該半導體晶片與該承載部上之膠材分離。

Description

內埋元件之封裝結構
本發明係有關一種半導體封裝製程，尤指一種可提升可靠度之內埋元件之式封裝結構。
隨著電子產品之功能不斷提升，且於節能及效率提升之需求下，半導體功率晶片、電源管理晶片逐步朝向模組化推展以提升效能，故而此類元件之封裝由習知打線(wire-bonding，如金線、銅線)或焊錫覆晶封裝方式已逐步進展到晶片內埋封裝，以提升電性效能。
習知內埋式封裝結構1，如圖1所示，其將半導體晶片10藉由膠材91設於承載板90上，且以絕緣層12包覆該半導體晶片10，並於該絕緣層12上形成電性連接該半導體晶片10之增層線路結構13。
惟，該半導體晶片10嵌埋於該絕緣層12中，尤其是大功率晶片，往往因為該半導體晶片10的熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)與該膠材91的CTE的差異過大，在熱應力效應下，致使兩者之接合力不佳，而容易造成該半導體晶片10與該膠材91之間發生分層(de-lamination)。
再者，習知技術亦有將晶片之晶背形成金屬化薄膜，以克服上述習知問題，而常用之金屬化薄膜之組成材料為兩層金屬層(如Ti/Ag)或三層金屬層(如Ti/Ni/Ag)，如此雖可改善結合力及增強導熱與散熱，但對於大功率且有高散熱需求之晶片進行封裝時，仍面臨有分層之可靠度風險。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之課題。
有鑑於習知技術之問題，本發明提供一種內埋元件之封裝結構，係包括：一載板結構，係包含一承載部、一設於該承載部上之絕緣層、複數嵌埋於該絕緣層內之導通結構、及一設於該絕緣層上之增層線路結構，其中，該承載部係包括至少一圖案化線路層以及與其相結合之絕緣材，且該線路層藉由該導通結構與該增層線路結構電性連接；以及至少一半導體晶片，係內埋於該絕緣層內並電性連接該於該增層線路結構，且該半導體晶片之晶背係金屬化為複數金屬層，以令該半導體晶片以該複數金屬層之側藉由一膠材黏設於該承載部上，其中，該複數金屬層之組成係包括由內而外依序堆疊結合之一第一鈦層、一鎳層、一第二鈦層及一銀層。
前述之內埋元件之封裝結構中，該半導體晶片係藉由銅導體電性連接該增層線路結構。
前述之內埋元件之封裝結構中，該導通結構係為導電柱及/或導電通孔。
前述之內埋元件之封裝結構中，該半導體晶片係結合於該承載部之金屬部位或絕緣部位。
前述之內埋元件之封裝結構中，該承載部係具有呈堆疊且電性相連接之複數圖案化線路層。
前述之內埋元件之封裝結構中，該承載部及/或該增層線路結構係設有外露之複數電極墊，以供結合外部元件。例如，該承載部於外露之該電極墊之側邊係形成有一弧形凹口。或者，該外部元件包括主動元件、被動元件、導電凸塊、焊錫球之其中之一者或其組合。
由上可知，本發明之內埋元件之封裝結構，主要藉由多層金屬層作為緩衝部，用於該半導體晶片與該膠材之間的緩衝，以防止環境衝擊之分離，故相較於習知技術，本發明之內埋元件之封裝結構能有效分散熱應力，而提高該半導體晶片與該膠材之間的接合力，以避免因該半導體晶片與該膠材之間的接合力不佳而發生脫層之問題，進而提升該內埋式封裝結構之可靠度。
1,2:封裝結構
10,20:半導體晶片
20b:晶背
12,22:絕緣層
13,23,43:增層線路結構
2a,3a,3b,3c,4a,4b:載板結構
20a:作用面
200:接點
21:緩衝部
211:第一鈦層
212:鎳層
213:第二鈦層
214:銀層
230:介電層
231:線路重佈層
232:銅導體
233,262,362,364:電極墊
24,34,44:導通結構
26,36,36a,46:承載部
26a:絕緣部位
26b,360:金屬部位
260:絕緣材
261,361:線路層
27,91:膠材
363:導電柱
42:絕緣保護層
432,463:導電柱體
440:凹口
51:主動元件
52:被動元件
53:導電凸塊
54:焊錫球
90:承載板
t1,t2,t3,t4:厚度
圖1係為習知內埋式封裝結構之剖面示意圖。
圖2A至圖2C係為本發明之內埋元件之封裝結構之製法之剖面示意圖。
圖2D係為圖2C之緩衝部之局部放大剖面圖。
圖3A、圖3B及圖3C係為圖2C之其它不同實施例之剖面示意圖。
圖4A及圖4B係為圖2C之其它不同實施例之剖面示意圖。
圖5係為圖2C之應用之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2C係為本發明之內埋元件之封裝結構2之製法之剖面示意圖。於本實施例中，係採用大版面規格封裝(Panel Level Packaging，簡稱PLP)技術製作該封裝結構2。
如圖2A所示，提供於一承載部26及一半導體晶片20，該半導體晶片20係具有相對之作用面20a與晶背20b，且該作用面20a上形成有複數接點200。其中，係先以沉積、濺鍍、化學氣相沉積(chemical vapor deposition，簡稱CVD)或電鍍的方式於該半導體晶片20之晶背20b上進行金屬化，以形成為複數金屬層，供作為緩衝部21。
於本實施例中，該承載部26係包括至少一圖案化線路層261及與其相結合之絕緣材260，且該承載部26之線路層261設有外露之複數電極墊262，以供結合外部元件(如圖5所示之主動元件51、被動元件52、導電凸塊53、焊錫球54之其中之一者或其組合)。例如，該承載部26為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路結構，其係於介電材上形成線路層261，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)。應可理解地，該承載部26亦可為其它可供承載如晶片等電子元件之基材，例如金屬(如Cu,Al,Ni,SUS)圖案化結構陶瓷、或多層佈線結構，並無特別限制。
再者，該半導體晶片20係結合於該承載部26之絕緣材260所形成之絕緣部位26a，且該膠材27係以大致均勻的厚度佈設於該承載部26對應置放該半導體晶片20之區域，故該膠材27之佈設面積略相當於該緩衝部21的佈設面積(或該半導體晶片20之晶背20b的面積)。或者，該半導體晶片20亦可結合於該承載部26之線路層261所形成之金屬部位26b，如圖3A所示。
又，該緩衝部21係形成於該半導體晶片20之晶背20b，供作為金屬緩衝及黏著介面，其為複合式金屬組合，如圖2D所示之包含多層相堆疊之金屬層。例如，該緩衝部21之組成係包括從該半導體晶片20之晶背20b朝外依序堆疊結合之一第一鈦層(Ti)211、鎳層(Ni)212、第二鈦層(Ti)213及銀層(Ag)214等四層金屬層。
進一步，該第一鈦層211的厚度t1係為0.01至2微米、該鎳層212的厚度t2係為0.01至2微米、該第二鈦層213的厚度t3係為 0.0001至2微米、及該銀層214的厚度t4係為0.01至10微米。該緩衝部21之各金屬層的厚度係可依需求設計，並無特別限制。因此，有關該第一鈦層211、鎳層212、第二鈦層213及銀層214等各層的厚度t1~t4可依封裝形式之需求進行調整，並不限於上述
應可理解地，有關該緩衝部21之金屬組合種類繁多，如Ti/Ni/Ti/Ag，Ti/Ni/Ag/Ni，Ti/Ni/Ti/Au，Ti/Au/Ti/Ni/V/Au等，但不限於上述。較佳為Ti/Ni/Ti/Ag。
如圖2B所示，將該半導體晶片20以其上之緩衝部21之側結合至該承載部26上之膠材27上。
於本實施例中，該膠材27係為一種導熱銀膠，其作為半導體晶片20與承載部26之連接，且常需180℃至270℃之烘烤。
如圖2C所示，形成一絕緣層22於該承載部26上，以令該絕緣層22包覆該半導體晶片20。接著，形成一增層線路結構23於該絕緣層22上，且令該增層線路結構23電性連接該些接點200，並於該絕緣層22內嵌埋有複數導通結構24，以電性連接該承載部26及該增層線路結構23，並且據以形成一載板結構2a，其包括一設於該承載部26上之絕緣層22、複數嵌埋於該絕緣層22內之導通結構24及一設於該絕緣層22上之增層線路結構23。
於本實施例中，形成該絕緣層22之材質係為聚醯亞胺(polyimide，簡稱PI)、ABF(Ajinomoto Build-up Film)、感光型有機材料、環氧膜壓樹脂(epoxy molding compound，簡稱EMC)等封裝材， 但並不限於上述。例如，可用壓合(lamination)或模壓(molding)之方式將該絕緣層22形成於該承載部26上。
再者，可於該絕緣層22上形成複數外露該些接點200之開孔，以利於該增層線路結構23連接該接點200。例如，該半導體晶片20係藉由銅導體232電性連接該增層線路結構23為最佳。
又，該增層線路結構23係具有至少一介電層230及至少一結合該介電層230之線路重佈層(Redistribution layer，簡稱RDL)231，且該線路重佈層231可藉由導電盲孔或導電柱(如銅導體232)電性連接該接點200，並於該增層線路結構23之最外側之線路重佈層231上設有外露之複數電極墊233，以供結合外部元件(如圖5所示之主動元件51、被動元件52、導電凸塊53、焊錫球54之其中之一者或其組合)。例如，形成該線路重佈層231之材質係為銅，且形成該介電層230之材質係為如ABF、感光型有機材料、EMC、聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材。
另外，該導通結構24係為導電柱(如圖2C所示)及/或導電通孔(如圖3A所示之載板結構3a，其導通結構34與該線路重佈層231係一體成形)，且該承載部26之線路層261藉由該導通結構24與該增層線路結構23電性連接。於另一實施例中，該承載部36亦可埋設於該絕緣層22中，如圖3B所示之載板結構3b，其包含一用以承載該半導體晶片20之金屬部位360(作為置晶墊)及用以設置及電性連接該導通結構24之線 路層361(其具有複數電極墊362)，且該絕緣材260係為該絕緣層22之其中一部分。
應可理解地，該承載部36a亦可具有呈堆疊且電性相連接之複數圖案化線路層261，如圖3C所示之載板結構3c，其包含複數電性連接各層間線路層261之導電盲孔或導電柱363，並於最外側之線路層261上設有外露之複數電極墊364，以供結合外部元件。
因此，本發明之結構特徵主要藉由多層金屬層作為緩衝部21，用於該半導體晶片20與該膠材27之間的緩衝，以防止環境衝擊之分離，故相較於習知技術，本發明之內埋元件之封裝結構2能提高該半導體晶片20與該承載部26,36,36a之間的接合力，且能提升該封裝結構2之可靠度。
再者，若以第一鈦層(Ti)211、鎳層(Ni)212、第二鈦層(Ti)213及銀層(Ag)214等四層金屬層作為該緩衝部21，其亦可作為黏著導電介面，並可提高接合力，以提升可靠度能力。
另外，本發明揭露之封裝結構2，其關於該承載部26、導通結構24及增層線路結構23之製程種類繁多，可依需求選用。例如，以導電柱體製程取代導電盲孔製程，如圖4A所示之載板結構4a，其承載部46(或增層線路結構43)係以導電柱體463(或導電柱體432)電性導通上下層之線路層261(或線路重佈層231)；或者，例如，該導通結構44亦可連結於該承載部36且外露於該絕緣層22之側面，如圖4B所示之載板結構4b，其於外露之該電極墊362之側邊形成一弧形凹口440，並以絕緣保護層42覆蓋該線路重佈層231，此時，該承載部36之功用則為電性連接 墊層，如平面網格陣列封裝(Land grid array，簡稱LGA)型焊墊，以當該封裝結構2之電極墊362藉由焊料組裝至一電路板(圖略)上時，可由該凹口440處利用光學檢查觀看該焊錫材料之結合情況，故此方法可避免安裝一應用該封裝結構2之車載電子部件(圖略)時品質不良之問題。
本發明提供一種內埋元件之封裝結構2，係包括：一載板結構2a,3a,3b,3c,4a,4b以及至少一內埋於該載板結構2a,3a,3b,3c,4a,4b內之半導體晶片20。
所述之載板結構2a,3a,3b,3c,4a,4b係包含一承載部26,36,36a,46、一設於該承載部26,36,36a,46上之絕緣層22、複數嵌埋於該絕緣層22內之導通結構24,34,44、及一設於該絕緣層22上之增層線路結構23,43，其中，該承載部26,36,36a,46係包括至少一圖案化線路層261,361以及與其相結合之絕緣材260，且該線路層261,361藉由該導通結構24,34,44與該增層線路結構23,43電性連接。
所述之半導體晶片20係內埋於該絕緣層22內並電性連接於該增層線路結構23,43，且該半導體晶片20之晶背20b係金屬化為複數金屬層，供作為緩衝部21，以令該半導體晶片20以該複數金屬層之側藉由一膠材27黏設於該承載部26,36,36a,46上，其中，該複數金屬層之組成係包括由內而外依序堆疊結合之一第一鈦層211、一鎳層212、一第二鈦層213及一銀層214。
於一實施例中，該半導體晶片20係藉由銅導體232電性連接該增層線路結構23。
於一實施例中，該導通結構24,34係為導電柱及/或導電通孔。
於一實施例中，該半導體晶片20係結合於該承載部26,36,36a,46之金屬部位26b,360或絕緣部位26a。
於一實施例中，該承載部46係具有呈堆疊且電性相連接之複數圖案化線路層261。
於一實施例中，該承載部26,36,36a,46及/或該增層線路結構23,43係設有外露之複數電極墊262,362,364,233，以供結合外部元件。例如，該承載部36於外露之該電極墊362之側邊係形成有一弧形凹口440。或者，該外部元件包括主動元件51、被動元件52、導電凸塊53、焊錫球54之其中之一者或其組合。
綜上所述，本發明之內埋元件之封裝結構係藉由將該半導體晶片之晶背金屬化為複數金屬層，供作為緩衝部，以解決半導體晶片與膠材之間因CTE差異大而產生接合力不佳的問題，故本發明之內埋元件之封裝結構將更有利於應用在高功率電源管理PMIC、高散熱等需求之相關產品，甚至於高信賴性要求之產品。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:封裝結構
2a:載板結構
20:半導體晶片
200:接點
21:緩衝部
22:絕緣層
23:增層線路結構
230:介電層
231:線路重佈層
232:銅導體
233,262:電極墊
24:導通結構
26:承載部
26a:絕緣部位
260:絕緣材
261:線路層
27:膠材

Claims (8)

  1. 一種內埋元件之封裝結構，係包括：
    一載板結構，係包含一承載部、一設於該承載部上之絕緣層、複數嵌埋於該絕緣層內之導通結構、及一設於該絕緣層上之增層線路結構，其中，該承載部係包括至少一圖案化線路層以及與其相結合之絕緣材，且該圖案化線路層藉由該導通結構與該增層線路結構電性連接；以及
    至少一半導體晶片，係內埋於該絕緣層內並電性連接於該增層線路結構，且該半導體晶片之晶背係金屬化為複數金屬層，以令該半導體晶片以該複數金屬層之側藉由一膠材黏設於該承載部上，其中，該複數金屬層之組成係包括由內而外依序堆疊結合之一第一鈦層、一鎳層、一第二鈦層及一銀層。
  2. 如請求項1所述之內埋元件之封裝結構，其中，該半導體晶片係藉由銅導體電性連接該增層線路結構。
  3. 如請求項1所述之內埋元件之封裝結構，其中，該導通結構係為導電柱及/或導電通孔。
  4. 如請求項1所述之內埋元件之封裝結構，其中，該半導體晶片係結合於該承載部之金屬部位或絕緣部位。
  5. 如請求項1所述之內埋元件之封裝結構，其中，該承載部係具有呈堆疊且電性相連接之複數圖案化線路層。
  6. 如請求項1所述之內埋元件之封裝結構，其中，該承載部及/或該增層線路結構係設有外露之複數電極墊，以供結合外部元件。
  7. 如請求項6所述之內埋元件之封裝結構，其中，該承載部於外露之該電極墊之側邊係形成有一弧形凹口。
  8. 如請求項6所述之內埋元件之封裝結構，其中，該外部元件包括主動元件、被動元件、導電凸塊、焊錫球之其中之一者或其組合。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200627607A (en) * 2005-01-25 2006-08-01 Advanced Semiconductor Eng Grain-embedded die structure and method for manufacturing the same
US20190326255A1 (en) * 2018-04-23 2019-10-24 Deca Technologies Inc. Fully molded semiconductor package for power devices and method of making the same
TW202034414A (zh) * 2018-10-31 2020-09-16 台灣積體電路製造股份有限公司 半導體裝置的形成方法及半導體結構

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200627607A (en) * 2005-01-25 2006-08-01 Advanced Semiconductor Eng Grain-embedded die structure and method for manufacturing the same
US20190326255A1 (en) * 2018-04-23 2019-10-24 Deca Technologies Inc. Fully molded semiconductor package for power devices and method of making the same
TW202034414A (zh) * 2018-10-31 2020-09-16 台灣積體電路製造股份有限公司 半導體裝置的形成方法及半導體結構

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