CN117747553A - 内埋元件的封装结构 - Google Patents

内埋元件的封装结构 Download PDF

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Publication number
CN117747553A
CN117747553A CN202311032626.6A CN202311032626A CN117747553A CN 117747553 A CN117747553 A CN 117747553A CN 202311032626 A CN202311032626 A CN 202311032626A CN 117747553 A CN117747553 A CN 117747553A
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China
Prior art keywords
layer
semiconductor chip
carrier
build
package structure
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CN202311032626.6A
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English (en)
Inventor
胡竹青
许诗滨
杨智贵
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Phoenix Pioneer Technology Co Ltd
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Phoenix Pioneer Technology Co Ltd
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Publication of CN117747553A publication Critical patent/CN117747553A/zh
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    • H01—ELECTRIC ELEMENTS
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Abstract

一种内埋元件的封装结构，包括于半导体芯片的晶背形成多层金属层以作为缓冲部，再将该半导体芯片以该缓冲部通过胶材接置于该承载部上，之后以绝缘层包覆该半导体芯片，且于该绝缘层上形成一电性连接该半导体芯片的增层线路结构，故在该半导体芯片的热膨胀系数小于胶材的热膨胀系数的情况下，该缓冲部能防止该半导体芯片与该承载部上的胶材分离。

Description

内埋元件的封装结构
技术领域
本发明涉及一种半导体封装工艺，尤其涉及一种可提升可靠度的内埋元件的式封装结构。
背景技术
随着电子产品的功能不断提升，且于节能及效率提升的需求下，半导体功率芯片、电源管理芯片逐步朝向模块化推展以提升效能，故而此类元件的封装由现有打线(wire-bonding，如金线、铜线)或焊锡倒装芯片封装方式已逐步进展到芯片内埋封装，以提升电性效能。
现有内埋式封装结构1，如图1所示，其将半导体芯片10通过胶材91设于承载板90上，且以绝缘层12包覆该半导体芯片10，并于该绝缘层12上形成电性连接该半导体芯片10的增层线路结构13。
但是，该半导体芯片10嵌埋于该绝缘层12中，尤其是大功率芯片，往往因为该半导体芯片10的热膨胀系数(Coefficient of thermal expansion，简称CTE)与该胶材91的CTE的差异过大，在热应力效应下，致使两者的接合力不佳，而容易造成该半导体芯片10与该胶材91之间发生分层(de-lamination)。
再者，现有技术亦有将芯片的晶背形成金属化薄膜，以克服上述现有问题，而常用的金属化薄膜的组成材料为两层金属层(如Ti/Ag)或三层金属层(如Ti/Ni/Ag)，如此虽可改善结合力及增强导热与散热，但对于大功率且有高散热需求的芯片进行封装时，仍面临有分层的可靠度风险。
因此，如何克服上述现有技术的种种问题，实已成为目前业界亟待克服的课题。
发明内容
本发明的目的在于提出一种内埋元件的封装结构，以解决上述至少一个问题。
有鉴于现有技术的问题，本发明提供一种内埋元件的封装结构，包括：一载板结构，其包含一承载部、一设于该承载部上的绝缘层、多个嵌埋于该绝缘层内的导通结构及一设于该绝缘层上的增层线路结构，其中，该承载部包括至少一图案化线路层以及与其相结合的绝缘材，且该线路层通过该导通结构与该增层线路结构电性连接；以及至少一半导体芯片，其内埋于该绝缘层内并电性连接该于该增层线路结构，且该半导体芯片的晶背金属化为多个金属层，以令该半导体芯片以该多个金属层的侧通过一胶材粘设于该承载部上，其中，该多个金属层的组成包括由内而外依序堆叠结合的一第一钛层、一镍层、一第二钛层及一银层。
前述的内埋元件的封装结构中，该半导体芯片通过铜导体电性连接该增层线路结构。
前述的内埋元件的封装结构中，该导通结构为导电柱及/或导电通孔。
前述的内埋元件的封装结构中，该半导体芯片结合于该承载部的金属部位或绝缘部位。
前述的内埋元件的封装结构中，该承载部具有呈堆叠且电性相连接的多个图案化线路层。
前述的内埋元件的封装结构中，该承载部及/或该增层线路结构设有外露的多个电极垫，以供结合外部元件。例如，该承载部于外露的该电极垫的侧边形成有一弧形凹口。或者，该外部元件包括有源元件、无源元件、导电凸块、焊锡球中的至少一个。
由上可知，本发明的内埋元件的封装结构，主要通过多层金属层作为缓冲部，用于该半导体芯片与该胶材之间的缓冲，以防止环境冲击的分离，故相较于现有技术，本发明的内埋元件的封装结构能有效分散热应力，而提高该半导体芯片与该胶材之间的接合力，以避免因该半导体芯片与该胶材之间的接合力不佳而发生脱层的问题，进而提升该内埋式封装结构的可靠度。
附图说明
图1为现有内埋式封装结构的剖面示意图。
图2A至图2C为本发明的内埋元件的封装结构的制法的剖面示意图。
图2D为图2C的缓冲部的局部放大剖面图。
图3A、图3B及图3C为图2C的其它不同实施例的剖面示意图。
图4A及图4B为图2C的其它不同实施例的剖面示意图。
图5为图2C的应用的剖面示意图。
附图标记如下：
1,2封装结构
10,20半导体芯片
20b晶背
12,22绝缘层
13,23,43增层线路结构
2a,3a,3b,3c,4a,4b载板结构
20a 作用面
200 接点
21 缓冲部
211 第一钛层
212 镍层
213 第二钛层
214 银层
230 介电层
231 线路重布层
232 铜导体
233,262,362,364电极垫
24,34,44导通结构
26,36,36a,46承载部
26a绝缘部位
26b,360金属部位
260绝缘材
261,361线路层
27,91胶材
363 导电柱
42 绝缘保护层
432,463导电柱体
440 凹口
51 有源元件
52 无源元件
53 导电凸块
54 焊锡球
90 承载板
t1,t2,t3,t4厚度
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所公开的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附附图所示出的结构、比例、大小等，均仅用以配合说明书所公开的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所公开的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2C为本发明的内埋元件的封装结构2的制法的剖面示意图。于本实施例中，采用大版面规格封装(Panel Level Packaging，简称PLP)技术制作该封装结构2。
如图2A所示，提供于一承载部26及一半导体芯片20，该半导体芯片20具有相对的作用面20a与晶背20b，且该作用面20a上形成有多个接点200。其中，先以沉积、溅镀、化学气相沉积(chemical vapor deposition，简称CVD)或电镀的方式于该半导体芯片20的晶背20b上进行金属化，以形成为多个金属层，供作为缓冲部21。
于本实施例中，该承载部26包括至少一图案化线路层261及与其相结合的绝缘材260，且该承载部26的线路层261设有外露的多个电极垫262，以供结合外部元件(如图5所示的有源元件51、无源元件52、导电凸块53、焊锡球54的其中的一者或其组合)。例如，该承载部26为具有核心层与线路结构的封装基板(substrate)或无核心层(coreless)的线路结构，其于介电材上形成线路层261，如扇出(fan out)型重布线路层(redistributionlayer，简称RDL)。应可理解地，该承载部26亦可为其它可供承载如芯片等电子元件的基材，例如金属(如Cu,Al,Ni,SUS)图案化结构陶瓷、或多层布线结构，并无特别限制。
再者，该半导体芯片20结合于该承载部26的绝缘材260所形成的绝缘部位26a，且该胶材27以大致均匀的厚度布设于该承载部26对应置放该半导体芯片20的区域，故该胶材27的布设面积略相当于该缓冲部21的布设面积(或该半导体芯片20的晶背20b的面积)。或者，该半导体芯片20亦可结合于该承载部26的线路层261所形成的金属部位26b，如图3A所示。
另外，该缓冲部21形成于该半导体芯片20的晶背20b，供作为金属缓冲及粘着界面，其为复合式金属组合，如图2D所示的包含多层相堆叠的金属层。例如，该缓冲部21的组成包括从该半导体芯片20的晶背20b朝外依序堆叠结合的一第一钛层(Ti)211、镍层(Ni)212、第二钛层(Ti)213及银层(Ag)214等四层金属层。
进一步，该第一钛层211的厚度t1为0.01至2微米、该镍层212的厚度t2为0.01至2微米、该第二钛层213的厚度t3为0.0001至2微米及该银层214的厚度t4为0.01至10微米。该缓冲部21的各金属层的厚度可依需求设计，并无特别限制。因此，有关该第一钛层211、镍层212、第二钛层213及银层214等各层的厚度t1～t4可依封装形式的需求进行调整，并不限于上述
应可理解地，有关该缓冲部21的金属组合种类繁多，如Ti/Ni/Ti/Ag，Ti/Ni/Ag/Ni，Ti/Ni/Ti/Au，Ti/Au/Ti/Ni/V/Au等，但不限于上述。较佳为Ti/Ni/Ti/Ag。
如图2B所示，将该半导体芯片20以其上的缓冲部21的侧结合至该承载部26上的胶材27上。
于本实施例中，该胶材27为一种导热银胶，其作为半导体芯片20与承载部26的连接，且常需180℃至270℃的烘烤。
如图2C所示，形成一绝缘层22于该承载部26上，以令该绝缘层22包覆该半导体芯片20。接着，形成一增层线路结构23于该绝缘层22上，且令该增层线路结构23电性连接多个接点200，并于该绝缘层22内嵌埋有多个导通结构24，以电性连接该承载部26及该增层线路结构23，并且据以形成一载板结构2a，其包括一设于该承载部26上的绝缘层22、多个嵌埋于该绝缘层22内的导通结构24及一设于该绝缘层22上的增层线路结构23。
于本实施例中，形成该绝缘层22的材质为聚酰亚胺(polyimide，简称PI)、ABF(Ajinomoto Build-up Film)、感光型有机材料、环氧膜压树脂(epoxy molding compound，简称EMC)等封装材，但并不限于上述。例如，可用压合(lamination)或模压(molding)的方式将该绝缘层22形成于该承载部26上。
再者，可于该绝缘层22上形成多个外露多个接点200的开孔，以利于该增层线路结构23连接该接点200。例如，该半导体芯片20通过铜导体232电性连接该增层线路结构23为最佳。
另外，该增层线路结构23具有至少一介电层230及至少一结合该介电层230的线路重布层(Redistribution layer，简称RDL)231，且该线路重布层231可通过导电盲孔或导电柱(如铜导体232)电性连接该接点200，并于该增层线路结构23的最外侧的线路重布层231上设有外露的多个电极垫233，以供结合外部元件(如图5所示的有源元件51、无源元件52、导电凸块53、焊锡球54的其中的一者或其组合)。例如，形成该线路重布层231的材质为铜，且形成该介电层230的材质为如ABF、感光型有机材料、EMC、聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材。
另外，该导通结构24为导电柱(如图2C所示)及/或导电通孔(如图3A所示的载板结构3a，其导通结构34与该线路重布层231为一体成形)，且该承载部26的线路层261通过该导通结构24与该增层线路结构23电性连接。于另一实施例中，该承载部36亦可埋设于该绝缘层22中，如图3B所示的载板结构3b，其包含一用以承载该半导体芯片20的金属部位360(作为置晶垫)及用以设置及电性连接该导通结构24的线路层361(其具有多个电极垫362)，且该绝缘材260为该绝缘层22的其中一部分。
应可理解地，该承载部36a亦可具有呈堆叠且电性相连接的多个图案化线路层261，如图3C所示的载板结构3c，其包含多个电性连接各层间线路层261的导电盲孔或导电柱363，并于最外侧的线路层261上设有外露的多个电极垫364，以供结合外部元件。
因此，本发明的结构特征主要通过多层金属层作为缓冲部21，用于该半导体芯片20与该胶材27之间的缓冲，以防止环境冲击的分离，故相较于现有技术，本发明的内埋元件的封装结构2能提高该半导体芯片20与该承载部26,36,36a之间的接合力，且能提升该封装结构2的可靠度。
再者，若以第一钛层(Ti)211、镍层(Ni)212、第二钛层(Ti)213及银层(Ag)214等四层金属层作为该缓冲部21，其亦可作为粘着导电界面，并可提高接合力，以提升可靠度能力。
另外，本发明公开的封装结构2，其关于该承载部26、导通结构24及增层线路结构23的工艺种类繁多，可依需求选用。例如，以导电柱体工艺取代导电盲孔工艺，如图4A所示的载板结构4a，其承载部46(或增层线路结构43)以导电柱体463(或导电柱体432)电性导通上下层的线路层261(或线路重布层231)；或者，例如，该导电柱44亦可连结于该承载部36且外露于该绝缘层22的侧面，如图4B所示的载板结构4b，其于外露的该电极垫362的侧边形成一弧形凹口440，并以绝缘保护层42覆盖该线路重布层231，此时，该承载部36的功用则为电性连接垫层，如平面网格阵列封装(Land grid array，简称LGA)型焊垫，以当该封装结构2的电极垫362通过焊料组装至一电路板(图略)上时，可由该凹口440处利用光学检查观看该焊锡材料的结合情况，故此方法可避免安装一应用该封装结构2的车载电子部件(图略)时品质不良的问题。
本发明提供一种内埋元件的封装结构2，包括：一载板结构2a,3a,3b,3c,4a,4b以及至少一内埋于该载板结构2a,3a,3b,3c,4a,4b内的半导体芯片20。
所述的载板结构2a,3a,3b,3c,4a,4b包含一承载部26,36,36a,46、一设于该承载部26,36,36a,46上的绝缘层22、多个嵌埋于该绝缘层22内的导通结构24,34,44及一设于该绝缘层22上的增层线路结构23,43，其中，该承载部26,36,36a,46包括至少一图案化线路层261,361以及与其相结合的绝缘材260，且该线路层261,361通过该导通结构24,34,44与该增层线路结构23,43电性连接。
所述的半导体芯片20内埋于该绝缘层22内并电性连接于该增层线路结构23,43，且该半导体芯片20的晶背20b金属化为多个金属层，供作为缓冲部21，以令该半导体芯片20以该多个金属层的侧通过一胶材27粘设于该承载部26,36,36a,46上，其中，该多个金属层的组成包括由内而外依序堆叠结合的一第一钛层211、一镍层212、一第二钛层213及一银层214。
于一实施例中，该半导体芯片20通过铜导体232电性连接该增层线路结构23。
于一实施例中，该导通结构24,34为导电柱及/或导电通孔。
于一实施例中，该半导体芯片20结合于该承载部26,36,36a,46的金属部位26b,360或绝缘部位26a。
于一实施例中，该承载部46具有呈堆叠且电性相连接的多个图案化线路层261。
于一实施例中，该承载部26,36,36a,46及/或该增层线路结构23,43设有外露的多个电极垫262,362,364,233，以供结合外部元件。例如，该承载部36于外露的该电极垫362的侧边形成有一弧形凹口440。或者，该外部元件包括有源元件51、无源元件52、导电凸块53、焊锡球54中的至少一个。
综上所述，本发明的内埋元件的封装结构通过将该半导体芯片的晶背金属化为多个金属层，供作为缓冲部，以解决半导体芯片与胶材之间因CTE差异大而产生接合力不佳的问题，故本发明的内埋元件的封装结构将更有利于应用在高功率电源管理PMIC、高散热等需求的相关产品，甚至于高信赖性要求的产品。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (8)

1.一种内埋元件的封装结构，包括：
一载板结构，其包含一承载部、一设于该承载部上的绝缘层、多个嵌埋于该绝缘层内的导通结构及一设于该绝缘层上的增层线路结构，其中，该承载部包括至少一图案化线路层以及与其相结合的绝缘材，且该图案化线路层通过该导通结构与该增层线路结构电性连接；以及
至少一半导体芯片，其内埋于该绝缘层内并电性连接于该增层线路结构，且该半导体芯片的晶背金属化为多个金属层，以令该半导体芯片以该多个金属层的侧通过一胶材粘设于该承载部上，其中，该多个金属层的组成包括由内而外依序堆叠结合的一第一钛层、一镍层、一第二钛层及一银层。
2.如权利要求1所述的内埋元件的封装结构，其中，该半导体芯片通过铜导体电性连接该增层线路结构。
3.如权利要求1所述的内埋元件的封装结构，其中，该导通结构为导电柱及/或导电通孔。
4.如权利要求1所述的内埋元件的封装结构，其中，该半导体芯片结合于该承载部的金属部位或绝缘部位。
5.如权利要求1所述的内埋元件的封装结构，其中，该承载部具有呈堆叠且电性相连接的多个图案化线路层。
6.如权利要求1所述的内埋元件的封装结构，其中，该承载部及/或该增层线路结构设有外露的多个电极垫，以供结合外部元件。
7.如权利要求6所述的内埋元件的封装结构，其中，该承载部于外露的该电极垫的侧边形成有一弧形凹口。
8.如权利要求6所述的内埋元件的封装结构，其中，该外部元件包括有源元件、无源元件、导电凸块、焊锡球中的至少一个。
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