J294671 九、發明說明： ^ 【發明所屬之技術領域】 本發明係有關一種晶粒嵌體結構及其製造方法，特別 是有關於一種加強晶粒與金屬層及晶粒與載板之黏結能力 - 的結構及其製程。 _ 【先前技術】 表面黏著（Surface Mount Technology，SMT)構裝技術 φ 中，將晶粒固定於構裝載板的製程稱為晶粒黏結（DieJ294671 IX. INSTRUCTIONS: ^ Technical Field of the Invention The present invention relates to a die inlay structure and a method of manufacturing the same, and more particularly to a bonding ability of a reinforcing die and a metal layer and a die and a carrier plate - Structure and its process. _ [Prior Art] Surface Mount Technology (SMT) structuring technology φ, the process of fixing the die to the mounting plate is called die bonding (Die
Attach或Die Mount )。晶粒黏結有許多方式，其中以銲結 材料黏結晶粒之方法如第1圖，先前技術之晶粒與銲接材 料剖面示意圖。首先’為獲得較佳的晶粒P20與載板P1 〇 結合性，可先於晶粒背面鍍上一金屬層P30，再使用 塗佈（或網印）於載板P10上的銲接材料P40來黏貼該金 屬層P30與載板P10，並予以迴銲後產生合金接合。 惟，上述習知之銲接黏結方式，雖可以銲接材料P40 •來緊密銲接接合該金屬層P3〇與該載板no，但在將來對 製品進行各種可靠性試驗時該載板P10上的鋒接材料_ 銲接接合的該金屬層P30僅為—平面，再無任何向上勺罗 之結構，此為降低其銲接強度之重要因素。 G復 【發明内容】 本發明之晶粒肷體結構及其製造方法掸 ...9進晶勒^鱼令 屬層之接合強度舁至屬層與銲接材料之銲接 /、一 攻哎，進而提 .1294671 高產品可靠度。 為達成上述增進晶粒與金屬層之接合強度與金屬層與 銲接材料之銲接強度之目的，本發明提供一種晶粒嵌體結 構，包含：一背面四邊各設有至少一切槽之晶粒；及一金 屬層，該金屬層成形於該晶粒之背面上並填滿該切槽以形 成複數個嵌體。據此結構，在將該帶有嵌體之晶粒銲於載 板上時，該侧立面的嵌體提供銲接材料之一包覆帶狀結 構，可產生較佳之銲接強度。 本發明之再一目的係提供一運用上述晶粒嵌體結構來 製成一接合度佳之封裝製品，以提高製品可靠性。 由於在本發明中固定晶粒的鲜接材料係直接對晶背的 金屬層材質作黏定，加上本發明之晶背的金屬層係嵌設於 晶粒之四邊，在將來對製品進行結合度的可靠性試驗時， 晶粒與金屬層的結合度佳而不易脫層；另一點，]本發明 中’載板上的鲜接材料鲜接接合的晶粒金屬層具有傲入結 構，可在晶粒之外側立面形成包覆之帶狀結構，銲接材料 會沿著後體而包覆部分晶粒之外侧立面，使銲接材料不僅 僅是與晶背銲接，成為加強晶粒與載板間銲接強度之重要 因素。 【實施方式】 茲配合圖式將本發明較佳實施例詳細說明如下。 請參閱第2圖，本發明晶粒之背面嵌體結構剖面示意 圖。其晶粒欲體結構，包含一晶粒30及一金屬層22 : • 1294671 该晶粒30之該背面31的四個邊緣各設有至少一切样 21，違些切槽21乃包括彼此呈垂直分佈之複數個切槽Μ ◦ 5亥金屬層22形成於該晶粒30之該背面31上，該金屬声 22於形成同時並會填滿該些切槽21之凹陷區域，在該些切 槽21的凹陷區域之金屬層22乃形成複數個嵌體23，而在垂 直分佈之若干該些切槽21之結構下，該些嵌體23則形成分 佈於该晶粒30之四邊侧面。 續請參閱第3圖，本發明之封裝件結構剖面示意圖。 本發明之該封裝件1 〇包含如前述之該結構，包含一晶粒 3〇、一金屬層22及一載板60 : 該晶粒30之該背面31四個邊緣上各設有至少一切槽 21。 日 該金屬層22形成於該晶粒30之該背面31上並填滿該些 切槽21以形成至少一嵌體23。 一 該載板60並以一銲接材料70與該金屬層22接合。 如第4圖（A)至（D)，本發明之晶粒之背面嵌體及封 裝件製作方法示意圖。 首先，凊芩照第4圖（A)所示，根據上述結構，本發 明在製造該晶粒嵌體結構之步驟包括：預先以一第一切割 刀40切割一晶圓2〇之背面形成至少一切槽21(步驟sl〇)， 該第一切割刀40僅需切入該晶圓20之背面矽層少許形成凹 槽狀即可。又該切槽21係可呈格狀分佈者。 睛芩閱第4圖（B)及（C)所示，續形成一金屬層22於 /日日圓20之月面上，a玄鍍於晶圓2〇石夕層上的金屬層22在形 1294671 成時，可同時填滿該切槽21形成至少一嵌體23(步驟 S20)，當然，若該切槽21彼此形成方格狀時，該嵌體23亦 將分佈於該晶圓20背面且隨之構成方格狀；以一刃寬小於 該第一切割刀40之一第二切割刀50切割該晶圓20為複數個 晶粒30(步驟S30)，此時，因該第一切割刀40與該第二切 割刀5 0之刃寬差所形成之該嵌體2 3係形成於該晶粒3 0之四 側邊。 運用本製成之晶粒30所形成之封裝件10製作方法包 括：一運用上述該晶粒嵌體結構之步驟（步驟S10〜步驟 S30)，繼而配置至少一該晶粒30於一載板60之銲接材料70 上（步驟S40)。再進行迴銲，以使該晶粒30藉由該金屬層 22接合於該載板60上（步驟S50)。 緣是，該晶粒30四側之該嵌體23呈上嵌狀，在將該晶 粒30黏於該銲接材料70時，該銲接材料70可進一步包覆至 該晶粒30四侧之該嵌體23上，形成一包覆帶狀結構E，請 同時參閱第3圖所示，此結構將提供較佳之銲接材料70與 晶粒30之銲接強度。 當然，上述封裝件10所稱載板60，可運用包含印刷電 路板（Printed Circuit Board，PCB)、基板（Substrate)或導 線架（Leadframe)等各種製品。 由上述可知，當知本案所創作之覆晶黏晶粒封裝製程 已具有產業利用性、新穎性與進步性，符合發明專利要 件。惟以上所述者，僅為本發明之一較佳實施例而已，並 非用來限定本發明實施之範圍。即凡依本發明申請專利範 1294671 圍所做的均等變化與修飾，皆為本發明專利範圍所涵蓋。 【圖式簡單說明】 第1圖係先前技術之晶粒與鲜接材料剖面不意圖。 第2圖係本發明晶粒之背面嵌體結構剖面示意圖。 第3圖係本發明之封裝件結構剖面示意圖。 第4圖（A)至（D)係本發明之晶粒之背面嵌體及封裝件 製作方法示意圖。Attach or Die Mount). There are many ways of grain bonding, in which the method of adhering the material to the grain of the bonding material is as shown in Fig. 1, the schematic diagram of the prior art grain and welding material. Firstly, in order to obtain a better bond between the crystal grain P20 and the carrier P1, a metal layer P30 may be plated on the back side of the die, and then the solder material P40 coated (or screen printed) on the carrier P10 may be used. The metal layer P30 and the carrier P10 are pasted and re-welded to form an alloy bond. However, the above-mentioned conventional welding bonding method can weld the material P40 to tightly weld the metal layer P3 and the carrier no, but the front material of the carrier P10 is tested in various reliability tests in the future. _ The metal layer P30 of the solder joint is only a plane, and there is no structure of the upward scoop, which is an important factor for reducing the welding strength. G complex [Summary of the Invention] The structure of the crystal corpus callosum of the present invention and the manufacturing method thereof are as follows: the bonding strength of the layer 9 into the crystal layer is welded to the solder layer of the genus layer and the solder material, and further提.1294671 High product reliability. In order to achieve the above-mentioned purpose of enhancing the bonding strength between the die and the metal layer and the welding strength of the metal layer and the solder material, the present invention provides a die inlay structure comprising: a die having at least all grooves on each of the back sides; A metal layer formed on the back side of the die and filling the grooving to form a plurality of inlays. According to this configuration, when the inlay-containing crystal grain is welded to the carrier, the inlay of the side elevation provides a ribbon-like structure of one of the solder materials, which can produce a better soldering strength. It is still another object of the present invention to provide a packaged article having a good bonding degree by using the above-described die inlay structure to improve the reliability of the article. Since the fresh-bonding material for fixing the crystal grains in the present invention directly bonds the material of the metal back layer of the crystal back, and the metal layer of the crystal back of the present invention is embedded on the four sides of the crystal grain, the product is combined in the future. In the reliability test, the degree of bonding between the crystal grains and the metal layer is good and the layer is not easily delaminated; in another aspect, the grain metal layer of the fresh joint material on the carrier plate in the present invention has a proud structure. A strip-like structure is formed on the outer side surface of the crystal grain, and the solder material covers a part of the outer side surface of the crystal grain along the rear body, so that the solder material is not only welded to the crystal back, but also strengthens the crystal grain and the load. An important factor in the strength of the welding between the plates. [Embodiment] A preferred embodiment of the present invention will be described in detail below with reference to the drawings. Referring to Figure 2, there is shown a cross-sectional view of the backside inlay structure of the die of the present invention. The die-like structure includes a die 30 and a metal layer 22: • 1294671 The four edges of the back face 31 of the die 30 are each provided with at least 21, and the slits 21 are perpendicular to each other. A plurality of grooving layers ◦ 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥The metal layer 22 of the recessed region of 21 forms a plurality of inlays 23, and the inlays 23 are formed on the four sides of the die 30 under the structure of a plurality of the slits 21 vertically distributed. Continuing to refer to FIG. 3, a schematic cross-sectional view of the package structure of the present invention. The package 1 of the present invention comprises the structure as described above, comprising a die 3〇, a metal layer 22 and a carrier 60: the back surface 31 of the die 30 has at least all slots on each of the four edges. twenty one. The metal layer 22 is formed on the back surface 31 of the die 30 and fills the slots 21 to form at least one inlay 23. A carrier 60 is bonded to the metal layer 22 by a solder material 70. 4(A) to (D), a schematic diagram of a method of fabricating a backside inlay and a package of the present invention. First, as shown in FIG. 4(A), according to the above structure, the step of fabricating the die inlay structure of the present invention includes: cutting a back surface of a wafer 2 by a first cutting blade 40 in advance to form at least All the grooves 21 (step sl), the first cutting blade 40 only needs to be cut into the back surface of the wafer 20 to form a groove shape. Further, the slits 21 can be distributed in a lattice shape. As shown in Fig. 4 (B) and (C), a metal layer 22 is formed on the moon surface of the Japanese yen 20, and a metal layer 22 on the wafer 2 is formed. 1294671, at the same time, the slit 21 can be filled at the same time to form at least one inlay 23 (step S20). Of course, if the slits 21 are formed in a checkered shape, the inlay 23 will also be distributed on the back of the wafer 20. And forming a square shape; the wafer 20 is cut into a plurality of crystal grains 30 by a second cutting blade 50 having a blade width smaller than the first cutting blade 40 (step S30). At this time, the first cutting is performed. The inlay 2 3 formed by the width difference between the blade 40 and the second cutting blade 50 is formed on the four sides of the die 30. The method for fabricating the package 10 formed by using the formed die 30 includes: applying the step of the die inlay structure (steps S10 to S30), and then arranging at least one die 30 on a carrier 60. The solder material 70 is on (step S40). Reflow is performed so that the die 30 is bonded to the carrier 60 by the metal layer 22 (step S50). The inlay 24 on the four sides of the die 30 is in an in-line shape. When the die 30 is adhered to the solder material 70, the solder material 70 may be further coated on the four sides of the die 30. On the inlay 23, a cladding strip structure E is formed. Please refer to FIG. 3 at the same time, which will provide a better welding strength between the solder material 70 and the die 30. Of course, the carrier board 60 referred to in the above package 10 can be used in various products including a printed circuit board (PCB), a substrate (Substrate), or a lead frame. It can be seen from the above that when it is known that the flip-chip paste crystal packaging process created by the present invention has industrial applicability, novelty and progress, it meets the patent requirements of the invention. However, the above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. That is, the equivalent changes and modifications made by the patent application No. 1294671 of the present invention are covered by the scope of the invention. [Simple description of the drawings] Fig. 1 is a schematic view of the prior art die and fresh joint material. Fig. 2 is a schematic cross-sectional view showing the back inlay structure of the crystal grain of the present invention. Figure 3 is a schematic cross-sectional view showing the structure of the package of the present invention. Fig. 4 (A) to (D) are schematic views showing a method of fabricating a backside inlay of a die of the present invention and a package.
【主要元件符號說明】 [先前技術部分] P10載板 P20晶粒 P30金屬層 P40銲接材料 [本發明技術部份] 10封裝件 20晶圓 21切槽 22金屬層 23嵌體 30晶粒 31背面 40第一切割刀 50第二切割刀 .1294671 60載板 70銲接材料 步驟S10預先以一第一切割刀切割一晶圓之背面形成 至少一切槽 步驟S20形成一金屬層於該晶圓之背面上，該金屬層 填滿該切槽形成至少一嵌體 步驟S30以一第二切割刀切割該晶圓為複數個晶粒 步驟S40配置至少一該晶粒於一載板之銲接材料上 步驟S50進行迴銲，以使該晶粒藉由該金屬層接合於 該載板上[Major component symbol description] [Previous technical part] P10 carrier P20 die P30 metal layer P40 solder material [Technical part of the present invention] 10 package 20 wafer 21 grooving 22 metal layer 23 inlay 30 die 31 back 40 first cutting blade 50 second cutting blade. 1129671 60 carrier plate 70 soldering material step S10, in advance, a first cutting blade is used to cut the back surface of a wafer to form at least all the grooves. Step S20 forms a metal layer on the back surface of the wafer. The metal layer fills the sipe to form at least one inlay step S30, and the second dicing blade cuts the wafer into a plurality of dies. Step S40 aligns at least one of the dies on a solder material of a carrier plate. Reflowing so that the die is bonded to the carrier by the metal layer