TWI652788B - 晶片封裝結構及晶片封裝結構陣列 - Google Patents

晶片封裝結構及晶片封裝結構陣列 Download PDF

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TWI652788B
TWI652788B TW106138745A TW106138745A TWI652788B TW I652788 B TWI652788 B TW I652788B TW 106138745 A TW106138745 A TW 106138745A TW 106138745 A TW106138745 A TW 106138745A TW I652788 B TWI652788 B TW I652788B
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chip
conductive pillars
conductive
item
patent application
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TW106138745A
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TW201919191A (zh
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張文遠
徐業奇
呂學忠
陳偉政
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大陸商上海兆芯集成電路有限公司
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Priority to TW106138745A priority Critical patent/TWI652788B/zh
Priority to US15/842,822 priority patent/US10504847B2/en
Priority to CN201810156851.3A priority patent/CN108364919A/zh
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Publication of TWI652788B publication Critical patent/TWI652788B/zh
Publication of TW201919191A publication Critical patent/TW201919191A/zh

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Abstract

一種晶片封裝結構包括多個第一晶片、多個第一導電柱、一第二晶片、多個第二導電柱、一封裝材料及一重佈線路結構。各第一晶片具有一第一主動面。各第一導電柱配置於對應的第一晶片的第一主動面上。第二晶片的一第二主動面經由這些第二導電柱電連接這些第一晶片的這些第一主動面。封裝材料局部地覆蓋這些第一晶片、這些第一導電柱、第二晶片及這些第二導電柱。重佈線路結構配置在封裝材料上並連接這些第一導電柱。一種電子結構陣列亦被提出。

Description

晶片封裝結構及晶片封裝結構陣列
本發明是有關於一種晶片封裝結構及晶片封裝結構陣列。
在晶片封裝技術領域中，有一種封裝類型是將積體電路晶片（IC chip）安裝在線路基板（circuit substrate）上，並經由線路基板電連接至下一層級的電子元件，例如主機板或模組板等。依照實際需求，可將多個晶片安裝在同一線路基板上而構成一多晶片封裝結構，而這些晶片可通過線路基板來彼此傳輸訊號。然而，目前的線路基板的線寬（line width）和線距（line pitch）無法符合在多晶片之間傳遞訊號的要求。
本發明提供一種晶片封裝結構，可符合在多晶片之間傳遞訊號的要求。
本發明提供一種晶片封裝結構陣列，可切割出多個晶片封裝結構，其符合在多晶片之間傳遞訊號的要求。
本發明的晶片封裝結構包括多個第一晶片、多個第一導電柱、一第二晶片、多個第二導電柱、一封裝材料及一重佈線路結構。各第一晶片具有一第一主動面。各第一導電柱配置於對應的第一晶片的第一主動面上。第二晶片具有一第二主動面。第二晶片的第二主動面經由這些第二導電柱電連接這些第一晶片的這些第一主動面。封裝材料覆蓋這些第一晶片、這些第一導電柱、第二晶片及這些第二導電柱。重佈線路結構配置在封裝材料上並連接這些第一導電柱。
本發明提供一種晶片封裝結構陣列，包括多個晶片封裝結構。晶片封裝結構適於陣列排列以形成晶片封裝結構陣列。各晶片封裝結構包括多個第一晶片、多個第一導電柱、一第二晶片、多個第二導電柱、一封裝材料及一重佈線路結構。各第一晶片具有一第一主動面。各第一導電柱配置於對應的第一晶片的第一主動面上。第二晶片具有一第二主動面。第二晶片的第二主動面經由這些第二導電柱電連接這些第一晶片的這些第一主動面。封裝材料覆蓋這些第一晶片、這些第一導電柱、第二晶片及這些第二導電柱。重佈線路結構配置在封裝材料上並連接這些第一導電柱。
基於上述，在本發明中，經由一晶片面對面地電連接至少另外兩個晶片，故可提供較高的連接路徑密度及較短的連接路徑長度。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
請參考圖1A，依照本實施例的晶片封裝方法，首先，將多個第一晶片110（例如：110-1、110-2）配置在一載板102上。各第一晶片110具有一第一主動面110a，且多個第一導電柱112配置在各第一主動面110a上。具體而言，這些第一導電柱112分別配置於對應的第一晶片110的第一主動面110a的多個接墊（未繪示）上。
請參考圖1B，經由多個第二導電柱122將一第二晶片120的一第二主動面120a電連接這些第一晶片110的這些第一主動面110a。具體而言，經由這些第二導電柱122將第二晶片120的第二主動面120a的多個接墊（未繪示）電連接這些第一晶片110的這些第一主動面110a的多個接墊（未繪示）。在本實施例中，第一晶片110-1的部分第一主動面110a與第二晶片120的部分第二主動面120a彼此相對，且第一晶片110-1的部分第一主動面110a在載板102的正投影與第二晶片120的部分第二主動面120a在載板102的正投影重疊。在本實施例中，第一晶片110-2的部分第一主動面110a與第二晶片120的部分第二主動面120a彼此相對，且第一晶片110-1的部分第一主動面110a在載板102的正投影與第二晶片120的部分第二主動面120a在載板102的正投影重疊。因此，第一晶片110-1可經由第一晶片110-1上的這些第二導電柱122、第二晶片120、第一晶片110-2上的這些第二導電柱122，而與第一晶片110-2彼此電連接，以提供較大的連接路徑密度及較短的連接路徑長度。在本實施例中，這些第二導電柱122的分布密度可大於這些第一導電柱112的分布密度。此外，這些第二導電柱122在載板102的正投影面積可不大於這些第一導電柱112在載板102的正投影面積。另外，這些第二導電柱122相對於第一主動面110a的高度不大於這些第一導電柱112相對於第一主動面110a的高度。
請參考圖1C，將一支撐結構130配置在載板102上並圍繞這些第一晶片110。在本實施例中，支撐結構130具有一開口130a，其包圍這些第一晶片110。支撐結構130有助於提高結構強度及減少翹曲程度。
請參考圖1D，形成一封裝材料140（encapsulated material），例如模塑料（molding compound）。封裝材料140局部地覆蓋這些第一晶片110、這些第一導電柱112、第二晶片120、這些第二導電柱122及支撐結構130。
請參考圖1E，部分地移除封裝材料140，以暴露出各第一導電柱112。在本實施例中，部分地移除封裝材料140的方式包括研磨（polishing）。封裝材料140維持覆蓋二晶片120。
請參考圖1F，形成一重佈線路結構150在封裝材料140上，用以重新分布訊號輸出或輸入的位置。在本實施例中，重佈線路結構150包括多個圖案化導電層152、多個介電層154及多個導電孔道156，這些介電層154與這些圖案化導電層152交替疊合，且各導電孔道156位於對應的介電層154中並電連接對應的這些圖案化導電層152。這些第一晶片110除可經由第二晶片120彼此電連接以外，也可經由重佈線路結構150彼此電連接。具體而言，第一晶片110-1經由第一晶片110-1上的這些第一導電柱112、重佈線路結構150的圖案化導電層152、第一晶片110-2上的這些第一導電柱112，而與第一晶片110-2彼此電連接。而且，第一晶片110-1也可經由第一晶片110-1上的這些第二導電柱122、第二晶片120、第一晶片110-2上的這些第二導電柱122而與第一晶片110-2彼此電連接。換言之，第一晶片110-1與第一晶片110-2之間的連接路徑至少有上述兩條連接路徑。
請參考圖1G，在形成重佈線路結構150之後，移除載板102，因而暴露出這些第一晶片110的一第一背面110b。此時，這些第一晶片110的一第一背面110b、裸露的封裝材料140、支撐結構130彼此共平面。
請參考圖1H，重佈線路結構150具有多個重佈線路接墊150a，其可由最外的圖案化導電層152所構成。在如圖1G移除載板102之後，在重佈線路結構150的每個重佈線路接墊150a上形成一導電接點160，例如銲球，用以連接下一層級的電子元件，例如線路板。
當以批次方式來生產多個晶片封裝結構100時，將由多個第一晶片110及至少一第二晶片120所構成的多個晶片群組G（圖1B僅繪示這些晶片群組G之一群組）配置在載板102上。因此，請參考圖1G，在形成這些導電接點160之前，可先執行單顆化的步驟，即沿切割線L來切割重佈線路結構150、封裝材料140及支撐結構130，以分離這些晶片群組G。此時，支撐結構130裸露於封裝材料140的一側面140a。因此，每個晶片封裝結構100包含一個晶片群組G，且包含重佈線路結構150（即切割後的重佈線路結構150的一部分）及封裝材料140（即切割後的封裝材料140的一部分）。
同樣地，當以批次方式來生產多個晶片封裝結構100時，支撐結構130具有以陣列排列的多個開口130a，如圖2所示，而各個開口130a圍繞對應的一個晶片群組G，如圖1C所示。因此，如圖1H所示，每個晶片封裝結構100包含支撐結構130（即切割後的支撐結構130的一部分）。
在本實施例中，以陣列排列且尚未切割的多個晶片封裝結構100可構成一晶片封裝結構陣列50，如圖1G所示。換句話說，晶片封裝結構陣列50包括以陣列排列且尚未切割的多個晶片封裝結構100。具體而言，各晶片封裝結構100包括多個第一晶片110（例如110-1、110-2）、多個第一導電柱112、一第二晶片120、多個第二導電柱122、一封裝材料140及一重佈線路結構150。各第一晶片110（例如110-1或110-2）具有一第一主動面110a。各第一導電柱112配置於對應的第一晶片110的第一主動面110a上。第二晶片120具有一第二主動面120a。第二晶片120的第二主動面120a經由這些第二導電柱122電連接這些第一晶片110的這些第一主動面110a。封裝材料140局部地覆蓋這些第一晶片110、這些第一導電柱112、第二晶片120及這些第二導電柱122。重佈線路結構150配置在封裝材料140上並連接這些第一導電柱112。
當晶片封裝結構陣列50的各別晶片封裝結構100的外圍區域配置有一支撐結構130（見圖2）時，可以減少晶片封裝結構陣列50封裝過程中發生的翹曲，並且能提升晶片封裝結構陣列50的結構強度且降低其製程的生產成本，進而增加晶片封裝結構100的產量。
在另一實施例中，如圖4所示，相較於圖1A至圖1H所示的實施例，當載板102的材料採用散熱材料時，可保留圖1F的載板102，使得完成封裝的晶片封裝結構100可包含圖1H的載板102（即切割後的載板102的一部分）作為一散熱件。此時，支撐結構130裸露於封裝材料140的一側面140a及載板102的一側面102a。
在另一實施例中，如圖5所示，相較於圖1A至圖1H所示的實施例，可省略圖1C的支撐結構130，使得最後封裝完成的晶片封裝結構100沒有圖1H的支撐結構130。
在另一實施例中，如圖6所示，相較於圖1A至圖1H所示的實施例，可省略圖1C的支撐結構130而保留圖1F的載板102，使得最後封裝完成的晶片封裝結構100沒有支撐結構130，而包含圖1H的載板102（即切割後的載板102的一部分）作為一散熱件。
晶片封裝結構100在圖4至圖6的各種變化也可應用於圖1G所示的晶片封裝結構陣列50。舉例而言，尚未切割的晶片封裝結構陣列50也可包含尚未切割的載板102，如圖1F、圖4及圖6所示，且載板102可作為尚未切割的散熱件。此外，尚未切割的晶片封裝結構陣列50也可不包含尚未切割的支撐結構130，如圖5所示。
在圖1H的實施例中，晶片封裝結構100包括多個第一晶片110（例如：110-1、110-2）、多個第一導電柱112、一第二晶片120、多個第二導電柱122、一封裝材料140及一重佈線路結構150。各第一晶片110具有一第一主動面110a，而各第一導電柱112配置於對應的第一晶片110的第一主動面110a上。第二晶片120具有一第二主動面120a。在本實施例中，第一晶片110-1的部分第一主動面110a與第二晶片120的部分第二主動面120a彼此相對，且第一晶片110-1的部分第一主動面110a在第一晶片110-1的第一背面110b的正投影與第二晶片120的部分第二主動面120a在第一晶片110-1的第一背面110b的正投影重疊。在本實施例中，第一晶片110-2的部分第一主動面110a與第二晶片120的部分第二主動面120a彼此相對，且第一晶片110-1的部分第一主動面110a在第一晶片110-2的第一背面110b的正投影與第二晶片120的部分第二主動面120a在第一晶片110-2的第一背面110b的正投影重疊。
第二晶片120的第二主動面120a經由這些第二導電柱122電連接這些第一晶片110（例如：110-1、110-2）的這些第一主動面110a。封裝材料140局部地覆蓋這些第一晶片110、這些第一導電柱112、第二晶片120及這些第二導電柱122。重佈線路結構150配置在封裝材料140上並連接這些第一導電柱112。
在圖1H的實施例中，這些第二導電柱122的分布密度大於這些第一導電柱112的分布密度。此外，這些第二導電柱122在這些第一晶片110的正投影面積可不大於這些第一導電柱112在這些第一晶片110的正投影面積。另外，這些第二導電柱122相對於第一主動面110a的高度不大於這些第一導電柱112相對於第一主動面110a的高度。封裝材料140的一部分位於第二晶片120與重佈線路結構150之間，並覆蓋第二晶片120的一第二背面120b。重佈線路結構150包括多個圖案化導電層152、多個介電層154及多個導電孔道156，這些介電層154與這些圖案化導電層152交替疊合，且各導電孔道156位於對應的介電層154中並電連接對應的這些圖案化導電層152。
在圖1H的實施例中，晶片封裝結構100更包括一支撐結構130。支撐結構130圍繞這些第一晶片110並與封裝材料140相嵌合。支撐結構130裸露於封裝材料140的一側面140a。
在圖1H的實施例中，晶片封裝結構100更包括多個導電接點160，例如銲球。重佈線路結構150具有多個重佈線路接墊150a，且這些導電接點160分別配置在這些重佈線路接墊150a上。
值得說明的是，第一晶片110-1經由第一晶片110-1上的這些第一導電柱112、重佈線路結構150的圖案化導電層152、第一晶片110-2上的這些第一導電柱112，而與第一晶片110-2彼此電連接。而且，第一晶片110-1也可經由第一晶片110-1上的這些第二導電柱122、第二晶片120、第一晶片110-2上的這些第二導電柱122而與第一晶片110-2彼此電連接。換言之，第一晶片110-1與第一晶片110-2之間的連接路徑至少有上述兩條連接路徑。
此外，上述實施例雖然是以一個第二晶片120以面對面的方式連接兩個第一晶片110-1、110-2，但並不以此為限。在其他實施例中，一個第二晶片120也可以連接三個第一晶片（如圖3A的110-1、110-2、110-3）、四個第一晶片（如圖3B的110-1、110-2、110-3、110-4）甚至更多的第一晶片110，其可視使用的需求而定。
在圖4的實施例中，相較於圖1H的實施例，晶片封裝結構100更包括一載板102。載板102的材料為散熱材料，使得載板102可作為一散熱件。這些第一晶片110、封裝材料140及支撐結構130配置於載板102上。支撐結構130裸露於封裝材料140的一側面140a及載板102的一側面102a。
在圖5的實施例中，相較於圖1H的實施例，晶片封裝結構100不具有圖1H的支撐結構130。
在圖6的實施例中，相較於圖5的實施例，晶片封裝結構100更包括一載板102。載板102的材料為散熱材料，使得載板102可作為一散熱件。這些第一晶片110及封裝材料140配置於載板102上。
綜上所述，在本發明中，經由一晶片面對面地電連接至少另外兩個晶片，故可提供較高的連接路徑密度及較短的連接路徑長度。此外，可增加支撐結構來提高結構強度及降低翹曲程度。另外，當載板的材料採用散熱材料時，也可保留載板作為一散熱件。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
50‧‧‧晶片封裝結構陣列
100‧‧‧晶片封裝結構
102‧‧‧載板
102a‧‧‧側面
110、110-1、110-2、110-3、110-4‧‧‧第一晶片
110a‧‧‧第一主動面
110b‧‧‧第一背面
112‧‧‧第一導電柱
120‧‧‧第二晶片
120a‧‧‧第二主動面
120b‧‧‧第二背面
122‧‧‧第二導電柱
130‧‧‧支撐結構
130a‧‧‧開口
140‧‧‧封裝材料
140a‧‧‧側面
150‧‧‧重佈線路結構
150a‧‧‧重佈線路接墊
152‧‧‧圖案化導電層
154‧‧‧介電層
156‧‧‧導電孔道
160‧‧‧導電接點
L‧‧‧切割線
G‧‧‧晶片群組
圖1A至圖1H是依照本發明的一實施例的一種晶片封裝方法的剖面示意圖。 圖2是圖1C的支撐結構包括多個開口的立體圖。 圖3A是依照本發明的另一實施例的第一晶片及第二晶片的俯視圖。 圖3B是依照本發明的另一實施例的第一晶片及第二晶片的俯視圖。 圖4是依照本發明的另一實施例的一種晶片封裝結構的剖面示意圖。 圖5是依照本發明的另一實施例的一種晶片封裝結構的剖面示意圖。 圖6是依照本發明的另一實施例的一種晶片封裝結構的剖面示意圖。

Claims (24)

  1. 一種晶片封裝結構，包括：多個第一晶片，各該第一晶片具有一第一主動面；多個第一導電柱，各該第一導電柱配置於對應的該第一晶片的該第一主動面上；一第二晶片，具有一第二主動面，其中該些第一主動面之一的一部分與該第二主動面的一部分彼此相對；多個第二導電柱，該第二晶片的該第二主動面經由該些第二導電柱電連接該些第一晶片的該些第一主動面；一封裝材料，局部地覆蓋該些第一晶片、該些第一導電柱、該第二晶片及該些第二導電柱；以及一重佈線路結構，配置在該封裝材料上並連接該些第一導電柱。
  2. 如申請專利範圍第1項所述的晶片封裝結構，其中該些第二導電柱的分布密度大於該些第一導電柱的分布密度。
  3. 如申請專利範圍第1項所述的晶片封裝結構，其中該些第二導電柱在該些第一晶片的正投影面積不大於該些第一導電柱在該些第一晶片的正投影面積。
  4. 如申請專利範圍第1項所述的晶片封裝結構，其中該些第二導電柱相對於該第一主動面的高度不大於該些第一導電柱相對於該第一主動面的高度。
  5. 如申請專利範圍第1項所述的晶片封裝結構，其中該些第一晶片經由該重佈線路結構彼此電連接。
  6. 如申請專利範圍第1項所述的晶片封裝結構，其中該封裝材料的一部分位於該二晶片與該重佈線路結構之間。
  7. 如申請專利範圍第1項所述的晶片封裝結構，更包括：一載板，其中該載板的材料為散熱材料以作為一散熱件，且該些第一晶片及該封裝材料配置於該載板上。
  8. 如申請專利範圍第1項所述的晶片封裝結構，更包括：一支撐結構，圍繞該些第一晶片並與該封裝材料相嵌合。
  9. 如申請專利範圍第8項所述的晶片封裝結構，其中該支撐結構裸露於該封裝材料的一側面。
  10. 如申請專利範圍第8項所述的晶片封裝結構，更包括：一載板，其中該載板的材料為散熱材料以作為一散熱件，且該些第一晶片、該封裝材料及該支撐結構配置於該載板上。
  11. 如申請專利範圍第10項所述的晶片封裝結構，其中該支撐結構裸露於該封裝材料的一側面及該載板的一側面。
  12. 如申請專利範圍第1項所述的晶片封裝結構，其中該重佈線路結構包括多個圖案化導電層、多個介電層及多個導電孔道，該些介電層與該些圖案化導電層交替疊合，且各該導電孔道位於對應的該介電層中並電連接對應的該些圖案化導電層。
  13. 如申請專利範圍第1項所述的晶片封裝結構，更包括：多個導電接點，其中該重佈線路結構具有多個重佈線路接墊，且該些導電接點分別配置在該些重佈線路接墊上。
  14. 一種晶片封裝結構陣列，包括：多個晶片封裝結構，適於陣列排列以形成該晶片封裝結構陣列，各該晶片封裝結構包括：多個第一晶片，各該第一晶片具有一第一主動面；多個第一導電柱，各該第一導電柱配置於對應的該第一晶片的該第一主動面上；一第二晶片，具有一第二主動面，其中該些第一主動面之一的一部分與該第二主動面的一部分彼此相對；多個第二導電柱，該第二晶片的該第二主動面經由該些第二導電柱電連接該些第一晶片的該些第一主動面；一封裝材料，局部地覆蓋該些第一晶片、該些第一導電柱、該第二晶片及該些第二導電柱；以及一重佈線路結構，配置在該封裝材料上並連接該些第一導電柱。
  15. 如申請專利範圍第14項所述的晶片封裝結構陣列，其中該些第二導電柱的分布密度大於該些第一導電柱的分布密度。
  16. 如申請專利範圍第14項所述的晶片封裝結構陣列，其中該些第二導電柱在該些第一晶片的正投影面積不大於該些第一導電柱在該些第一晶片的正投影面積。
  17. 如申請專利範圍第14項所述的晶片封裝結構陣列，其中該些第二導電柱相對於該第一主動面的高度不大於該些第一導電柱相對於該第一主動面的高度。
  18. 如申請專利範圍第14項所述的晶片封裝結構陣列，其中該些第一晶片經由該重佈線路結構彼此電連接。
  19. 如申請專利範圍第14項所述的晶片封裝結構陣列，其中該封裝材料的一部分位於該二晶片與該重佈線路結構之間。
  20. 如申請專利範圍第14項所述的晶片封裝結構陣列，其中該晶片封裝結構更包括：一載板，其中該載板的材料為散熱材料以作為一散熱件，且該些第一晶片及該封裝材料配置於該載板上。
  21. 如申請專利範圍第14項所述的晶片封裝結構陣列，其中該晶片封裝結構更包括：一支撐結構，圍繞該些第一晶片並與該封裝材料相嵌合。
  22. 如申請專利範圍第21項所述的晶片封裝結構陣列，其中該晶片封裝結構更包括：一載板，其中該載板的材料為散熱材料以作為一散熱件，且該些第一晶片、該封裝材料及該支撐結構配置於該載板上。
  23. 如申請專利範圍第14項所述的晶片封裝結構陣列，其中該重佈線路結構包括多個圖案化導電層、多個介電層及多個導電孔道，該些介電層與該些圖案化導電層交替疊合，且各該導電孔道位於對應的該介電層中並電連接對應的該些圖案化導電層。
  24. 如申請專利範圍第14項所述的晶片封裝結構陣列，其中該晶片封裝結構更包括：多個導電接點，其中該重佈線路結構具有多個重佈線路接墊，且該些導電接點分別配置在該些重佈線路接墊上。
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US20190139898A1 (en) 2019-05-09

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