TWI565026B - 晶片封裝結構 - Google Patents

晶片封裝結構 Download PDF

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Publication number
TWI565026B
TWI565026B TW101100472A TW101100472A TWI565026B TW I565026 B TWI565026 B TW I565026B TW 101100472 A TW101100472 A TW 101100472A TW 101100472 A TW101100472 A TW 101100472A TW I565026 B TWI565026 B TW I565026B
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Taiwan
Prior art keywords
wafer
wafers
carrier
pair
package structure
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TW101100472A
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English (en)
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TW201330214A (zh
Inventor
張文遠
徐業奇
賴威志
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威盛電子股份有限公司
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Application filed by 威盛電子股份有限公司 filed Critical 威盛電子股份有限公司
Priority to TW101100472A priority Critical patent/TWI565026B/zh
Priority to CN2012100099304A priority patent/CN102543973A/zh
Priority to US13/429,441 priority patent/US9418964B2/en
Publication of TW201330214A publication Critical patent/TW201330214A/zh
Application granted granted Critical
Publication of TWI565026B publication Critical patent/TWI565026B/zh

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    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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Description

晶片封裝結構
本發明是有關於一種晶片封裝結構。
半導體積體電路產業大致包含積體電路製造及積體電路封裝。積體電路製造是將積體電路製作在晶圓上，而積體電路封裝則可提供結構保護、電性傳遞及良好散熱給已製作有積體電路的裸晶片(晶圓於切割後的一部分)。
積體電路封裝通常是以單顆裸晶片作為加工對象，意即封裝單顆裸晶片是常見的作法。然而，在某些特殊需求下，必須將多顆裸晶片同時封裝在單一載板上。因此，如何排列這些裸晶片成為降低晶片封裝結構尺寸的關鍵。
本發明有關一種晶片封裝結構，用以封裝多個晶片。
本發明提出一種晶片封裝結構，其包括一載板及一晶片群組。晶片群組包括一對晶片，其為相同的積體電路晶片。這對晶片反向並排地配置在該載板上並電性連接至該載板。
基於上述，本發明將一對相同的晶片反向並排地配置在載板上，以提供一種多晶片的封裝方式。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1為本發明之一實施例之晶片封裝結構的立體圖。請參考圖1，本實施例之晶片封裝結構100a包括一載板110及一晶片群組120。在本實施例中，晶片群組120包括一對第一晶片121。這對第一晶片121為相同的積體電路晶片，例如具有相同的電性功能、外觀尺寸及線路圖案的積體電路晶片。這對第一晶片121反向並排地配置在載板110上並電性連接至載板110。這對第一晶片121之一旋轉180度且與另一第一晶片121靠攏，使得這對第一晶片121的長度方向均平行於X軸。
請再參考圖1，為了容易表現出這對第一晶片121是相同的晶片且反向並排地配置在載板110上，在這對第一晶片121上加上了字母”A”。依照字母”A”的正反方向，這對第一晶片121包括位於圖1右側的一第一正向晶片121a及位於圖1左側的一第一反向晶片121b。
在本實施例中，這對第一晶片121可為相同功能的晶片，例如記憶體晶片。此外，這對第一晶片121以導線接合(wire bonding)方式電性連接至載板110。具體而言，這對第一晶片121藉由多條導線180來電性連接至載板110，並藉由封膠182來包覆這些導線180。進一步說，這些導線180包括多條第一導線180a及多條第二導線180b。這些第一導線180a電性連接第一正向晶片121a與載板110，而這些第二導線180b電性連接第一反向晶片121b與載板110。這些第一導線180a在載板110上的投影位於載板110的一第一側110a，而這些第二導線180b在載板110上的投影位於載板110與第一側110a相對的一第二側110b。這些第一導線180a與這些第二導線180b可傳遞相同傳輸協定的訊號。
此外，本發明透過這對第一晶片121(即第一正向晶片121a及第一反向晶片121b)的反向並排，用於電性連接導線180(如：訊號導線)之具有相同功能的接墊112(如：訊號接墊)將會分佈載板110的不同側。如此一來，可以更有效地利用載板110上的空間。此外，本發明的導線180的長度較短，故可解決訊號延遲、耦合效應及電力消耗等問題。
圖2為本發明另一實施例之晶片封裝結構的立體圖。請參考圖2，相較於圖1的實施例，本實施例之晶片封裝結構100b的晶片群組120更包括一對第二晶片122。這對第二晶片122與這對第一晶片121均為相同的積體電路晶片。這對第二晶片122反向並排地配置在這對第一晶片121上並電性連接至載板110。這對第一晶片121之一的長度方向(平行X軸)與這對第二晶片122之一的長度方向(平行Y軸)兩者在載板110上的投影不相互平行。在一實施例中，這對第一晶片121之一的長度方向(平行X軸)與這對第二晶片122之一的長度方向(平行Y軸)兩者在載板110上的投影亦可不相互平行，且相互垂直。
請再參考圖2，同樣地，為了容易表現出這對第二晶片122是相同的晶片且反向並排地配置在這對第一晶片121上，在這對第二晶片122上亦加上了字母”A”。依照字母”A”的正反方向，這對第二晶片122包括位於圖2上側的一第二正向晶片122a及位於圖2下側的一第二反向晶片122b。
在本實施例中，這對第一晶片121及這對第二晶片122可為相同功能的晶片，例如記憶體晶片。同樣地，這對第二晶片122也以導線接合方式電性連接至載板110。具體而言，這對第二晶片122亦藉由多條導線180來電性連接至載板110，並藉由封膠182來包覆這些導線180。
進一步說，這些導線180還包括多條第三導線180c及多條第四導線180d。這些第三導線180c電性連接第二正向晶片122a與載板110，而這些第四導線180d電性連接第二反向晶片122b與載板110。這些第三導線180c在載板110上的投影位於載板110的一第三側110c，而這些第四導線180d在載板110上的投影位於載板110的一第四側110d。第一側110a與第二側110b相對，第三側110c與第一側110a的一側相鄰，且第四側110d與第一側110a的另一側相鄰。這些第一導線180a、這些第二導線180b、這些第三導線180c與這些第四導線180d可傳遞相同傳輸協定的訊號。
此外，本發明透過這對第一晶片121(即第一正向晶片121a及第一反向晶片121b)與這對第二晶片122(即第二正向晶片122a及第二反向晶片122b)的反向並排，且這對第一晶片121與這對第二晶片122以不相互平行堆疊，用於電性連接導線180(如：訊號導線)之具有相同功能的接墊112(如：訊號接墊)將會分佈載板110的不同側。如此一來，可以更有效地利用載板110上的空間。此外，本發明的設計可縮短導線180的長度，故可解決訊號延遲、耦合效應及電力消耗等問題。
圖3A及圖3B分別為本發明另一實施例之晶片封裝結構的立體圖及俯視圖。請參考圖3A及圖3B，相較於圖2的實施例，本實施例之晶片封裝結構100c的晶片群組120更包括一頂部晶片130。頂部晶片130配置在晶片群組120上，並電性連接至晶片群組120。具體而言，頂部晶片130配置在晶片群組120的這對第二晶片122上，並電性連接至晶片群組120的這對第一晶片121及這對第二晶片122。此外，頂部晶片130的部分接點更可經由導線直接電性連接至載板110。
在本實施例中，這對第一晶片121及這對第二晶片122可為相同功能的晶片，例如記憶體晶片，且頂部晶片130可為控制晶片。此外，頂部晶片130可以導線接合方式電性連接至這對第一晶片121及這對第二晶片122。具體而言，頂部晶片130藉由多條導線181a、多條導線181b、多條導線181c、多條導線181d來電性連接至這對第一晶片121及這對第二晶片122。此外，本發明透過這對第一晶片121與這對第二晶片122中的二個晶片的反向並排，且這對第一晶片121與這對第二晶片122以不相互平行堆疊，用於電性連接導線181a～181d(如：訊號導線)之具有相同功能的接墊112(如：訊號接墊)將會分佈頂部晶片130的不同側。如此一來，可以更有效地利用頂部晶片130上的空間。此外，本發明的設計可縮短導線181a～181d的長度，故可解決訊號延遲、耦合效應及電力消耗等問題。
圖4分別為本發明另一實施例之晶片封裝結構的俯視圖。請參考圖4，相較於圖3B的實施例，本實施例之晶片封裝結構100d的頂部晶片130的長度方向與這對第一晶片121的長度方向(平行X軸)兩者在載板110上的投影相互傾斜。換句話說，頂部晶片130的長度方向與這對第一晶片121的長度方向在載板110上的投影兩者不相互平行且不相互垂直。
在本實施例中，相似於圖3B的實施例，圖4的頂部晶片130亦以導線接合方式電性連接至這對第一晶片121及這對第二晶片122。值得注意的是，當採用導線接合方式將頂部晶片130與這對第一晶片121及這對第二晶片122時，藉由反向並排的配置除可薄化封裝厚度及縮小封裝成品尺寸以外，更可調整這些導線181a～181d的長度，以解決訊號延遲、耦合效應及電力消耗等問題。特別注意的是，本實施例設計可使頂部晶片130連接至這對第一晶片121及這對第二晶片122的佈線呈對稱配置，可減少佈線配置對其傳遞的訊號產生差異。在一般製造工藝的控制下，可以使其傳遞訊號的差異控制在最小範圍。
依照圖3B及圖4的實施例，更可藉由改變頂部晶片130在載板110上方的位置及角度，將位於頂部晶片130的兩相對側的該些相對應的導線181a～181d的長度調整至相同，以符合電性效能上的考量。舉例而言，在頂部晶片130的相對角落(例如左上角落及右下角落)的導線181a～181d具有相同的長度。
圖5為本發明另一實施例之晶片封裝結構的立體圖。請參考圖5，相較於圖1的實施例，本實施例之晶片封裝結構100e的晶片群組120更包括多對第一晶片121，其堆疊成兩疊在載板110上，同一疊且相鄰的這些第一晶片121相互電性連接，且鄰近載板110的這對第一晶片121電性連接至載板110。在本實施例中，同一疊且相鄰的這些第一晶片121以導線接合方式相互電性連接，且鄰近載板110的這對第一晶片121以導線接合方式電性連接至載板110。
具體而言，這些對第一晶片121包括一第一正向晶片121a、一第一反向晶片121b、另一第一正向晶片121c及另一第一反向晶片121d，其中第一正向晶片121a與第一反向晶片121b相鄰，第一正向晶片121c及第一反向晶片121d相鄰，第一正向晶片121a及121c相疊，且第一反向晶片121b及121d相疊。此外，第一正向晶片121a及121c以多條導線183a互連，而第一反向晶片121b及121d以多條導線183b互連。
圖6為本發明另一實施例之晶片封裝結構的立體圖。請參考圖6，相較於圖5的實施例，本實施例之晶片封裝結構100f的晶片群組120更包括多對第二晶片122，其堆疊成兩疊在這些對第一晶片121上，且同一疊且相鄰的這些第二晶片122相互電性連接。在本實施例中，同一疊且相鄰的這些第二晶片121以導線接合方式相互電性連接。
具體而言，這些對第二晶片122包括一第二正向晶片122a、一第二反向晶片122b、另一第二正向晶片122c及另一第二反向晶片122d，其中第二正向晶片122a與第二反向晶片122b相鄰，第二正向晶片122c及第二反向晶片122d相鄰，第二正向晶片122a及122c相疊，且第二反向晶片122b及122d相疊。此外，第二正向晶片122a及122c以多條導線183c互連，而第二反向晶片122b及122d以多條導線183d互連。
圖7為本發明另一實施例之晶片封裝結構的立體圖。請參考圖7，相較於圖6的實施例，本實施例之晶片封裝結構100g更包括一頂部晶片130。頂部晶片130配置在晶片群組120上，並電性連接至晶片群組120。具體而言，頂部晶片130配置在這對第二晶片122上，並電性連接至這對第一晶片121及這對第二晶片122。在本實施例中，頂部晶片130可以導線接合方式電性連接至這對第一晶片121及這對第二晶片122。此外，頂部晶片130的部分接點更可經由導線直接電性連接至載板110。
值得注意的是，當採用導線接合方式將頂部晶片130與這對第一晶片121及這對第二晶片122時，藉由反向並排的配置除可薄化封裝厚度以外，更可調整這些導線181a～181d的長度，以解決訊號延遲、耦合效應及電力消耗等問題。除此之外，更可藉由改變頂部晶片130在載板110上方的位置及角度，將位於頂部晶片130的兩相對側的該些相對應的導線181a～181d的長度調整至相同，以符合電性效能上的考量。
圖8為本發明另一實施例之晶片封裝結構的立體圖。請參考圖8，相較於圖1的實施例，本實施例之晶片封裝結構100p的晶片群組120的這對第一晶片121以覆晶接合(flip chip bonding)方式電性連接至載板110。具體而言，這對第一晶片121可藉由多個導電凸塊190來電性連接至載板110，同時藉由這些導電凸塊190將這對第一晶片121配置在載板110上。此外，在一實施例中，這對第一晶片121為相同的積體電路晶片，例如具有相同的電性功能、外觀尺寸及線路圖案的積體電路晶片，如：記憶體晶片。特別是，這對第一晶片121以反向並排地配置在載板110上並電性連接至載板110。因此，本發明透過這對第一晶片121中的二個晶片的反向並排，用於電性連接晶片121與載板110之具有相同功能的導電凸塊190(如：訊號導電凸塊)將會分佈載板110的不同側，如此一來，可以更有效地利用載板110上的空間。
請再參考圖8，同樣地，為了容易表現出這對第一晶片121是相同的晶片且反向並排地配置在載板110上，在這對第一晶片121上加上了字母”A”。依照字母”A”的正反方向，這對第一晶片121包括位於圖8右側的一第一正向晶片121a及位於圖8左側的一第一反向晶片121b。此外，在本實施例中，這些導電凸塊190包括多個第一導電凸塊190a及多個第二導電凸塊190b。這些第一導電凸塊190a電性連接第一正向晶片121a與載板110，而這些第二導電凸塊190b電性連接第一反向晶片121b與載板110。這些第一導電凸塊190a在載板110上的投影位於載板110的一第一側110a，而這些第二導電凸塊190b在載板110上的投影位於載板110與第一側110a相對的一第二側110b。這些第一導電凸塊190a與這些第二導電凸塊190b可傳遞相同傳輸協定的訊號。
圖9為本發明另一實施例之晶片封裝結構的立體圖。請參考圖9，相較於圖8的實施例，本實施例之晶片封裝結構100q的晶片群組120更包括一對第二晶片122。這對第二晶片122亦以覆晶接合方式電性連接至這對第一晶片121，並間接地經由這對第一晶片121而電性連接至載板110。在一實施例中，這對第二晶片122透過覆晶接合方式電性連接這對第一晶片121之後，更藉由在這對第一晶片121實施直通矽晶穿孔(Through-Silicon Via，TSV)技術，而電性連接至載板110。
請再參考圖9，同樣地，為了容易表現出這對第二晶片122是相同的晶片且反向並排地配置在這對第一晶片121上，在這對第二晶片122上亦加上了字母”A”。依照字母”A”的正反方向，這對第二晶片122包括位於圖2上側的一第二正向晶片122a及位於圖2下側的一第二反向晶片122b。
在本實施例中，這些導電凸塊190還包括多個第三導電凸塊190c及多個第四導電凸塊190d。這些第三導電凸塊190c電性連接第二正向晶片122a與載板110，而這些第四導電凸塊190d電性連接第二反向晶片122b與載板110。這些第三導電凸塊190c在載板110上的投影位於載板110的一第三側110c，而這些第四導電凸塊190d在載板110上的投影位於載板110的一第四側110d。第一側110a與第二側110b相對，第三側110c與第一側110a的一側相鄰，且第四側110d與第一側110a的另一側相鄰。這些第一導電凸塊190a、這些第二導電凸塊190b、這些第三導電凸塊190c與這些第四導電凸塊190d可傳遞相同傳輸協定的訊號。
圖10為本發明另一實施例之晶片封裝結構的立體圖。請參考圖10，相較於圖9的實施例，本實施例之晶片封裝結構100r的晶片群組120更包括一頂部晶片130。頂部晶片130配置在晶片群組120上，並電性連接至載板110。在本實施例中，頂部晶片130可以導線191直接電性連接至載板110。
圖11為本發明另一實施例之晶片封裝結構的立體圖。請參考圖11，相較於圖10的實施例，本實施例之晶片封裝結構100s的頂部晶片130亦配置在相鄰的這對第二晶片122上，並電性連接至這對第二晶片122。在本實施例中，頂部晶片130可以覆晶接合方式電性連接至這對第二晶片122，並間接地經由這對第二晶片122及這對第一晶片121而電性連接至載板110。在一實施例中，頂部晶片130透過覆晶接合方式電性連接這對這對第二晶片122之後，更藉由在這對第二晶片122及這對第一晶片121實施TSV，而電性連接至載板110。
圖12為本發明另一實施例之晶片封裝結構的立體圖。請參考圖12，相較於圖8的實施例，本實施例之晶片封裝結構100t更包括多對第一晶片121，其堆疊成兩疊在載板110上，同一疊且相鄰的這些第一晶片121相互電性連接，且鄰近載板110的這對第一晶片121電性連接至載板110。在本實施例中，同一疊且相鄰的這些第一晶片121藉由導電凸塊190以覆晶接合方式相互電性連接，且鄰近載板110的這對第一晶片121亦可藉由導電凸塊190以覆晶接合方式電性連接至載板110。
在本實施例中，這些對第一晶片121包括一第一正向晶片121a、一第一反向晶片121b、一第一正向晶片121c、一第一反向晶片121d、一第一正向晶片121e及一第一反向晶片121f。第一正向晶片121a與第一反向晶片121b相鄰，第一正向晶片121c及第一反向晶片121d相鄰，且一第一正向晶片121e及一第一反向晶片121f。同時，第一正向晶片121a、121c及121e相疊，第一反向晶片121b、121d及121f相疊。
在一實施例中，上述之「利用導電凸塊以覆晶接合方式」亦可以「利用銅柱(Copper Pillar)以覆晶接合方式」取代，且可在第一正向晶片121a、第一反向晶片121b、第一正向晶片121c及第一反向晶片121d中實施TSV技術，已完成上下晶片之電性連接。
圖13為本發明另一實施例之晶片封裝結構的立體圖。請參考圖13，相較於圖12的實施例，本實施例之晶片封裝結構100u的晶片群組120更包括多對第二晶片122，其堆疊成兩疊在這些對第一晶片121上，且同一疊且相鄰的這些第二晶片122相互電性連接。在本實施例中，同一疊且相鄰的這些第二晶片121藉由導電凸塊190以覆晶接合方式相互電性連接，且鄰近這對第一晶片121的這對第二晶片122亦可藉由導電凸塊以覆晶接合方式電性連接至這對第一晶片121。
在本實施例中，這些對第二晶片122包括一第二正向晶片122a、一第二反向晶片122b、一第二正向晶片122c、一第二反向晶片122d、一第二正向晶片122e及一第二反向晶片122f。第二正向晶片122a與第二反向晶片122b相鄰，第二正向晶片122c及第二反向晶片122d相鄰，且一第二正向晶片122e及一第二反向晶片122f。同時，第二正向晶片122a、122c及122e相疊，第二反向晶片122b、122d及122f相疊。
在一實施例中，上述之「利用導電凸塊以覆晶接合方式」亦可以「利用銅柱(Copper Pillar)以覆晶接合方式」取代，且可在第一正向晶片121a、第一反向晶片121b、第一正向晶片121c、第一反向晶片121d、第二正向晶片122a、第二反向晶片122b、第二正向晶片122c、第二反向晶片122d中實施TSV技術，以完成上下晶片之電性連接。
對於圖1、2、5、6、8、9、12及13之在未加上頂部晶片130的這些實施例，也可參考圖3A、3B、4、7、10、11之有加上頂部晶片130的實施例加上頂部晶片，並可藉由導線接合或覆晶接合方式電性連接其下方的載板110或晶片群組120。
綜上所述，本發明將一對相同的第一晶片反向並排地配置在載板上，這有助於薄化整體封裝結構的厚度。此外，本發明更可將一對相同的第二晶片相對於這對第一晶片傾斜後反向並排地配置在這對第一晶片上，這亦有助於薄化整體封裝結構的厚度，進一步縮小封裝成品尺寸。
再者，本發明更可在這些晶片上配置一頂部晶片，且當頂部晶片以導線接合的方式，電性連接至這些第一及第二晶片時，可藉由這些晶片之反向並排的配置來調整導線的長度，以解決訊號延遲、耦合效應及電力消耗等問題。除此之外，透過本發明之這些第一及第二晶片的配置方式，可以更有效地利用頂部晶片或是載板上的空間。經由將頂部晶片與這些第一及第二晶片對稱配置，更可以使其間傳遞的訊號差異減少至最低，降低或避免佈線設計的差異對訊號傳遞的影響。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100(a～g、p～u)．．．晶片封裝結構
110．．．載板
110a．．．第一側
110b．．．第二側
110c．．．第三側
110d．．．第四側
112．．．接墊
120．．．晶片群組
121．．．第一晶片
121a、121c、121e．．．第一正向晶片
121b、121d、121f．．．第一反向晶片
122．．．第二晶片
122a、122c、122e．．．第二正向晶片
122b、122d、122f．．．第二反向晶片
130．．．頂部晶片
180．．．導線
180a．．．第一導線
180b．．．第二導線
180c．．．第三導線
180d．．．第四導線
181a．．．導線
181b．．．導線
181c．．．導線
181d．．．導線
182．．．封膠
183a．．．導線
183b．．．導線
183c．．．導線
183d．．．導線
190．．．導電凸塊
190a．．．第一導電凸塊
190b．．．第二導電凸塊
190c．．．第三導電凸塊
190d．．．第四導電凸塊
191．．．導線
圖1為本發明之一實施例之晶片封裝結構的立體圖。
圖2為本發明另一實施例之晶片封裝結構的立體圖。
圖3A及圖3B分別為本發明另一實施例之晶片封裝結構的立體圖及俯視圖。
圖4為本發明另一實施例之晶片封裝結構的俯視圖。
圖5為本發明另一實施例之晶片封裝結構的立體圖。
圖6為本發明另一實施例之晶片封裝結構的立體圖。
圖7為本發明另一實施例之晶片封裝結構的立體圖。
圖8為本發明另一實施例之晶片封裝結構的立體圖。
圖9為本發明另一實施例之晶片封裝結構的立體圖。
圖10為本發明另一實施例之晶片封裝結構的立體圖。
圖11為本發明另一實施例之晶片封裝結構的立體圖。
圖12為本發明另一實施例之晶片封裝結構的立體圖。
圖13為本發明另一實施例之晶片封裝結構的立體圖。
100c．．．晶片封裝結構
110．．．載板
110a．．．第一側
110b．．．第二側
110c．．．第三側
110d．．．第四側
120．．．晶片群組
121．．．第一晶片
121a．．．第一正向晶片
121b．．．第一反向晶片
122．．．第二晶片
122a．．．第二正向晶片
122b．．．第二反向晶片
130．．．頂部晶片
180．．．導線
180a．．．第一導線
180b．．．第二導線
180c．．．第三導線
180d．．．第四導線
181a、181b、181c、181d．．．導線
182．．．封膠

Claims (15)

  1. 一種晶片封裝結構，包括：一載板；以及一晶片群組，包括：一對第一晶片，配置在該載板上並電性連接至該載板，其中該對第一晶片包括一第一正向晶片與一第一反向晶片，該第一正向晶片以及該第一反向晶片為兩相同的積體電路晶片且並排於一平面上，各個該相同的積體電路晶片與所對應的該相同的積體電路晶片的同一側具有多個焊墊，其中一該相同的積體電路晶片相對於另一該相同的積體電路晶片於該平面上旋轉180度，使其中一該相同的積體電路晶片的該焊墊與另一該相同的積體電路晶片的該焊墊分別設置為並排且位於該平面的兩相對側上，其中一該相同的積體電路晶片的該焊墊位於該相同的積體電路晶片的一端，該相同的積體電路晶片的該端位於該相同的積體電路晶片的另一端的對側，該相同的積體電路晶片的該另一端與另一該相同的積體電路晶片的一端並排，且另一該相同的積體電路晶片的該焊墊位於另一該相同的積體電路晶片的該端，另一該相同的積體電路晶片的該端位於另一該相同的積體電路晶片的另一端的對側，另一該相同的積體電路晶片的該另一端與該相同的積體電路晶片的該端並排。
  2. 如申請專利範圍第1項所述之晶片封裝結構，其中 該對第一晶片包括一第一正向晶片與一第一反向晶片，且該晶片封裝結構更包括：多數條第一導線，用於電性連接該第一正向晶片與該載板，並且該些第一導線在該載板上的投影位於該載板的第一側；以及多數條第二導線，用於電性連接該第一反向晶片與該載板，並且該些第二導線在該載板上的投影位於該載板的第二側，其中該些第一導線與該些第二導線用以傳遞相同的訊號，且該第一側與該第二側相對。
  3. 如申請專利範圍第1項所述之晶片封裝結構，其中該對第一晶片是具有相同功能的晶片。
  4. 如申請專利範圍第1項所述之晶片封裝結構，其中該晶片群組包括：多個該對第一晶片，堆疊成兩疊在該載板上，其中同一疊且相鄰的該些第一晶片相互電性連接，且鄰近該載板的該對第一晶片電性連接至該載板。
  5. 如申請專利範圍第4項所述之晶片封裝結構，其中同一疊且相鄰的該些第一晶片以導線接合方式相互電性連接，且鄰近該載板的該對第一晶片以導線接合方式電性連接至該載板。
  6. 如申請專利範圍第1項所述之晶片封裝結構，其中該晶片群組更包括：一對第二晶片，與該對第一晶片為相同的積體電路晶片，該對第二晶片反向並排地配置在該對第一晶片上並電 性連接至該載板，且該對第一晶片之一的長度方向與該對第二晶片之一的長度方向兩者在該載板上的投影不相互平行。
  7. 如申請專利範圍第6項所述之晶片封裝結構，其中該對第一晶片之一的長度方向與該對第二晶片之一的長度方向兩者在該載板上的投影相互垂直。
  8. 如申請專利範圍第6項所述之晶片封裝結構，其中該對第一晶片包括一第一正向晶片與一第一反向晶片，該對第二晶片包括一第二正向晶片與一第二反向晶片，且該晶片封裝結構更包括：多數條第一導線，用於電性連接該第一正向晶片與該載板，並且該些第一導線在該載板上的投影位於該載板的第一側；以及多數條第二導線，用於電性連接該第一反向晶片與該載板，並且該些第二導線在該載板上的投影位於該載板的第二側；多數條第三導線，用於電性連接該第二正向晶片與該載板，並且該些第三導線在該載板上的投影位於該載板的第三側；多數條第四導線，用於電性連接該第二反向晶片與該載板，並且該些第四導線在該載板上的投影位於該載板的第四側，其中該些第一導線、該些第二導線、該些第三導線、該些第四導線用以傳遞相同的訊號，且該第一側與該第二側相對，該第三側與該第一側的一側相鄰、該第四側 與該第一側的另一側相鄰。
  9. 如申請專利範圍第6項所述之晶片封裝結構，其中該對第一晶片及該對第二晶片是相同的記憶體晶片。
  10. 如申請專利範圍第1項所述之晶片封裝結構，其中該晶片群組更包括：多個該對第二晶片，堆疊成兩疊在該對第一晶片上，且同一疊且相鄰的該些第二晶片相互電性連接。
  11. 如申請專利範圍第10項所述之晶片封裝結構，其中同一疊且相鄰的該些第二晶片以導線接合方式相互電性連接。
  12. 如申請專利範圍第1項所述之晶片封裝結構，更包括：一頂部晶片，配置在該晶片群組上，並電性連接至該晶片群組或該載板。
  13. 如申請專利範圍第12項所述之晶片封裝結構，其中該頂部晶片以導線接合方式電性連接至該晶片群組或該載板。
  14. 如申請專利範圍第13項所述之晶片封裝結構，其中該頂部晶片的兩相對側的該些相對應的導線的長度相同。
  15. 如申請專利範圍第12項所述之晶片封裝結構，其中該晶片群組的所有晶片是相同的記憶體晶片，且該頂部晶片為控制晶片。
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