TW202101726A - 具有中介件的堆疊半導體封裝件 - Google Patents
具有中介件的堆疊半導體封裝件 Download PDFInfo
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- TW202101726A TW202101726A TW108137487A TW108137487A TW202101726A TW 202101726 A TW202101726 A TW 202101726A TW 108137487 A TW108137487 A TW 108137487A TW 108137487 A TW108137487 A TW 108137487A TW 202101726 A TW202101726 A TW 202101726A
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- pad
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- interposer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 230000005540 biological transmission Effects 0.000 claims description 19
- 238000004806 packaging method and process Methods 0.000 claims description 17
- 235000012431 wafers Nutrition 0.000 description 195
- 239000010410 layer Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
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- 238000005520 cutting process Methods 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
根據本揭示的一態樣的半導體封裝件包括:封裝基板;依序堆疊在封裝基板上的下晶片、中介件和上晶片;以及電連接封裝基板和中介件的接合導線。中介件包括:在中介件的下表面上電連接至下晶片的下晶片連接墊;在中介件的上表面上分別電連接至上晶片的第一上晶片連接墊和第二上晶片連接墊;設置在中介件的上表面上並接合至接合導線的導線接合墊;設置在中介件的上表面上並且將第二上晶片連接墊電連接至導線接合墊的第一重分佈線;以及電連接下晶片連接墊和第一上晶片連接墊的通孔電極。
Description
本揭示總體上涉及半導體封裝件,並且更具體地,涉及包括中介件(interposer)的堆疊半導體封裝件。相關申請的交叉引用
本申請案主張於2019年6月21日提交的韓國專利申請案第10-2019-0074338號的優先權,其全部內容通過引用合併於此。
通常,半導體封裝件可以被配置為包括基板和安裝在基板上的半導體晶片。半導體晶片可以通過諸如凸塊或導線之類的連接構件電連接至基板。
近來,根據對具有高性能和高整合度的半導體封裝件的需求,已經提出了在基板上堆疊多個半導體晶片的各種方式。例如,已經提出了使用過矽通孔(TSV)電連接堆疊在基板上的多個半導體晶片的技術。
根據本揭示的實施方式,半導體封裝件可以包括:封裝基板;依序堆疊在封裝基板上的下晶片、中介件和上晶片;並且包括電連接封裝基板和中介件的接合導線。中介件包括設置在中介件的下表面上的下晶片連接墊,其中,下晶片連接墊電連接至下晶片。中介件還包括設置在中介件的上表面上的第一上晶片連接墊和第二上晶片連接墊,其中,第一上晶片連接墊和第二上晶片連接墊電連接至上晶片。中介件還包括設置在中介件的上表面上並接合至接合導線的導線接合墊;設置在中介件的上表面上並將第二上晶片連接墊電連接至導線接合墊的第一重分佈線;以及將下晶片連接墊電連接至第一上晶片連接墊的通孔電極。
根據本揭示的另一實施方式,堆疊半導體封裝件可以包括:封裝基板;依序堆疊在封裝基板上的下晶片、中介件和上晶片;以及電連接封裝基板和中介件的接合導線。中介件包括:將下晶片電連接至上晶片的通孔電極;以及將上晶片電連接至接合導線的第一重分佈線。
本文使用的術語可以對應於考慮到它們在實施方式中的功能而選擇的詞,並且根據實施方式所屬領域的普通技術人員,可以將術語的含義解釋為不同。如果詳細定義了術語,則可以根據這些定義來解釋術語。除非另有定義,否則本文中使用的術語(包括技術術語和科學術語)具有與實施方式所屬領域的普通技術人員通常所理解的含義相同的含義。
將理解的是,儘管在本文中可以使用術語“第一”、“第二”、“第三”等來描述各種元件,但是這些元件不應受這些術語的限制。這些術語僅用於將一個元件與另一元件區分開,而不用於暗示元件的特定順序或數量。還應理解,當元件或層稱為在另一元件或層“上”、“上方”、“下”、“下方”或“外部”時,該元件或層可以直接接觸另一個元件或層,或者可以存在中間元件或層。應該以類似的方式來解釋用於描述元件或層之間的關係的其它詞語(例如,“在……之間”與“直接在……之間”或“相鄰”與“直接相鄰”)。
諸如“之下”、“下”、“低於”、“上方”、“高於”、“頂”、“底”等的空間相對術語可以用於描述元件和/或特徵與另一元件和/或特徵的關係,如例如附圖中示出的關係。將理解的是,除了附圖中繪出的方位之外,空間相對術語還旨在涵蓋裝置在使用和/或操作中的不同方位。例如,當附圖中的裝置被翻轉時,則被描述為在其它元件或特徵下或下方的元件將被定向在其它元件或特徵上方。可以以其它方式定向裝置(旋轉90度或其它方位),並據此解釋本文中使用的空間相對描述語。
本文描述的半導體封裝件可以包括諸如半導體晶片的電子裝置。可以通過使用晶粒切割製程將諸如晶圓之類的半導體基板分成多片來獲得半導體晶片。半導體晶片可以對應於記憶體晶片、邏輯晶片(包括特定應用積體電路(ASIC)晶片)或單晶片系統(SoC)。記憶體晶片可以包括整合在半導體基板上的動態隨機存取記憶體(DRAM)電路、靜態隨機存取記憶體(SRAM)電路、反及型快閃記憶體電路、反或型快閃記憶體電路、磁隨機存取記憶體(MRAM)電路、電阻式隨機存取記憶體(ReRAM)電路、鐵電隨機存取記憶體(FeRAM)電路或相變隨機存取記憶體(PcRAM)電路。邏輯晶片可以包括整合在半導體基板上的邏輯電路。半導體晶片根據它們在晶粒切割製程之後的形狀可以被稱為半導體晶粒。
半導體封裝件可以包括其上安裝有半導體晶片的封裝基板。封裝基板可以包括積體電路圖案的至少一層,並且在本說明書中可以稱為印刷電路板(PCB)。
作為實施方式,半導體封裝件可以包括安裝在封裝基板上的多個半導體晶片。在半導體封裝件中,多個半導體晶片中的任何一個可以被設置為主晶片,而其餘半導體晶片可以被設置為從晶片。然後,可以使用主晶片來控制從晶片的記憶體單元。主晶片可以直接與封裝基板交換信號,而從晶片可以通過主晶片與封裝基板交換信號。
半導體封裝件可用於諸如行動電話、與生物技術或醫療保健相關的電子系統、或可穿戴電子系統之類的各種通信系統中。
在整個說明書中,相同的附圖標記指代相同的元件。即使未參照一附圖提及或描述附圖標記,也可以參照另一附圖提及或描述該附圖標記。另外,即使附圖標記未在一附圖中示出,也可以參照另一附圖來提及或描述附圖標記。
圖1是例示根據本揭示的實施方式的半導體封裝件1的截面圖。
參照圖1,半導體封裝件1可以包括堆疊在封裝基板100上的下晶片200、中介件300和上晶片400。中介件300可以使用接合導線50a和50b電連接至封裝基板100。
下晶片200和上晶片400可以各自是包括積體電路的半導體晶片。上晶片400可以使用第一重分佈線340a和340b以及接合導線50a和50b電連接至封裝基板100。此外,下晶片200可以使用中介件300中的通孔電極360a和360b電連接至上晶片400。也就是說,上晶片400可以通過第一重分佈線340a和340b以及接合導線50a和50b與封裝基板100交換電信號,並且下晶片200可以通過上晶片400與封裝基板100交換電信號。
參照圖1,提供了封裝基板100。封裝基板100可以具有上表面100S1和與上表面100S1相對的下表面100S2。儘管圖1中未示出,但是封裝基板100可以包括積體電路圖案的至少一層。
用於與中介件300進行導線接合的連接墊110a和110b可以設置在封裝基板100的上表面100S1上。另外,用於與其它半導體封裝件或PCB的電連接的連接結構550可以設置在封裝基板100的下表面100S2上。連接結構550可以包括例如凸塊、焊料球等。
下晶片200可以設置在封裝基板100上。下晶片200可以具有上表面200S1和下表面200S2。第一下晶片墊210a和210b以及第二下晶片墊220a和220b可以設置在下晶片200的上表面200S1上。第一下晶片墊210a和210b中的每個可以通過第一凸塊520分別連接至中介件300的下晶片連接墊350a和350b。第二下晶片墊220a和220b可以在橫向方向(即,x方向)上與第一下晶片墊210a和210b間隔開設置並且可以不參與與中介件300的橫向連接。此外,非導電黏合層510可以設置在下晶片200的下表面200S2上,使得下晶片200可以接合至封裝基板100。
中介件300可以設置在下晶片200上方。中介件300可以具有上表面300S1和下表面300S2。電連接至下晶片200的下晶片連接墊350a和350b可以設置在中介件300的下表面300S2上。在實施方式中,下晶片連接墊350a和350b可以通過第一凸塊520分別連接至第一下晶片墊210a和210b。電連接至上晶片400的第一上晶片連接墊310a和310b以及第二上晶片連接墊320a和320b可以設置在中介件300的上表面300S1上。
中介件300可以包括在橫向方向(即,D1和D2方向)上從上晶片400的邊緣區域突出的至少一個區域。因此,作為示例,中介件300沿x方向的寬度可以大於上晶片400沿x方向的寬度。導線接合墊330a和330b可以設置在中介件300的在橫向方向上突出或延伸超出上晶片400的區域上。導線接合墊330a和330b可以通過接合導線50a和50b電連接至封裝基板100上的下晶片連接墊110a和110b。此外,用於將第二上晶片連接墊320a和320b連接至導線接合墊330a和330b的第一重分佈線340a和340b可以設置在中介件300的上表面300S1上。第二上晶片連接墊320a和320b電連接至上晶片400的第二上晶片墊420a和420b,使得上晶片400通過第一重分佈線340a和340b以及接合導線50a和50b電連接至封裝基板100。
中介件300可以包括用於將第一上晶片連接墊310a和310b分別電連接至下晶片連接墊350a和350b的通孔電極360a和360b。在實施方式中,如下面參照圖5所述,中介件300還可以包括設置在中介件300的上表面300S1和下表面300S2上的第二佈線層至第五佈線層371、372、381和382,以便將第一上晶片連接墊310a和310b以及下晶片連接墊350a和350b分別連接至通孔電極360a和360b。
上晶片400可以設置在中介件300上方。上晶片400可以具有上表面400S1和下表面400S2。第一上晶片墊410a和410b以及第二上晶片墊420a和420b可以設置在上晶片400的面向中介件300的上表面400S1上。第一上晶片墊410a和410b可以通過第二凸塊530分別連接至中介件300的第一上晶片連接墊310a和310b。第二上晶片墊420a和420b可以在橫向方向(即,x方向)上與第一上晶片墊410a和410b間隔開設置,並可以通過第三凸塊540分別連接至中介件300的第二上晶片連接墊320a和320b。在實施方式中,第一上晶片墊410a和410b中的每個可以具有與第二上晶片墊420a和420b基本上相同的尺寸。在實施方式中,第二凸塊530和第三凸塊540可以具有基本相同的尺寸。
在實施方式中,下晶片200和上晶片400中的每個可以是記憶體晶片。在實施方式中,下晶片200和上晶片400可以是具有相同結構的晶片。在實施方式中,上晶片400可以是主晶片,並且下晶片200可以是從晶片。上晶片400可以通過中介件300的第一重分佈線340a和340b以及接合導線50a和50b電連接至封裝基板100。下晶片200可以藉由通孔電極360a和360b通過上晶片400電連接至封裝基板100。因此,下晶片200可以共享上晶片400的輸入/輸出電路。
圖2和圖3是例示根據本揭示的實施方式的半導體晶片的平面圖。更具體地,圖2例示了圖1的下晶片200,並且圖3例示了圖1的上晶片400。圖4A、圖4B和圖4C是例示根據本揭示的實施方式的中介件的圖。更具體地,圖4A是例示圖1的中介件300的平面圖,圖4B是圖4A的部分“L”的局部放大圖,並且圖4C是圖4A的通孔佈置區域“C”的立體圖。
參照圖2,下晶片200可以具有沿x方向的短軸和沿y方向的長軸。另外,下晶片200可以具有平行於長軸的中心軸Cy-200。下晶片200可以在短軸方向上具有寬度W200,並且在長軸方向上具有長度L200。中心軸Cy-200可以延伸以使得下晶片200的寬度W200的一半在中心軸Cy-200的各側上。
第一下晶片墊210a和210b以及第二下晶片墊220a和220b可以沿長軸方向(即,y方向)佈置。第一下晶片墊210a和210b以及第二下晶片墊220a和220b可以設置為分別相對於中心軸Cy-200形成對稱對。在具體實施方式中,第一下晶片墊210a和210b可以設置為比第二下晶片墊220a和220b更靠近中心軸Cy-200。第一下晶片墊210a和210b可以相對於中心軸Cy-200分類為第一下晶片左墊210a和第一下晶片右墊210b。第二下晶片墊220a和220b可以相對於中心軸Cy-200分類為第二下晶片左墊220a和第二下晶片右墊220b。
如圖2所示,第一下晶片墊210a和210b中的每個的表面積可以與第二下晶片墊220a和220b中的每個的表面積基本相同。作為示例,第一下晶片墊210a和210b以及第二下晶片墊220a和220b可以具有相同的形狀和尺寸。這裡,第一下晶片墊210a和210b的列以及第二下晶片墊220a和220b的列可以在x方向上以相同的水平間隔S1佈置。如圖2所示,第二下晶片左墊220a、第一下晶片左墊210a、第一下晶片右墊210b和第二下晶片右墊220b可以以相同的水平間隔S1依序佈置。另外,第一下晶片墊210a和210b以及第二下晶片墊220a和220b可以在y方向上以相同的垂直間隔S2佈置。
參照圖1和圖2,第一下晶片墊210a和210b可以通過通孔電極360a和360b電連接至上晶片400。也就是說,第一下晶片墊210a和210b可以用作下晶片200的用於與上晶片400交換電信號的信號輸入/輸出墊。第一下晶片墊210a和210b可以以集中方式佈置在下晶片200的上表面200S1上的通孔電極佈置區A中。第二下晶片墊220a和220b可以沿中心軸Cy-200以相同的垂直間隔S2連續設置。此外,下晶片200的第二下晶片墊220a和220b可以不電連接至諸如中介件300和封裝基板100之類的其它結構。
參照圖3,上晶片400可具有沿x方向的短軸和沿y方向的長軸。另外,上晶片400可以具有與長軸平行的中心軸Cy-400。上晶片400可以在短軸方向上具有寬度W400,並且可以在長軸方向上具有長度L400。中心軸Cy-400可以延伸以使得上晶片400的寬度W400的一半在中心軸Cy-400的各側上。
第一上晶片墊410a和410b以及第二上晶片墊420a和420b可以沿長軸方向(即,y方向)佈置在上晶片400的上表面400S1上。第一上晶片墊410a和410b以及第二上晶片墊420a和420b可以佈置為分別相對於中心軸Cy-400形成對稱對。在具體示例中,第一上晶片墊410a和410b可以設置為比第二上晶片墊420a和420b更靠近中心軸Cy-400。第一上晶片墊410a和410b可以相對於中心軸Cy-400分類為第一上晶片左墊410a和第一上晶片右墊410b。第二上晶片墊420a和420b可以相對於中心軸Cy-400分類為第二上晶片左墊420a和第二上晶片右墊420b。
如圖3所示,第一上晶片墊410a和410b中的每個的表面積可以與第二上晶片墊420a和420b中的每個的表面積基本相同。作為示例,第一上晶片墊410a和410b以及第二上晶片墊420a和420b可以具有相同的形狀和尺寸。這裡,第一上晶片墊410a和410b的列以及第二上晶片墊420a和420b的列可以在x方向上以相同的水平間隔S1佈置。如圖3所示,第二上晶片左墊420a、第一上晶片左墊410a、第一上晶片右墊410b和第二上晶片右墊420b可以以相同的水平間隔S1依序地佈置。另外,第一上晶片墊410a和410b以及第二上晶片墊420a和420b可以在y方向上以相同的垂直間隔S2佈置。
參照圖1和圖3,第一上晶片墊410a和410b可以通過通孔電極360a和360b電連接至下晶片200。也就是說,第一上晶片墊410a和410b可以用作上晶片400的用於與下晶片200交換電信號的信號輸入/輸出墊。第一上晶片墊410a和410b可以以集中方式佈置在上晶片400的上表面400S1上的通孔電極佈置區B中。第二上晶片墊420a和420b可以沿中心軸Cy-400以相同的垂直間隔S2連續地設置。上晶片400的第二上晶片墊420a和420b可以電連接至中介件300的第二上晶片連接墊320a和320b。也就是說,第二上晶片墊420a和420b可以用作上晶片400的用於與中介件300和封裝基板100交換電信號的信號輸入/輸出墊。
參照圖4A至圖4C,中介件300可以具有沿x方向的短軸和沿y方向的長軸。另外,中介件300可以具有平行於長軸的中心軸Cy-300。中介件300可以在短軸方向上具有寬度W300,並且可以在長軸方向上具有長度L300。中心軸Cy-300可以延伸以使得中介件300的寬度W300的一半在中心軸Cy-300的各側上。
第一上晶片連接墊310a和310b、第二上晶片連接墊320a和320b以及導線接合墊330a和330b可以沿長軸方向(即,y方向)佈置在中介件300的上表面300S1上。在實施方式中,第一上晶片連接墊310a和310b、第二上晶片連接墊320a和320b以及導線接合墊330a和330b可以設置為分別相對於中心軸Cy-300形成對稱對。在具體示例中,第一上晶片連接墊310a和310b、第二上晶片連接墊320a和320b以及導線接合墊330a和330b可以在x方向上從中介件300的中心軸Cy-300開始依序地設置。如圖所示,第一上晶片連接墊310a和310b、第二上晶片連接墊320a和320b以及導線接合墊330a和330b中的每個的表面積可以基本相同。作為示例,第一上晶片連接墊310a和310b、第二上晶片連接墊320a和320b以及導線接合墊330a和330b可以具有相同的形狀和尺寸。
此外,第一上晶片連接墊310a和310b可以被分類為相對於中心軸Cy-300彼此對稱的第一上左墊310a和第一上右墊310b。這裡,連接至第一上左墊310a的第二重分佈線371和連接至第一上右墊310b的第三重分佈線372可以沿y方向設置在中介件300的上表面300S1上。如以下參照圖4C至圖5所描述的,第二重分佈線371可以將第一上左墊310a連接至第一通孔電極360a,並且第三重分佈線372可以將第一上右墊310b連接至第二通孔電極360b。導線接合墊330a和330b可以被分類為相對於中心軸Cy-300彼此對稱的左導線接合墊330a和右導線接合墊330b。
此外,第一上晶片連接墊310a和310b可以通過第二凸塊530分別連接至第一上晶片墊410a和410b。
下晶片連接墊350a和350b可以設置在中介件300的下表面300S2上。下晶片連接墊350a和350b可以通過第一凸塊520分別連接至下晶片200的第一下晶片墊210a和210b。此外,下晶片連接墊350a和350b可以分類為相對於中心軸Cy-300彼此對稱的下左墊350a和下右墊350b。這裡,連接至下左墊350a的第五重分佈線382和連接至下右墊350b的第四重分佈線381可以設置在中介件300的下表面300S2上。
下左墊350a可以在中介件300的下表面300S2上通過第五重分佈線382連接至第二通孔電極360b。另外,下右墊350b可以通過第四重佈線381連接至第一通孔電極360a。在實施方式中,下左墊350a可以直接設置在上左墊310a的下方以面對上左墊310a。另外,下右墊350b可以直接設置在上右墊310b的下方以面對上右墊310b。換句話說,下左墊350a和上左墊310a可以設置為在垂直方向上彼此交疊,並且下右墊350b和上右墊310b可以設置為在垂直方向上彼此交疊。
參照圖1和圖4A,第一重分佈線340a和340b可以設置在中介件300的上表面300S1上。第一重分佈線340a和340b可以成對設置,以相對於中心軸Cy-300對稱。作為示例,第一重分佈線340a和340b可以相對於中心軸Cy-300分類為第一左重分佈線340a和第一右重分佈線340b。第一重分佈線340a和340b可以將第二上晶片連接墊320a和320b分別連接至導線接合墊330a和330b。更具體地,第一重分佈線340a和340b可以設置在第二上晶片連接墊320a和320b與導線接合墊330a和330b之間,同時在短軸方向(即,x方向)上延伸。
圖5是例示根據本揭示的實施方式的在半導體晶片與封裝基板之間交換電信號的方法的示意圖。在圖5,使用上面參照圖1至圖4C描述的半導體封裝件1的下晶片200、中介件300和上晶片400的構造來例示交換電信號的方法。為了便於說明,在圖5中未示出封裝基板100。
參照圖5,上晶片400和下晶片200之間的電信號交換可以如下進行。作為示例,從上晶片400的第一上晶片左墊410a輸出的電信號可以通過第二凸塊530,中介件300的第一上左墊310a、第二重分佈線371、第一通孔電極360a、第三重分佈線381和下右墊350b,以及第一凸塊520到達第一下晶片右墊210b。這樣,半導體封裝件1可以具有從上晶片400至下晶片200的電信號路徑。另外,半導體封裝件1可以具有在相反方向上從下晶片200至上晶片400的電信號路徑。上晶片400和下晶片200之間的電信號路徑在圖5中示為“F1”。
作為另一示例,從上晶片400的第一上晶片右墊410b輸出的電信號也可以通過第二凸塊530,中介件300的第一上右墊310b、第三重分佈線372、第二通孔電極360b、第四重分佈線382和下左墊350a,以及第一凸塊520到達第一下晶片左墊210a。這樣,半導體封裝件1可以具有從上晶片400至下晶片200的電信號路徑。另外,半導體封裝件1可以具有在相反方向上從下晶片200至上晶片400的電信號路徑。
參照圖5和圖1,上晶片400和封裝基板100之間的電信號交換可以如下進行。作為示例,從上晶片400的第二上晶片左墊420a輸出的電信號可以通過第三凸塊540、中介件300的第二上左墊320a和第一左重分佈線340a到達左導線接合墊330a。到達左導線接合墊330a的電信號可以通過接合導線50a和50b中的左佈線50a傳輸至封裝基板100。這樣,半導體封裝件1可以具有從上晶片400至封裝基板100的電信號路徑。電信號可以在相反方向上從封裝基板100傳輸至上晶片400。上晶片400和封裝基板100之間的電信號路徑在圖5中示為“F2”。
作為另一示例,從第二上晶片右墊420b輸出的電信號也可以通過第三凸塊540、中介件300的第二上右墊320b和第一右重分佈線340b到達右導線接合墊330b。到達右導線接合墊330b的電信號可以通過接合導線50a和50b中的右佈線50b傳輸至封裝基板100。
如上所述,上晶片400可以不通過導線接合直接連接至封裝基板100。替代地,在使用凸塊將上晶片400連接至中介件300之後,上晶片400可以電連接至設置在中介件300上的導線接合墊340a和340b。因此,上晶片400可以通過接合至導線接合墊340a和340b的接合導線50a和50b電連接至封裝基板100。
另外,下晶片200可以不直接連接至封裝基板100,而是可以經由上晶片400電連接至封裝基板100。也就是說,下晶片200可以不直接具有用於與封裝基板100導線接合的導線接合墊。下晶片200可以使用中介件300的通孔電極360a和360b連接至上晶片400,然後使用上晶片400的內部佈線電連接至第二上晶片墊420a和420b。也就是說,下晶片200可以共享作為上晶片400的輸入/輸出墊的第二上晶片墊420a和420b,從而下晶片200可以使用與上晶片400的電信號路徑相同的路徑與封裝基板100交換電信號。
圖6是例示根據本揭示的實施方式的半導體封裝件的內部電路構造的圖。圖6可以是示意性地例示以上參照圖1描述的半導體封裝件1的內部電路的圖。
參照圖6,封裝基板100可以包括設置在上表面100S1上並且通過接合導線50a和50b連接的連接墊110a和110b。另外,封裝基板100可以包括連接結構550,連接結構550設置在下表面100S2上並且設置為用於與另一半導體封裝件或印刷電路板的電連接。
下晶片200可以包括第一輸入/輸出電路方塊200A1和第二輸入/輸出電路方塊200A2、第一位址和命令電路方塊200B1、第一數據傳輸電路方塊200B2和第一記憶體單元核心方塊200C。同樣,上晶片400可以包括第三輸入/輸出電路方塊400A1和第四輸入/輸出電路方塊400A2、第二位址和命令電路方塊400B1、第二數據傳輸電路方塊400B2、和第二記憶體單元核心方塊400C。
設置在下晶片200和上晶片400之間的中介件300可以包括設置在中介件300的下表面300S2上的用於與下晶片200連接的下晶片連接墊350a和350b。另外,中介件300可以包括設置在中介件300的上表面300S1上的用於與上晶片400連接的第一上晶片連接墊310a和310b以及第二上晶片連接墊320a和320b。另外,中介件300可以包括用於與接合導線50a和50b連接的導線接合墊330a和330b,並且可以包括用於將第二上晶片連接墊320a和320b分別連接至導線接合墊330a和330b的第一重分佈線340a和340b。
首先,封裝基板100的電信號可以經由連接墊110a和110b,接合導線50a和50b,中介件300的導線接合墊330a和330b、第一重分佈線340a和340b和第二上晶片連接墊320a和320b,以及第三凸塊540輸入至上晶片400的第二上晶片墊420a和420b。在輸入電信號當中,沿著輸入電信號的第一上晶片內部佈線400I1的一些輸入信號可以穿過第三輸入/輸出電路方塊400A1並由第二位址和命令電路方塊400B1轉換為位址和命令信號,然後可以傳送至第二記憶體單元核心方塊400C。另外,在輸入電信號當中,沿著第二上晶片內部佈線400I2的一些其它輸入信號可以穿過第四輸入/輸出電路方塊400A2,並由第二數據傳輸電路方塊400B2轉換為數據信號,然後可以傳送至第二記憶體單元核心方塊400C。
此外,上晶片400的第一上晶片內部佈線400I1可以經由第一上晶片墊410a、第二凸塊530、中介件300的第一上晶片連接墊310a、中介件300的第一內部佈線360a1(包括通孔電極和重分佈線)、下晶片連接墊350b、第一凸塊520和第一下晶片墊210b連接至第一下晶片內部佈線200I1。因此,在封裝基板100的電信號當中,從上晶片400的第二位址和命令電路方塊400B1輸出的一些電信號可以輸入至下晶片200。輸入至下晶片200的電信號可以輸入至第一位址和命令電路方塊200B1並轉換成第一位址和命令信號,然後可以沿著第一下晶片內部佈線200I1傳送至第一記憶體單元核心方塊200C。結果,下晶片200能夠經由上晶片400接收封裝基板100的電信號,而無需電信號穿過第二下晶片墊220b、第一輸入/輸出電路方塊200A1、和第一位址和命令電路方塊200B1。
同樣地,上晶片400的第二上晶片內部佈線400I2可以經由第一上晶片墊410b、第二凸塊530、中介件300的第一上晶片連接墊310b、中介件300的第二內部佈線360b1(包括通孔電極和重分佈線)、下晶片連接墊350a、第一凸塊520、第一下晶片墊210a連接至第二下晶片內部佈線200I2。因此,在封裝基板100的電信號當中,從上晶片400的第二數據傳輸電路方塊400B2輸出的一些電信號可以輸入至下晶片200。輸入至下晶片200的電信號可以輸入至第一數據傳輸電路方塊200B2中並轉換為數據信號,然後可以沿著第二下晶片內部佈線200I2傳送至第一記憶體單元核心方塊200C。結果,下晶片200能夠經由上晶片400接收封裝基板100的電信號,而無需電信號穿過第二下晶片墊220a、第二輸入/輸出電路方塊200A2以及第一數據傳輸電路方塊200B2。
此外,再次參照圖6,從上晶片400的第二數據單元核心方塊400C輸出的電信號可以沿著第一上晶片內部佈線400I1穿過第二位址和命令電路方塊400B1和第三輸入/輸出電路方塊400A1,或者可以沿著第二上晶片內部佈線400I2穿過第二數據傳輸電路方塊400B2和第四輸入/輸出電路方塊400A2,從而到達第二上晶片墊420a或420b。此後,電信號可以從第二上晶片墊420a和420b輸出至中介件300。並且,電信號可以通過接合導線50a和50b從中介件300傳送至封裝基板100。
另外,從下晶片200的第一數據單元核心方塊200C輸出的電信號可以分別沿著第一下晶片內部佈線200I1和第二下晶片內部佈線200I2、第一中介件內部佈線360a1和第二中介件內部佈線360b1到達第一上晶片連接墊310a和310b。信號可以沿著第一上晶片內部佈線400I1和第二上晶片內部佈線400I2移動並到達上晶片400的第二上晶片墊420a和420b。此後,電信號可以從第二上晶片墊420a和420b輸出至中介件300,並且然後可以經由接合導線50a和50b傳送至封裝基板100。
電連接至下晶片200的第一下晶片內部佈線200I1和第二下晶片內部佈線200I2的第二下晶片墊220a和220b可以不電連接至封裝件外部的其它結構。因此,除了上晶片400之外,下晶片200可以不通過第一輸入/輸出電路方塊200A1和第二輸入/輸出電路方塊200A2電連接至其它外部晶片、封裝件或基板。
如上所述,本揭示的實施方式可以提供具有依序地堆疊在封裝基板上的下晶片、中介件和上晶片的半導體封裝件。在半導體封裝件中,中介件可以通過接合導線連接至封裝基板。上晶片可以通過凸塊連接至中介件,並且可以經由重分佈線和接合導線電連接至封裝基板。另外,上晶片可以使用中介件內部的通孔電極電連接至下晶片。
根據本揭示的實施方式,在上晶片和下晶片上能夠省略用於與封裝基板連接的重分佈線。因此,可以減少或抑制上晶片和下晶片的重分佈線與電路圖案層之間的寄生電容的產生。另外,上晶片可以被配置為經由中介件與封裝基板交換電信號,而下晶片可以被配置為經由上晶片與封裝基板交換電信號。因此,能夠省略下晶片和封裝基板之間的直接電連接,結果,能夠進一步減小或抑制由於電連接中所涉及的輸入/輸出電路而在下晶片中產生的寄生電容。
因此,在本揭示的實施方式中,可以提供一種能夠通過減少或抑制在堆疊在封裝基板上的半導體晶片中出現的不期望的寄生電容來提高半導體封裝件的信號傳輸速度的半導體封裝件結構。
已經出於示例性目的揭示了本揭示的實施方式。本領域技術人員將理解,在不脫離本揭示和所附請求項的範圍和精神的情況下,可以進行各種變型、添加和替換。
A:通孔電極佈置區
B:通孔電極佈置區
C:通孔電極佈置區
Cy-200:中心軸
Cy-300:中心軸
Cy-400:中心軸
D1:方向
D2:方向
F1:電信號路徑
F2:電信號路徑
L:部分
L200:長度
L300:長度
L400:長度
S1:水平間隔
S2:垂直間隔
W200:寬度
W300:寬度
W400:寬度
1:半導體封裝件
50a:接合導線
50b:接合導線
100:封裝基板
100S1:上表面
100S2:下表面
110a:下晶片連接墊
110b:下晶片連接墊
200:下晶片
200A1:第一輸入/輸出電路方塊
200A2:第二輸入/輸出電路方塊
200B1:第一位址和命令電路方塊
200B2:第一數據傳輸電路方塊
200C:第一記憶體單元核心方塊
200I1:第一下晶片內部佈線
200I2:第二下晶片內部佈線
200S1:上表面
200S2:下表面
210a:第一下晶片墊
210b:第一下晶片墊
220a:第二下晶片墊
220b:第二下晶片墊
300:中介件
300S1:上表面
300S2:下表面
310a:第一上晶片連接墊
310b:第一上晶片連接墊
320a:第二上晶片連接墊
320b:第二上晶片連接墊
330a:導線接合墊
330b:導線接合墊
340a:第一重分佈線
340b:第一重分佈線
350a:下晶片連接墊
350b:下晶片連接墊
360a:通孔電極
360a1:第一內部佈線
360b:通孔電極
360b1:第二內部佈線
371:第二重分佈線
372:第三重分佈線
381:第四重分佈線
382:第五重分佈線
400:上晶片
400A1:第三輸入/輸出電路方塊
400A2:第四輸入/輸出電路方塊
400B1:第二位址和命令電路方塊
400B2:第二數據傳輸電路方塊
400C:第二數據單元核心方塊
400S1:上表面
400S2:下表面
400I1:第一上晶片內部佈線
400I2:第二上晶片內部佈線
410a:第一上晶片墊
410b:第一上晶片墊
420a:第二上晶片墊
420b:第二上晶片墊
510:非導電黏合層
520:第一凸塊
530:第二凸塊
540:第三凸塊
550:連接結構
圖1是例示根據本揭示的實施方式的半導體封裝件的截面圖。
圖2是例示根據本揭示的實施方式的半導體晶片的平面圖。
圖3是例示根據本揭示的實施方式的半導體晶片的平面圖。
圖4A、圖4B和圖4C是例示根據本揭示的實施方式的中介件的圖。
圖5是例示根據本揭示的實施方式的在半導體晶片與封裝基板之間交換電信號的方法的示意圖。
圖6是例示根據本揭示的實施方式的半導體封裝件的內部電路配置的圖。
D1:方向
D2:方向
L:部分
1:半導體封裝件
50a:接合導線
50b:接合導線
100:封裝基板
100S1:上表面
100S2:下表面
110a:下晶片連接墊
110b:下晶片連接墊
200:下晶片
200S1:上表面
200S2:下表面
210a:第一下晶片墊
210b:第一下晶片墊
220a:第二下晶片墊
220b:第二下晶片墊
300:中介件
300S1:上表面
300S2:下表面
310a:第一上晶片連接墊
310b:第一上晶片連接墊
320a:第二上晶片連接墊
320b:第二上晶片連接墊
330a:導線接合墊
330b:導線接合墊
340a:第一重分佈線
340b:第一重分佈線
350a:下晶片連接墊
350b:下晶片連接墊
360a:通孔電極
360b:通孔電極
400:上晶片
400S1:上表面
400S2:下表面
410a:第一上晶片墊
410b:第一上晶片墊
420a:第二上晶片墊
420b:第二上晶片墊
510:非導電黏合層
520:第一凸塊
530:第二凸塊
540:第三凸塊
550:連接結構
Claims (24)
- 一種堆疊半導體封裝件,所述堆疊半導體封裝件包括: 封裝基板; 依序堆疊在所述封裝基板上的下晶片、中介件和上晶片;以及 接合導線,所述接合導線電連接所述封裝基板和所述中介件, 其中,所述中介件包括: 下晶片連接墊,所述下晶片連接墊設置在所述中介件的下表面上,其中,所述下晶片連接墊電連接至所述下晶片; 第一上晶片連接墊和第二上晶片連接墊,所述第一上晶片連接墊和所述第二上晶片連接墊設置在所述中介件的上表面上,其中,所述第一上晶片連接墊和所述第二上晶片連接墊電連接至所述上晶片; 導線接合墊,所述導線接合墊設置在所述中介件的所述上表面上並接合至所述接合導線; 第一重分佈線,所述第一重分佈線設置在所述中介件的所述上表面上,所述第一重分佈線將所述第二上晶片連接墊電連接至所述導線接合墊;以及 通孔電極,所述通孔電極將所述下晶片連接墊電連接至所述第一上晶片連接墊。
- 根據請求項1所述的堆疊半導體封裝件, 其中,所述下晶片包括電連接至所述下晶片連接墊的第一下晶片墊, 其中,所述下晶片包括與所述第一下晶片墊橫向相鄰設置的第二下晶片墊,其中,所述第二下晶片墊未連接至所述下晶片連接墊且未連接至所述封裝基板,並且 其中,所述上晶片包括電連接至所述第一上晶片連接墊的第一上晶片墊和電連接至所述第二上晶片連接墊的第二上晶片墊。
- 根據請求項2所述的堆疊半導體封裝件,所述堆疊半導體封裝件還包括: 第一凸塊,所述第一凸塊設置在所述第一下晶片連接墊和所述第一下晶片墊之間; 第二凸塊,所述第二凸塊設置在所述第一上晶片連接墊和所述第一上晶片墊之間;以及 第三凸塊,所述第三凸塊設置在所述第二上晶片連接墊和所述第二上晶片墊之間, 其中,所述第二凸塊和所述第三凸塊具有基本相同的尺寸。
- 根據請求項2所述的堆疊半導體封裝件,其中,所述第一上晶片墊和所述第二上晶片墊具有基本相同的尺寸。
- 根據請求項2所述的堆疊半導體封裝件, 其中,所述上晶片通過所述中介件電連接至所述封裝基板,並且 其中,所述下晶片藉由所述中介件的所述通孔電極和所述上晶片電連接至所述封裝基板。
- 根據請求項2所述的堆疊半導體封裝件, 其中,所述下晶片包括: 第一位址和命令電路方塊,所述第一位址和命令電路方塊電連接至所述第一下晶片墊中的第一個下晶片墊; 第一數據傳輸電路方塊,所述第一數據傳輸電路方塊電連接至所述第一下晶片墊中的第二個下晶片墊; 第一輸入/輸出電路方塊,所述第一輸入/輸出電路方塊電連接至所述第二下晶片墊中的第一個下晶片墊並且電連接至所述第一位址和命令電路方塊; 第二輸入/輸出電路方塊,所述第二輸入/輸出電路方塊電連接至所述第二下晶片墊中的第二個下晶片墊並且電連接至所述第一數據傳輸電路方塊;以及 第一記憶體單元核心方塊,所述第一記憶體單元核心方塊電連接至所述第一位址和命令電路方塊並且電連接至所述第一數據傳輸電路方塊,並且 其中,所述上晶片包括: 第二位址和命令電路方塊,所述第二位址和命令電路方塊電連接至所述第一上晶片墊中的第一個上晶片墊; 第二數據傳輸電路方塊,所述第二數據傳輸電路方塊電連接至所述第一上晶片墊中的第二個上晶片墊; 第三輸入/輸出電路方塊,所述第三輸入/輸出電路方塊電連接至所述第二上晶片墊中的第一個上晶片墊並且電連接至所述第二位址和命令電路方塊; 第四輸入/輸出電路方塊,所述第四輸入/輸出電路方塊電連接至所述第二上晶片墊中的第二個上晶片墊並且電連接至所述第二數據傳輸電路方塊;以及 第二記憶體單元核心方塊,所述第二記憶體單元核心方塊電連接至所述第二位址和命令電路方塊並且電連接至所述第二數據傳輸電路方塊。
- 根據請求項6所述的堆疊半導體封裝件, 其中,來自所述封裝基板的第一電信號通過所述接合導線中的第一接合導線、所述導線接合墊中的第一導線接合墊、所述第一重分佈線中的第一條重分佈線、所述第二上晶片連接墊中的第一個上晶片連接墊和所述第二上晶片墊中的第一個上晶片墊輸入至所述第三輸入/輸出電路方塊, 其中,來自所述封裝基板的第二電信號通過所述接合導線中的第二接合導線、所述導線接合墊中的第二導線接合墊、所述第一重分佈線中的第二條重分佈線、所述第二上晶片連接墊中的第二個上晶片連接墊和所述第二上晶片墊中的第二個上晶片墊輸入至所述第四輸入/輸出電路方塊, 其中,所述第一電信號使用所述上晶片的內部佈線通過所述第二位址和命令電路方塊被傳送至所述上晶片的所述第二記憶體單元核心方塊,並且 其中,所述第二電信號使用所述上晶片的所述內部佈線通過所述第二數據傳輸電路方塊被傳送至所述上晶片的所述第二記憶體單元核心方塊。
- 根據請求項7所述的堆疊半導體封裝件, 其中,來自所述封裝基板的所述第一電信號被傳送至所述第一下晶片墊中的第二個下晶片墊, 其中,來自所述封裝基板的所述第二電信號被傳送至所述第一下晶片墊中的第一個下晶片墊, 其中,所述第一電信號使用所述下晶片的內部佈線通過所述第一位址和命令電路方塊被傳送至所述下晶片的所述第一記憶體單元核心方塊,並且 其中,所述第二電信號使用所述下晶片的所述內部佈線通過所述第一數據傳輸電路方塊被傳送至所述下晶片的所述第一記憶體單元核心方塊。
- 根據請求項1所述的堆疊半導體封裝件,其中,所述中介件包括超出所述上晶片的側邊緣的至少一個橫向突出區域。
- 根據請求項9所述的堆疊半導體封裝件,其中,所述導線接合墊設置在所述中介件的所述至少一個橫向突出區域上。
- 根據請求項1所述的堆疊半導體封裝件,其中,所述第一上晶片連接墊、所述第二上晶片連接墊、所述導線接合墊、所述下晶片連接墊以及所述通孔電極各自以相對於所述中介件的中心軸成對對稱的方式設置。
- 根據請求項11所述的堆疊半導體封裝件, 其中,所述中介件包括相對於所述中介件的所述中心軸彼此對稱的第一上左墊和第一上右墊作為所述第一上晶片連接墊,並且包括位於緊接在所述第一上左墊下方的下左墊以及位於緊接在所述第一上右墊下方的下右墊作為所述下晶片連接墊,並且 其中,所述第一上左墊通過第一通孔電極電連接至所述下右墊,並且所述第一上右墊通過第二通孔電極電連接至所述下左墊。
- 根據請求項12所述的堆疊半導體封裝件,其中,所述中介件具有在所述中介件的所述上表面上將所述第一上左墊電連接至所述第一通孔電極的第二重分佈線以及將所述第二通孔電極電連接至所述上右墊的第三重分佈線,並且具有在所述中介件的所述下表面上將所述下右墊電連接至所述第一通孔電極的第四重分佈線以及將所述第二通孔電極電連接至所述下左墊的第五重分佈線。
- 一種堆疊半導體封裝件,所述堆疊半導體封裝件包括: 封裝基板; 依序堆疊在所述封裝基板上的下晶片、中介件和上晶片;以及 接合導線,所述接合導線電連接所述封裝基板和所述中介件, 其中,所述中介件包括: 通孔電極,所述通孔電極將所述下晶片電連接至所述上晶片;以及 第一重分佈線,所述第一重分佈線將所述上晶片電連接至所述接合導線。
- 根據請求項14所述的堆疊半導體封裝件, 其中,所述上晶片通過所述中介件電連接至所述封裝基板,並且 其中,所述下晶片藉由所述中介件的所述通孔電極和所述上晶片電連接至所述封裝基板。
- 根據請求項14所述的堆疊半導體封裝件, 其中,所述中介件還包括: 下晶片連接墊,所述下晶片連接墊設置在所述中介件的下表面上,其中,所述下晶片連接墊電連接至所述下晶片; 第一上晶片連接墊和第二上晶片連接墊,所述第一上晶片連接墊和所述第二上晶片連接墊設置在所述中介件的上表面上,其中,所述第一上晶片連接墊和所述第二上晶片連接墊電連接至所述上晶片;以及 導線接合墊,所述導線接合墊設置在所述中介件的所述上表面上並接合至所述接合導線。
- 根據請求項16所述的堆疊半導體封裝件, 其中,所述通孔電極將所述下晶片連接墊電連接至所述第一上晶片連接墊,並且 其中,所述第一重分佈線將所述第二上晶片連接墊電連接至所述導線接合墊。
- 根據請求項17所述的堆疊半導體封裝件,其中,所述第一上晶片連接墊、所述第二上晶片連接墊、所述導線接合墊、所述下晶片連接墊和所述通孔電極各自以相對於所述中介件的中心軸成對對稱的方式設置。
- 根據請求項18所述的堆疊半導體封裝件, 其中,所述中介件包括相對於所述中介件的所述中心軸彼此對稱的第一上左墊和第一上右墊作為所述第一上晶片連接墊,並且包括位於緊接在所述第一上左墊下方的下左墊和位於緊接在所述第一上右墊下方的下右墊作為所述下晶片連接墊,並且 其中,所述第一上左墊通過第一通孔電極電連接至所述下右墊,並且所述第一上右墊通過第二通孔電極電連接至所述下左墊。
- 根據請求項19所述的堆疊半導體封裝件, 其中,所述中介件具有在所述中介件的所述上表面上將所述第一上左墊電連接至所述第一通孔電極的第二重分佈線以及將所述第二通孔電極電連接至所述上右墊的第三重分佈線,並且具有在所述中介件的所述下表面上將所述下右墊電連接至所述第一通孔電極的第四重分佈線以及將所述第二通孔電極電連接至所述下左墊的第五重分佈線。
- 根據請求項16所述的堆疊半導體封裝件,其中,所述導線接合墊設置在所述中介件的超出所述上晶片的邊緣橫向延伸的區域上。
- 根據請求項16所述的堆疊半導體封裝件, 其中,所述下晶片包括電連接至所述下晶片連接墊的第一下晶片墊和與所述第一下晶片墊橫向相鄰設置的第二下晶片墊,其中,所述第二下晶片墊未連接至所述下晶片連接墊並且未連接至所述封裝基板,並且 其中,所述上晶片包括電連接至所述第一上晶片連接墊的第一上晶片墊和電連接至所述第二上晶片連接墊的第二上晶片墊。
- 根據請求項22所述的堆疊半導體封裝件,所述堆疊半導體封裝件還包括: 第一凸塊,所述第一凸塊設置在所述下晶片連接墊和所述第一下晶片墊之間; 第二凸塊,所述第二凸塊設置在所述第一上晶片連接墊和所述第一上晶片墊之間;以及 第三凸塊,所述第三凸塊設置在所述第二上晶片連接墊和所述第二上晶片墊之間, 其中,所述第二凸塊和所述第三凸塊具有基本相同的尺寸。
- 根據請求項22所述的堆疊半導體封裝件,其中,所述第一上晶片墊和所述第二上晶片墊具有基本相同的尺寸。
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KR1020190074338A KR20200145387A (ko) | 2019-06-21 | 2019-06-21 | 인터포저를 포함하는 적층 반도체 패키지 |
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TWI799215B (zh) * | 2021-12-23 | 2023-04-11 | 南亞科技股份有限公司 | 具有複合中間互連器的半導體元件 |
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WO2021133741A1 (en) | 2019-12-23 | 2021-07-01 | Invensas Bonding Technologies, Inc. | Electrical redundancy for bonded structures |
US11721653B2 (en) | 2019-12-23 | 2023-08-08 | Adeia Semiconductor Bonding Technologies Inc. | Circuitry for electrical redundancy in bonded structures |
US11469216B2 (en) * | 2020-03-27 | 2022-10-11 | Nanya Technology Corporation | Dual-die semiconductor package and manufacturing method thereof |
US20230100032A1 (en) * | 2021-09-24 | 2023-03-30 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with active interposer |
US20230109629A1 (en) * | 2021-10-01 | 2023-04-06 | Microchip Technology Incorporated | Electronic device including interposers bonded to each other |
KR20240037712A (ko) * | 2022-09-15 | 2024-03-22 | 삼성전자주식회사 | 반도체 패키지 |
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US7576435B2 (en) * | 2007-04-27 | 2009-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-cost and ultra-fine integrated circuit packaging technique |
US8421244B2 (en) * | 2007-05-08 | 2013-04-16 | Samsung Electronics Co., Ltd. | Semiconductor package and method of forming the same |
US7553752B2 (en) * | 2007-06-20 | 2009-06-30 | Stats Chippac, Ltd. | Method of making a wafer level integration package |
US10354984B2 (en) * | 2015-05-27 | 2019-07-16 | Bridge Semiconductor Corporation | Semiconductor assembly with electromagnetic shielding and thermally enhanced characteristics and method of making the same |
US10121768B2 (en) * | 2015-05-27 | 2018-11-06 | Bridge Semiconductor Corporation | Thermally enhanced face-to-face semiconductor assembly with built-in heat spreader and method of making the same |
KR102258739B1 (ko) * | 2014-03-26 | 2021-06-02 | 삼성전자주식회사 | 하이브리드 적층 구조를 갖는 반도체 소자 및 그 제조방법 |
KR20180006229A (ko) * | 2016-07-08 | 2018-01-17 | 삼성전자주식회사 | 스택 구조의 반도체 메모리 패키지, 메모리 장치 및 반도체 메모리 시스템 |
US10937741B2 (en) * | 2018-11-16 | 2021-03-02 | STATS ChipPAC Pte. Ltd. | Molded laser package with electromagnetic interference shield and method of making |
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- 2019-10-17 TW TW108137487A patent/TW202101726A/zh unknown
- 2019-10-22 US US16/660,671 patent/US20200402959A1/en not_active Abandoned
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TWI799215B (zh) * | 2021-12-23 | 2023-04-11 | 南亞科技股份有限公司 | 具有複合中間互連器的半導體元件 |
US11881446B2 (en) | 2021-12-23 | 2024-01-23 | Nanya Technology Corporation | Semiconductor device with composite middle interconnectors |
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